more LA signals
[raggedstone] / dhwk / source / top.vhd
CommitLineData
377c0242 1-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
62946980 11entity dhwk is\r
377c0242 12 Port ( KONST_1 : In std_logic;\r
13 PCI_CBEn : In std_logic_vector (3 downto 0);\r
14 PCI_CLOCK : In std_logic;\r
15 PCI_FRAMEn : In std_logic;\r
16 PCI_IDSEL : In std_logic;\r
17 PCI_IRDYn : In std_logic;\r
18 PCI_RSTn : In std_logic;\r
257c0fc1 19-- SERIAL_IN : In std_logic;\r
20-- SPC_RDY_IN : In std_logic;\r
377c0242 21 TAST_RESn : In std_logic;\r
22 TAST_SETn : In std_logic;\r
bba7a6d5 23 LED_2 : out std_logic;\r
24 LED_3 : out std_logic;\r
25 LED_4 : out std_logic;\r
26 LED_5 : out std_logic;\r
377c0242 27 PCI_AD : InOut std_logic_vector (31 downto 0);\r
28 PCI_PAR : InOut std_logic;\r
29 PCI_DEVSELn : Out std_logic;\r
30 PCI_INTAn : Out std_logic;\r
31 PCI_PERRn : Out std_logic;\r
32 PCI_SERRn : Out std_logic;\r
33 PCI_STOPn : Out std_logic;\r
34 PCI_TRDYn : Out std_logic;\r
7b87d14d 35 PCI_REQn : Out std_logic;\r
36 PCI_GNTn : In std_logic;\r
257c0fc1 37-- SERIAL_OUT : Out std_logic;\r
38-- SPC_RDY_OUT : Out std_logic;\r
377c0242 39 TB_IDSEL : Out std_logic;\r
40 TB_nDEVSEL : Out std_logic;\r
41 TB_nINTA : Out std_logic );\r
62946980 42end dhwk;\r
377c0242 43\r
62946980 44architecture SCHEMATIC of dhwk is\r
377c0242 45\r
46 SIGNAL gnd : std_logic := '0';\r
47 SIGNAL vcc : std_logic := '1';\r
48\r
49 signal READ_XX7_6 : std_logic;\r
50 signal RESERVE : std_logic;\r
51 signal SR_ERROR : std_logic;\r
52 signal R_ERROR : std_logic;\r
53 signal S_ERROR : std_logic;\r
54 signal WRITE_XX3_2 : std_logic;\r
55 signal WRITE_XX5_4 : std_logic;\r
56 signal WRITE_XX7_6 : std_logic;\r
57 signal READ_XX1_0 : std_logic;\r
58 signal READ_XX3_2 : std_logic;\r
59 signal INTAn : std_logic;\r
60 signal TRDYn : std_logic;\r
61 signal READ_XX5_4 : std_logic;\r
62 signal DEVSELn : std_logic;\r
63 signal FIFO_RDn : std_logic;\r
64 signal WRITE_XX1_0 : std_logic;\r
65 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
66 signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
67 signal INT_REG : std_logic_vector (7 downto 0);\r
68 signal REVISON_ID : std_logic_vector (7 downto 0);\r
69 signal VENDOR_ID : std_logic_vector (15 downto 0);\r
70 signal READ_SEL : std_logic_vector (1 downto 0);\r
71 signal AD_REG : std_logic_vector (31 downto 0);\r
72 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
2825d08e 73 signal R_EFn : std_logic;\r
74 signal R_FFn : std_logic;\r
75 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
76 signal R_HFn : std_logic;\r
77 signal S_EFn : std_logic;\r
78 signal S_FFn : std_logic;\r
79 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
80 signal S_HFn : std_logic;\r
81 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
82 signal R_FIFO_READn : std_logic;\r
83 signal R_FIFO_RESETn : std_logic;\r
84 signal R_FIFO_RTn : std_logic;\r
85 signal R_FIFO_WRITEn : std_logic;\r
86 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
87 signal S_FIFO_READn : std_logic;\r
88 signal S_FIFO_RESETn : std_logic;\r
89 signal S_FIFO_RTn : std_logic;\r
90 signal S_FIFO_WRITEn : std_logic;\r
257c0fc1 91 signal SERIAL_IN : std_logic;\r
92 signal SPC_RDY_IN : std_logic;\r
93 signal SERIAL_OUT : std_logic;\r
94 signal SPC_RDY_OUT : std_logic;\r
7b87d14d 95 signal watch_PCI_INTAn : std_logic;\r
96 signal watch_PCI_TRDYn : std_logic;\r
97 signal watch_PCI_STOPn : std_logic;\r
98 signal watch_PCI_SERRn : std_logic;\r
99 signal watch_PCI_PERRn : std_logic;\r
100 signal watch_PCI_REQn : std_logic;\r
1afff8d4 101 signal control0 : std_logic_vector(35 downto 0);\r
1cc8dbeb 102 signal data : std_logic_vector(95 downto 0);\r
103 signal trig0 : std_logic_vector(31 downto 0);\r
377c0242 104\r
105 component MESS_1_TB\r
106 Port ( DEVSELn : In std_logic;\r
107 INTAn : In std_logic;\r
108 KONST_1 : In std_logic;\r
109 PCI_IDSEL : In std_logic;\r
110 REG_OUT_XX7 : In std_logic_vector (7 downto 0);\r
111 TB_DEVSELn : Out std_logic;\r
112 TB_INTAn : Out std_logic;\r
113 TB_PCI_IDSEL : Out std_logic );\r
114 end component;\r
115\r
116 component VEN_REV_ID\r
117 Port ( REV_ID : Out std_logic_vector (7 downto 0);\r
118 VEN_ID : Out std_logic_vector (15 downto 0) );\r
119 end component;\r
120\r
121 component INTERRUPT\r
122 Port ( INT_IN_0 : In std_logic;\r
123 INT_IN_1 : In std_logic;\r
124 INT_IN_2 : In std_logic;\r
125 INT_IN_3 : In std_logic;\r
126 INT_IN_4 : In std_logic;\r
127 INT_IN_5 : In std_logic;\r
128 INT_IN_6 : In std_logic;\r
129 INT_IN_7 : In std_logic;\r
130 INT_MASKE : In std_logic_vector (7 downto 0);\r
131 INT_RES : In std_logic_vector (7 downto 0);\r
132 PCI_CLOCK : In std_logic;\r
133 PCI_RSTn : In std_logic;\r
134 READ_XX5_4 : In std_logic;\r
135 RESET : In std_logic;\r
136 TAST_RESn : In std_logic;\r
137 TAST_SETn : In std_logic;\r
138 TRDYn : In std_logic;\r
139 INT_REG : Out std_logic_vector (7 downto 0);\r
140 INTAn : Out std_logic;\r
141 PCI_INTAn : Out std_logic );\r
142 end component;\r
143\r
144 component FIFO_CONTROL\r
145 Port ( FIFO_RDn : In std_logic;\r
146 FLAG_IN_0 : In std_logic;\r
147 FLAG_IN_4 : In std_logic;\r
148 HOLD : In std_logic;\r
149 KONST_1 : In std_logic;\r
150 PCI_CLOCK : In std_logic;\r
151 PSC_ENABLE : In std_logic;\r
152 R_EFn : In std_logic;\r
153 R_FFn : In std_logic;\r
154 R_HFn : In std_logic;\r
155 RESET : In std_logic;\r
156 S_EFn : In std_logic;\r
157 S_FFn : In std_logic;\r
158 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
159 S_HFn : In std_logic;\r
160 SERIAL_IN : In std_logic;\r
161 SPC_ENABLE : In std_logic;\r
162 SPC_RDY_IN : In std_logic;\r
163 WRITE_XX1_0 : In std_logic;\r
164 R_ERROR : Out std_logic;\r
165 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
166 R_FIFO_READn : Out std_logic;\r
167 R_FIFO_RESETn : Out std_logic;\r
168 R_FIFO_RETRANSMITn : Out std_logic;\r
169 R_FIFO_WRITEn : Out std_logic;\r
170 RESERVE : Out std_logic;\r
171 S_ERROR : Out std_logic;\r
172 S_FIFO_READn : Out std_logic;\r
173 S_FIFO_RESETn : Out std_logic;\r
174 S_FIFO_RETRANSMITn : Out std_logic;\r
175 S_FIFO_WRITEn : Out std_logic;\r
176 SERIAL_OUT : Out std_logic;\r
177 SPC_RDY_OUT : Out std_logic;\r
178 SR_ERROR : Out std_logic;\r
179 SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
180 end component;\r
181\r
182 component PCI_TOP\r
183 Port ( FLAG : In std_logic_vector (7 downto 0);\r
184 INT_REG : In std_logic_vector (7 downto 0);\r
185 PCI_CBEn : In std_logic_vector (3 downto 0);\r
186 PCI_CLOCK : In std_logic;\r
187 PCI_FRAMEn : In std_logic;\r
188 PCI_IDSEL : In std_logic;\r
189 PCI_IRDYn : In std_logic;\r
190 PCI_RSTn : In std_logic;\r
191 R_FIFO_Q : In std_logic_vector (7 downto 0);\r
192 REVISON_ID : In std_logic_vector (7 downto 0);\r
193 VENDOR_ID : In std_logic_vector (15 downto 0);\r
194 PCI_AD : InOut std_logic_vector (31 downto 0);\r
195 PCI_PAR : InOut std_logic;\r
196 AD_REG : Out std_logic_vector (31 downto 0);\r
197 DEVSELn : Out std_logic;\r
198 FIFO_RDn : Out std_logic;\r
199 PCI_DEVSELn : Out std_logic;\r
200 PCI_PERRn : Out std_logic;\r
201 PCI_SERRn : Out std_logic;\r
202 PCI_STOPn : Out std_logic;\r
203 PCI_TRDYn : Out std_logic;\r
204 READ_SEL : Out std_logic_vector (1 downto 0);\r
205 READ_XX1_0 : Out std_logic;\r
206 READ_XX3_2 : Out std_logic;\r
207 READ_XX5_4 : Out std_logic;\r
208 READ_XX7_6 : Out std_logic;\r
209 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
210 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
211 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
212 TRDYn : Out std_logic;\r
213 WRITE_XX1_0 : Out std_logic;\r
214 WRITE_XX3_2 : Out std_logic;\r
215 WRITE_XX5_4 : Out std_logic;\r
216 WRITE_XX7_6 : Out std_logic );\r
217 end component;\r
218\r
078adaa6 219component dhwk_fifo\r
2825d08e 220 port (\r
221 clk: IN std_logic;\r
222 din: IN std_logic_VECTOR(7 downto 0);\r
223 rd_en: IN std_logic;\r
224 rst: IN std_logic;\r
225 wr_en: IN std_logic;\r
226 almost_empty: OUT std_logic;\r
227 almost_full: OUT std_logic;\r
228 dout: OUT std_logic_VECTOR(7 downto 0);\r
229 empty: OUT std_logic;\r
230 full: OUT std_logic;\r
231 prog_full: OUT std_logic);\r
232end component;\r
233\r
1afff8d4 234component icon\r
235port\r
236 (\r
237 control0 : out std_logic_vector(35 downto 0)\r
238 );\r
239end component;\r
240\r
241 component ila\r
242 port\r
243 (\r
244 control : in std_logic_vector(35 downto 0);\r
245 clk : in std_logic;\r
1cc8dbeb 246 data : in std_logic_vector(95 downto 0);\r
247 trig0 : in std_logic_vector(31 downto 0)\r
1afff8d4 248 );\r
249 end component;\r
250\r
251\r
377c0242 252begin\r
7b87d14d 253 watch_PCI_REQn <= '1';\r
257c0fc1 254 SERIAL_IN <= SERIAL_OUT;\r
255 SPC_RDY_IN <= SPC_RDY_OUT;\r
7b87d14d 256 LED_2 <= not PCI_RSTn;\r
257 LED_3 <= PCI_IDSEL;\r
258 LED_4 <= not PCI_FRAMEn;\r
259 LED_5 <= not watch_PCI_INTAn;\r
260 PCI_INTAn <= watch_PCI_INTAn;\r
a570ee15 261 trig0(31 downto 0) <= (\r
7b87d14d 262 0 => watch_PCI_INTAn,\r
a570ee15 263 1 => R_FIFO_READn,\r
264 2 => R_FIFO_WRITEn,\r
265 3 => S_FIFO_READn,\r
266 4 => S_FIFO_WRITEn, \r
7b87d14d 267 5 => PCI_RSTn,\r
a570ee15 268 16 => PCI_AD(0),\r
269 17 => PCI_AD(1),\r
270 18 => PCI_AD(2),\r
271 19 => PCI_AD(3),\r
272 20 => PCI_AD(4),\r
273 21 => PCI_AD(5),\r
274 22 => PCI_AD(6),\r
275 23 => PCI_AD(7),\r
276 27 => PCI_FRAMEn,\r
277 28 => PCI_CBEn(0),\r
278 29 => PCI_CBEn(1),\r
279 30 => PCI_CBEn(2),\r
280 31 => PCI_CBEn(3),\r
281 others => '0');\r
282\r
7b87d14d 283 data(0) <= watch_PCI_INTAn;\r
a76e12bd 284 data(1) <= R_EFn;\r
285 data(2) <= R_HFn;\r
286 data(3) <= R_FFn;\r
287 data(4) <= R_FIFO_READn;\r
288 data(5) <= R_FIFO_RESETn;\r
289 data(6) <= R_FIFO_RTn;\r
290 data(7) <= R_FIFO_WRITEn;\r
291 data(8) <= S_EFn;\r
292 data(9) <= S_HFn;\r
293 data(10) <= S_FFn;\r
294 data(11) <= S_FIFO_READn;\r
295 data(12) <= S_FIFO_RESETn;\r
296 data(13) <= S_FIFO_RTn;\r
297 data(14) <= S_FIFO_WRITEn;\r
298 data(15) <= SERIAL_IN;\r
299 data(16) <= SPC_RDY_IN;\r
300 data(17) <= SERIAL_OUT;\r
301 data(18) <= SPC_RDY_OUT;\r
e6724389 302 data(26 downto 19) <= S_FIFO_Q_OUT;\r
f822aceb 303 data(34 downto 27) <= R_FIFO_Q_OUT;\r
1cc8dbeb 304 data(66 downto 35) <= PCI_AD(31 downto 0);\r
8985684b 305 data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
a570ee15 306 data(71) <= PCI_FRAMEn;\r
7b87d14d 307 data(72) <= PCI_IDSEL;\r
308 PCI_TRDYn <= watch_PCI_TRDYn;\r
309 data(73) <= watch_PCI_TRDYn;\r
310 data(74) <= PCI_IRDYn;\r
311 PCI_STOPn <= watch_PCI_STOPn;\r
312 data(75) <= watch_PCI_STOPn;\r
313 PCI_SERRn <= watch_PCI_SERRn;\r
314 data(76) <= watch_PCI_SERRn;\r
315 PCI_PERRn <= watch_PCI_PERRn;\r
316 data(77) <= watch_PCI_PERRn;\r
317 PCI_REQn <= watch_PCI_REQn;\r
318 data(78) <= watch_PCI_REQn;\r
319 data(79) <= PCI_GNTn;\r
377c0242 320\r
321 I19 : MESS_1_TB\r
322 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
323 PCI_IDSEL=>PCI_IDSEL,\r
324 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
325 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
326 TB_PCI_IDSEL=>TB_IDSEL );\r
327 I18 : VEN_REV_ID\r
328 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
329 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
330 I16 : INTERRUPT\r
331 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
332 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
333 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
334 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
335 INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
336 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
337 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
338 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
339 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
7b87d14d 340 INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);\r
377c0242 341 I14 : FIFO_CONTROL\r
342 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
343 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
344 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
345 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
346 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
347 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
348 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
349 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
350 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
351 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
352 R_FIFO_READn=>R_FIFO_READn,\r
353 R_FIFO_RESETn=>R_FIFO_RESETn,\r
354 R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
355 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
356 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
357 S_FIFO_RESETn=>S_FIFO_RESETn,\r
358 S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
359 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
360 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
361 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
362 I1 : PCI_TOP\r
363 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
364 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
365 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
366 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
367 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
368 PCI_RSTn=>PCI_RSTn,\r
369 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
370 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
371 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
372 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
373 PCI_PAR=>PCI_PAR,\r
374 AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
375 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
7b87d14d 376 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,\r
377 PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,\r
378 PCI_TRDYn=>watch_PCI_TRDYn,\r
377c0242 379 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
380 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
381 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
382 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
383 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
384 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
385 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
386 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
387 WRITE_XX7_6=>WRITE_XX7_6 );\r
388\r
078adaa6 389receive_fifo : dhwk_fifo\r
2825d08e 390 port map (\r
391 clk => PCI_CLOCK,\r
392 din => R_FIFO_D_IN,\r
393 rd_en => not R_FIFO_READn,\r
394 rst => not R_FIFO_RESETn,\r
395 wr_en => not R_FIFO_WRITEn,\r
396 dout => R_FIFO_Q_OUT,\r
397 empty => R_EFn,\r
398 full => R_FFn,\r
399 prog_full => R_HFn);\r
400\r
078adaa6 401send_fifo : dhwk_fifo\r
2825d08e 402 port map (\r
403 clk => PCI_CLOCK,\r
404 din => S_FIFO_D_IN,\r
405 rd_en => not S_FIFO_READn,\r
406 rst => not S_FIFO_RESETn,\r
407 wr_en => not S_FIFO_WRITEn,\r
408 dout => S_FIFO_Q_OUT,\r
409 empty => S_EFn,\r
410 full => S_FFn,\r
411 prog_full => S_HFn);\r
1afff8d4 412\r
413 i_icon : icon\r
414 port map\r
415 (\r
416 control0 => control0\r
417 );\r
418\r
419 i_ila : ila\r
420 port map\r
421 (\r
422 control => control0,\r
423 clk => PCI_CLOCK,\r
424 data => data,\r
425 trig0 => trig0\r
426 );\r
377c0242 427end SCHEMATIC;\r
Impressum, Datenschutz