[raggedstone] / dhwk / source / pci / config_space_header.vhd

-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity CONFIG_SPACE_HEADER is
        Port ( AD_REG : In std_logic_vector (31 downto 0);
               ADDR_REG : In std_logic_vector (31 downto 0);
               CBE_REGn : In std_logic_vector (3 downto 0);
               CF_RD_COM : In std_logic;
               CF_WR_COM : In std_logic;
               IRDY_REGn : In std_logic;
               PCI_CLOCK : In std_logic;
               PCI_RSTn : In std_logic;
               PERR : In std_logic;
               REVISION_ID : In std_logic_vector (7 downto 0);
               SERR : In std_logic;
               TRDYn : In std_logic;
               VENDOR_ID : In std_logic_vector (15 downto 0);
               CONF_DATA : Out std_logic_vector (31 downto 0);
               CONF_DATA_04H : Out std_logic_vector (31 downto 0);
               CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
end CONFIG_SPACE_HEADER;

architecture SCHEMATIC of CONFIG_SPACE_HEADER is

        SIGNAL gnd : std_logic := '0';
        SIGNAL vcc : std_logic := '1';

        signal CONF_WR_04H : std_logic;
        signal CONF_WR_10H : std_logic;
        signal CONF_WR_3CH : std_logic;
        signal CONF_READ_SEL : std_logic_vector (2 downto 0);
        signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
        signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
        signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
        signal CONF_DATA_08H : std_logic_vector (31 downto 0);
        signal CONF_DATA_00H : std_logic_vector (31 downto 0);

        component CONFIG_MUX_0
                Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);
                       CONF_DATA_04H : In std_logic_vector (31 downto 0);
                       CONF_DATA_08H : In std_logic_vector (31 downto 0);
                       CONF_DATA_10H : In std_logic_vector (31 downto 0);
                       CONF_DATA_3CH : In std_logic_vector (31 downto 0);
                       READ_SEL : In std_logic_vector (2 downto 0);
                       CONF_DATA : Out std_logic_vector (31 downto 0) );
        end component;

        component CONFIG_RD_0
                Port ( ADDR_REG : In std_logic_vector (31 downto 0);
                       CF_RD_COM : In std_logic;
                       READ_SEL : Out std_logic_vector (2 downto 0) );
        end component;

        component CONFIG_WR_0
                Port ( ADDR_REG : In std_logic_vector (31 downto 0);
                       CF_WR_COM : In std_logic;
                       IRDY_REGn : In std_logic;
                       TRDYn : In std_logic;
                       CONF_WR_04H : Out std_logic;
                       CONF_WR_10H : Out std_logic;
                       CONF_WR_3CH : Out std_logic );
        end component;

        component CONFIG_3CH
                Port ( AD_REG : In std_logic_vector (31 downto 0);
                       CBE_REGn : In std_logic_vector (3 downto 0);
                       CONF_WR_3CH : In std_logic;
                       PCI_CLOCK : In std_logic;
                       PCI_RSTn : In std_logic;
                       CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
        end component;

        component CONFIG_10H
                Port ( AD_REG : In std_logic_vector (31 downto 0);
                       CBE_REGn : In std_logic_vector (3 downto 0);
                       CONF_WR_10H : In std_logic;
                       PCI_CLOCK : In std_logic;
                       PCI_RSTn : In std_logic;
                       CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
        end component;

        component CONFIG_08H
                Port ( REVISION_ID : In std_logic_vector (7 downto 0);
                       CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
        end component;

        component CONFIG_00H
                Port ( VENDOR_ID : In std_logic_vector (15 downto 0);
                       CONF_DATA_00H : Out std_logic_vector (31 downto 0) );
        end component;

        component CONFIG_04H
                Port ( AD_REG : In std_logic_vector (31 downto 0);
                       CBE_REGn : In std_logic_vector (3 downto 0);
                       CONF_WR_04H : In std_logic;
                       PCI_CLOCK : In std_logic;
                       PCI_RSTn : In std_logic;
                       PERR : In std_logic;
                       SERR : In std_logic;
                       CONF_DATA_04H : Out std_logic_vector (31 downto 0) );
        end component;

begin

        CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
        CONF_DATA_10H <= CONF_DATA_10H_DUMMY;

        I10 : CONFIG_MUX_0
        Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
        CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
        CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
        CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
        CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
        READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
        CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
        I9 : CONFIG_RD_0
        Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                   CF_RD_COM=>CF_RD_COM,
                   READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
        I8 : CONFIG_WR_0
        Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
                   CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
                   TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
                   CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
        I6 : CONFIG_3CH
        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
        CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
        PCI_RSTn=>PCI_RSTn,
        CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
        I5 : CONFIG_10H
        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
        CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
        PCI_RSTn=>PCI_RSTn,
        CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
        I4 : CONFIG_08H
        Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
        CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
        I3 : CONFIG_00H
        Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
        CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
        I2 : CONFIG_04H
        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
        CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
        PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
        CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );

end SCHEMATIC;
Commit	Line	Data
11b038c2	1	-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
11b038c2	2
696ded12	3	LIBRARY ieee;
	4
	5	USE ieee.std_logic_1164.ALL;
	6	USE ieee.numeric_std.ALL;
	7
	8
	9	entity CONFIG_SPACE_HEADER is
2612d712	10	Port ( AD_REG : In std_logic_vector (31 downto 0);
	11	ADDR_REG : In std_logic_vector (31 downto 0);
	12	CBE_REGn : In std_logic_vector (3 downto 0);
	13	CF_RD_COM : In std_logic;
	14	CF_WR_COM : In std_logic;
	15	IRDY_REGn : In std_logic;
	16	PCI_CLOCK : In std_logic;
	17	PCI_RSTn : In std_logic;
	18	PERR : In std_logic;
	19	REVISION_ID : In std_logic_vector (7 downto 0);
	20	SERR : In std_logic;
	21	TRDYn : In std_logic;
	22	VENDOR_ID : In std_logic_vector (15 downto 0);
	23	CONF_DATA : Out std_logic_vector (31 downto 0);
	24	CONF_DATA_04H : Out std_logic_vector (31 downto 0);
	25	CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
696ded12	26	end CONFIG_SPACE_HEADER;
	27
	28	architecture SCHEMATIC of CONFIG_SPACE_HEADER is
	29
2612d712	30	SIGNAL gnd : std_logic := '0';
	31	SIGNAL vcc : std_logic := '1';
	32
	33	signal CONF_WR_04H : std_logic;
	34	signal CONF_WR_10H : std_logic;
	35	signal CONF_WR_3CH : std_logic;
	36	signal CONF_READ_SEL : std_logic_vector (2 downto 0);
11b038c2	37	signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
11b038c2	38	signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
2612d712	39	signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
	40	signal CONF_DATA_08H : std_logic_vector (31 downto 0);
	41	signal CONF_DATA_00H : std_logic_vector (31 downto 0);
	42
11b038c2	43	component CONFIG_MUX_0
	44	Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);
	45	CONF_DATA_04H : In std_logic_vector (31 downto 0);
	46	CONF_DATA_08H : In std_logic_vector (31 downto 0);
	47	CONF_DATA_10H : In std_logic_vector (31 downto 0);
	48	CONF_DATA_3CH : In std_logic_vector (31 downto 0);
	49	READ_SEL : In std_logic_vector (2 downto 0);
	50	CONF_DATA : Out std_logic_vector (31 downto 0) );
	51	end component;
	52
	53	component CONFIG_RD_0
	54	Port ( ADDR_REG : In std_logic_vector (31 downto 0);
	55	CF_RD_COM : In std_logic;
	56	READ_SEL : Out std_logic_vector (2 downto 0) );
	57	end component;
	58
	59	component CONFIG_WR_0
	60	Port ( ADDR_REG : In std_logic_vector (31 downto 0);
	61	CF_WR_COM : In std_logic;
	62	IRDY_REGn : In std_logic;
	63	TRDYn : In std_logic;
	64	CONF_WR_04H : Out std_logic;
	65	CONF_WR_10H : Out std_logic;
	66	CONF_WR_3CH : Out std_logic );
	67	end component;
	68
	69	component CONFIG_3CH
	70	Port ( AD_REG : In std_logic_vector (31 downto 0);
	71	CBE_REGn : In std_logic_vector (3 downto 0);
	72	CONF_WR_3CH : In std_logic;
	73	PCI_CLOCK : In std_logic;
	74	PCI_RSTn : In std_logic;
	75	CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
	76	end component;
	77
	78	component CONFIG_10H
	79	Port ( AD_REG : In std_logic_vector (31 downto 0);
	80	CBE_REGn : In std_logic_vector (3 downto 0);
	81	CONF_WR_10H : In std_logic;
	82	PCI_CLOCK : In std_logic;
	83	PCI_RSTn : In std_logic;
	84	CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
	85	end component;
	86
	87	component CONFIG_08H
	88	Port ( REVISION_ID : In std_logic_vector (7 downto 0);
	89	CONF_DATA_08H : Out std_logic_vector (31 downto 0) );
	90	end component;
	91
	92	component CONFIG_00H
	93	Port ( VENDOR_ID : In std_logic_vector (15 downto 0);
	94	CONF_DATA_00H : Out std_logic_vector (31 downto 0) );
	95	end component;
	96
	97	component CONFIG_04H
	98	Port ( AD_REG : In std_logic_vector (31 downto 0);
	99	CBE_REGn : In std_logic_vector (3 downto 0);
	100	CONF_WR_04H : In std_logic;
	101	PCI_CLOCK : In std_logic;
	102	PCI_RSTn : In std_logic;
	103	PERR : In std_logic;
	104	SERR : In std_logic;
	105	CONF_DATA_04H : Out std_logic_vector (31 downto 0) );
	106	end component;
816293e0	107
11b038c2	108	begin
2e92b1a1	109
11b038c2	110	CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
	111	CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
	112
	113	I10 : CONFIG_MUX_0
	114	Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
	115	CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
	116	CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
	117	CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
	118	CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
	119	READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
	120	CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
	121	I9 : CONFIG_RD_0
	122	Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
	123	CF_RD_COM=>CF_RD_COM,
	124	READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
	125	I8 : CONFIG_WR_0
	126	Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
	127	CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
	128	TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
	129	CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
	130	I6 : CONFIG_3CH
	131	Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
	132	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
	133	CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
	134	PCI_RSTn=>PCI_RSTn,
	135	CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
	136	I5 : CONFIG_10H
	137	Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
	138	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
	139	CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
	140	PCI_RSTn=>PCI_RSTn,
	141	CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
	142	I4 : CONFIG_08H
	143	Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),
	144	CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );
	145	I3 : CONFIG_00H
	146	Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
	147	CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );
	148	I2 : CONFIG_04H
	149	Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
	150	CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
	151	CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
	152	PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
	153	CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
2e92b1a1	154
696ded12	155	end SCHEMATIC;