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[raggedstone] / dhwk / source / fifo_control.vhd
1 -- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity FIFO_CONTROL is
12 Port ( FIFO_RDn : In std_logic;
13 FLAG_IN_0 : In std_logic;
14 FLAG_IN_4 : In std_logic;
15 HOLD : In std_logic;
16 KONST_1 : In std_logic;
17 PCI_CLOCK : In std_logic;
18 PSC_ENABLE : In std_logic;
19 R_EFn : In std_logic;
20 R_FFn : In std_logic;
21 R_HFn : In std_logic;
22 RESET : In std_logic;
23 S_EFn : In std_logic;
24 S_FFn : In std_logic;
25 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
26 S_HFn : In std_logic;
27 SERIAL_IN : In std_logic;
28 SPC_ENABLE : In std_logic;
29 SPC_RDY_IN : In std_logic;
30 WRITE_XX1_0 : In std_logic;
31 R_ERROR : Out std_logic;
32 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
33 R_FIFO_READn : Out std_logic;
34 R_FIFO_RESETn : Out std_logic;
35 R_FIFO_RETRANSMITn : Out std_logic;
36 R_FIFO_WRITEn : Out std_logic;
37 RESERVE : Out std_logic;
38 S_ERROR : Out std_logic;
39 S_FIFO_READn : Out std_logic;
40 S_FIFO_RESETn : Out std_logic;
41 S_FIFO_RETRANSMITn : Out std_logic;
42 S_FIFO_WRITEn : Out std_logic;
43 SERIAL_OUT : Out std_logic;
44 SPC_RDY_OUT : Out std_logic;
45 SR_ERROR : Out std_logic;
46 SYNC_FLAG : Out std_logic_vector (7 downto 0);
47 PAR_SER_IN : Out std_logic_vector (7 downto 0));
48 end FIFO_CONTROL;
49
50 architecture SCHEMATIC of FIFO_CONTROL is
51
52 SIGNAL gnd : std_logic := '0';
53 SIGNAL vcc : std_logic := '1';
54
55 signal XXXR_FIFO_WRITEn : std_logic;
56 signal XXXS_FIFO_READn : std_logic;
57 signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
58 signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
59
60 component SER_PAR_CON
61 Port ( PCI_CLOCK : In std_logic;
62 RESET : In std_logic;
63 SERIAL_IN : In std_logic;
64 SPC_ENABLE : In std_logic;
65 SYNC_R_FIFO_FFn : In std_logic;
66 PAR_OUT : Out std_logic_vector (7 downto 0);
67 R_FIFO_WRITEn : Out std_logic;
68 SPC_RDY_OUT : Out std_logic );
69 end component;
70
71 component PAR_SER_CON
72 Port ( PAR_IN : In std_logic_vector (7 downto 0);
73 PCI_CLOCK : In std_logic;
74 PSC_ENABLE : In std_logic;
75 RESET : In std_logic;
76 SPC_RDY_IN : In std_logic;
77 SYNC_S_FIFO_EFn : In std_logic;
78 S_FIFO_READn : Out std_logic;
79 SER_OUT : Out std_logic );
80 end component;
81
82 component FIFO_IO_CONTROL
83 Port ( FIFO_RDn : In std_logic;
84 PCI_CLOCK : In std_logic;
85 RESET : In std_logic;
86 SYNC_FLAG_1 : In std_logic;
87 SYNC_FLAG_7 : In std_logic;
88 WRITE_XX1_0 : In std_logic;
89 R_ERROR : Out std_logic;
90 R_FIFO_READn : Out std_logic;
91 R_FIFO_RESETn : Out std_logic;
92 R_FIFO_RETRANSMITn : Out std_logic;
93 S_ERROR : Out std_logic;
94 S_FIFO_RESETn : Out std_logic;
95 S_FIFO_RETRANSMITn : Out std_logic;
96 S_FIFO_WRITEn : Out std_logic;
97 SR_ERROR : Out std_logic );
98 end component;
99
100 component CONNECTING_FSM
101 Port ( PCI_CLOCK : In std_logic;
102 PSC_ENABLE : In std_logic;
103 RESET : In std_logic;
104 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
105 SPC_ENABLE : In std_logic;
106 SYNC_R_FIFO_FFn : In std_logic;
107 SYNC_S_FIFO_EFn : In std_logic;
108 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
109 R_FIFO_WRITEn : Out std_logic;
110 S_FIFO_READn : Out std_logic );
111 end component;
112
113 component FLAG_BUS
114 Port ( FLAG_IN_0 : In std_logic;
115 FLAG_IN_4 : In std_logic;
116 HOLD : In std_logic;
117 KONS_1 : In std_logic;
118 PCI_CLOCK : In std_logic;
119 R_EFn : In std_logic;
120 R_FFn : In std_logic;
121 R_HFn : In std_logic;
122 S_EFn : In std_logic;
123 S_FFn : In std_logic;
124 S_HFn : In std_logic;
125 SYNC_FLAG : Out std_logic_vector (7 downto 0) );
126 end component;
127
128 begin
129
130 SYNC_FLAG <= SYNC_FLAG_DUMMY;
131 PAR_SER_IN <= S_FIFO_Q_OUT;
132
133
134 RESERVE <= gnd;
135 I23 : SER_PAR_CON
136 Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
137 SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
138 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
139 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
140 R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
141 I22 : PAR_SER_CON
142 Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
143 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
144 RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,
145 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
146 S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );
147 I21 : FIFO_IO_CONTROL
148 Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
149 SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),
150 SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),
151 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
152 R_FIFO_READn=>R_FIFO_READn,
153 R_FIFO_RESETn=>R_FIFO_RESETn,
154 R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,
155 S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,
156 S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,
157 S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );
158 I20 : CONNECTING_FSM
159 Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
160 RESET=>RESET,
161 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
162 SPC_ENABLE=>SPC_ENABLE,
163 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
164 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
165 R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),
166 R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,
167 S_FIFO_READn=>XXXS_FIFO_READn );
168 I19 : FLAG_BUS
169 Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,
170 KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,
171 R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,
172 S_HFn=>S_HFn,
173 SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );
174
175 end SCHEMATIC;
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