other watched signals
authormichael <michael>
Sat, 10 Mar 2007 15:48:06 +0000 (15:48 +0000)
committermichael <michael>
Sat, 10 Mar 2007 15:48:06 +0000 (15:48 +0000)
dhwk/ila.arg
dhwk/source/fifo_control.vhd
dhwk/source/top.vhd

index e206017192b902954c71c3ac47c73ac3487590be..2d1a3184a154e9502a6d2705ba0af37b7a7704a1 100644 (file)
@@ -3,8 +3,8 @@
 #
 -compname=ila
 -outputdirectory=.
--datadepth=1024
--datawidth=64
+-datadepth=8192
+-datawidth=36
 -numtrigports=1
 -trigportwidth0=8
 -nummatchunits=1
index 7c9ce96638fc787736da0ecd3a6bd3c0e9f079d4..1c2d52ea88c3bf00fc17e17e78b10958c20862b2 100644 (file)
@@ -43,7 +43,8 @@ entity FIFO_CONTROL is
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
-             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0);\r
+            PAR_SER_IN : Out std_logic_vector (7 downto 0));\r
 end FIFO_CONTROL;\r
 \r
 architecture SCHEMATIC of FIFO_CONTROL is\r
@@ -127,6 +128,8 @@ architecture SCHEMATIC of FIFO_CONTROL is
 begin\r
 \r
    SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
+   PAR_SER_IN <= S_FIFO_Q_OUT;\r
+\r
 \r
    RESERVE <= gnd;\r
    I23 : SER_PAR_CON\r
index dda8be16ac73559b5083c628932c8353870ee809..e2f307c0e6266ff027978c13b07d9ba352ff5594 100644 (file)
@@ -92,7 +92,7 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_OUT : std_logic;\r
    signal watch : std_logic;\r
    signal control0       : std_logic_vector(35 downto 0);\r
-   signal data       : std_logic_vector(63 downto 0);\r
+   signal data       : std_logic_vector(35 downto 0);\r
    signal trig0      : std_logic_vector(7 downto 0);\r
 \r
    component MESS_1_TB\r
@@ -169,6 +169,7 @@ architecture SCHEMATIC of dhwk is
              SERIAL_OUT : Out   std_logic;\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
+            PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r
@@ -236,7 +237,7 @@ end component;
     (\r
       control     : in    std_logic_vector(35 downto 0);\r
       clk         : in    std_logic;\r
-      data        : in    std_logic_vector(63 downto 0);\r
+      data        : in    std_logic_vector(35 downto 0);\r
       trig0       : in    std_logic_vector(7 downto 0)\r
     );\r
   end component;\r
@@ -250,28 +251,27 @@ begin
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r
-       trig0(7 downto 0) <= (others => '0');\r
-       data(31 downto 0) <= PCI_AD(31 downto 0);\r
-       data(32) <= watch;\r
+       trig0(7 downto 0) <= (0 => watch, others => '0');\r
+       data(0) <= watch;\r
        \r
-       data(33) <= R_EFn;\r
-       data(34) <= R_HFn;\r
-       data(35) <= R_FFn;\r
-       data(36) <= R_FIFO_READn;\r
-       data(37) <= R_FIFO_RESETn;\r
-       data(38) <= R_FIFO_RTn;\r
-       data(39) <= R_FIFO_WRITEn;\r
-       data(40) <= S_EFn;\r
-       data(41) <= S_HFn;\r
-       data(42) <= S_FFn;\r
-       data(43) <= S_FIFO_READn;\r
-       data(44) <= S_FIFO_RESETn;\r
-       data(45) <= S_FIFO_RTn;\r
-       data(46) <= S_FIFO_WRITEn;\r
-       data(47) <= SERIAL_IN;\r
-       data(48) <= SPC_RDY_IN;\r
-       data(49) <= SERIAL_OUT;\r
-       data(50) <= SPC_RDY_OUT;\r
+       data(1) <= R_EFn;\r
+       data(2) <= R_HFn;\r
+       data(3) <= R_FFn;\r
+       data(4) <= R_FIFO_READn;\r
+       data(5) <= R_FIFO_RESETn;\r
+       data(6) <= R_FIFO_RTn;\r
+       data(7) <= R_FIFO_WRITEn;\r
+       data(8) <= S_EFn;\r
+       data(9) <= S_HFn;\r
+       data(10) <= S_FFn;\r
+       data(11) <= S_FIFO_READn;\r
+       data(12) <= S_FIFO_RESETn;\r
+       data(13) <= S_FIFO_RTn;\r
+       data(14) <= S_FIFO_WRITEn;\r
+       data(15) <= SERIAL_IN;\r
+       data(16) <= SPC_RDY_IN;\r
+       data(17) <= SERIAL_OUT;\r
+       data(18) <= SPC_RDY_OUT;\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
@@ -313,6 +313,7 @@ begin
                  S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                  S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                  SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
+                PAR_SER_IN(7 downto 0)=>data(26 downto 19),\r
                  SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
    I1 : PCI_TOP\r
       Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
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