signal md_padoe_o : std_logic;
signal int_o : std_logic;
signal wbm_adr_o : std_logic_vector(31 downto 0);
-signal wb_stb_i_helper : std_logic_vector(31 downto 0);
signal m_wb_cti_o : std_logic_vector(2 downto 0);
signal m_wb_bte_o : std_logic_vector(1 downto 0);
PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
end generate;
-wb_adr_i <= wbm_adr_o (11 downto 2);
-
-wb_stb_i_helper(32 downto 8) <= (others => '0');
-wb_stb_i_helper(7 downto 0) <= wbm_adr_o (7 downto 0);
+wb_adr_i(11 downto 2) <= (others => '0');
+wb_adr_i <= wbm_adr_o (7 downto 2);
wb_clk_i <= PCI_CLOCK;
wb_sel_i => wb_sel_i ,
wb_we_i => wb_we_i ,
wb_cyc_i => wb_cyc_i ,
- wb_stb_i => wb_stb_i_helper ,
+ wb_stb_i => wb_stb_i,
wb_ack_o => wb_ack_o ,
wb_err_o => wb_err_o ,
m_wb_adr_o => m_wb_adr_o,