only regenerate cores when needed, and not on every build

diff --git a/common/Makefile.common b/common/Makefile.common
index bbf42182f35c96b6a4e7b16d8c94593f17b364f1..1cb35934680a3f46504aa1be385800c246f91034 100644 (file)
--- a/common/Makefile.common
+++ b/common/Makefile.common
@@ -7,7 +7,7 @@ CABLE ?= auto
 
 INTSTYLE := silent
 
 
 INTSTYLE := silent
 

-SOURCES := $(shell find . -name "*.vhd" -print) $(shell find . -name "*.v" -print)
+SOURCES := $(shell find . -wholename './tmp' -prune -o -name "*.vhd" -print) $(shell find . -wholename './tmp' -prune -o -name "*.v" -print)

 PART ?= xc3s1500-fg456-4
 TARGET ?= bit
 CLEANFILES ?=
 PART ?= xc3s1500-fg456-4
 TARGET ?= bit
 CLEANFILES ?=

diff --git a/dhwk/Makefile b/dhwk/Makefile
index fed955350bdfeae0a6d6764a64f6fccaa81318b8..c4d674383db2625961ddf817c8693a084fc6e0bb 100644 (file)
--- a/dhwk/Makefile
+++ b/dhwk/Makefile
@@ -1,19 +1,19 @@
 PROJECT := dhwk
 PROJECT := dhwk

-CLEANFILES := dhwk_fifo* fifo_generator_* param.opt icon.vhd icon.vho icon_flist.txt icon_readme.txt icon_xmdf.tcl ila.vhd ila.vho ila_flist.txt ila_readme.txt ila_xmdf.tcl vio.vhd vio.vho vio_flist.txt vio_readme.txt vio_xmdf.tcl
+CLEANFILES := dhwk_fifo* fifo_generator_* param.opt icon.* icon_flist.txt icon_readme.txt icon_xmdf.tcl ila.* ila_flist.txt ila_readme.txt ila_xmdf.tcl vio.* vio_flist.txt vio_readme.txt vio_xmdf.tcl

 
 dhwk_all: ip all
 
 ip: icon.ngc ila.ngc vio.ngc dhwk_fifo.ngc
 
 
 dhwk_all: ip all
 
 ip: icon.ngc ila.ngc vio.ngc dhwk_fifo.ngc
 

-icon.ngc: icon.xco
+icon.ngc: icon_core.xco

        coregen -b $<
        -rmdir -p tmp/_cg
 
        coregen -b $<
        -rmdir -p tmp/_cg
 

-ila.ngc: ila.xco
+ila.ngc: ila_core.xco

        coregen -b $<
        -rmdir -p tmp/_cg
 
        coregen -b $<
        -rmdir -p tmp/_cg
 

-vio.ngc: vio.xco
+vio.ngc: vio_core.xco

        coregen -b $<
        -rmdir -p tmp/_cg
 
        coregen -b $<
        -rmdir -p tmp/_cg
 

diff --git a/dhwk/icon.xco b/dhwk/icon.xco
deleted file mode 100644 (file)
index e501122..0000000
--- a/dhwk/icon.xco
+++ /dev/null
@@ -1,31 +0,0 @@
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = VHDL
-SET device = xc3s1500
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -4
-SET verilogsim = False
-SET vhdlsim = True
-# END Project Options
-# BEGIN Select
-SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a
-# END Select
-# BEGIN Parameters
-CSET component_name=icon
-CSET number_control_ports=2
-CSET use_ext_bscan=false
-CSET use_jtag_bufg=false
-CSET use_unused_bscan=false
-CSET user_scan_chain=USER1
-# END Parameters
-GENERATE

diff --git a/dhwk/icon_core.xco b/dhwk/icon_core.xco
new file mode 100644 (file)
index 0000000..e501122
--- /dev/null
+++ b/dhwk/icon_core.xco
@@ -0,0 +1,31 @@
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s1500
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -4
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a
+# END Select
+# BEGIN Parameters
+CSET component_name=icon
+CSET number_control_ports=2
+CSET use_ext_bscan=false
+CSET use_jtag_bufg=false
+CSET use_unused_bscan=false
+CSET user_scan_chain=USER1
+# END Parameters
+GENERATE

diff --git a/dhwk/ila.xco b/dhwk/ila.xco
deleted file mode 100644 (file)
index c0a3496..0000000
--- a/dhwk/ila.xco
+++ /dev/null
@@ -1,115 +0,0 @@
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = VHDL
-SET device = xc3s1500
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -4
-SET verilogsim = False
-SET vhdlsim = True
-# END Project Options
-# BEGIN Select
-SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a
-# END Select
-# BEGIN Parameters
-CSET component_name=ila
-CSET counter_width_1=Disabled
-CSET counter_width_10=Disabled
-CSET counter_width_11=Disabled
-CSET counter_width_12=Disabled
-CSET counter_width_13=Disabled
-CSET counter_width_14=Disabled
-CSET counter_width_15=Disabled
-CSET counter_width_16=Disabled
-CSET counter_width_2=Disabled
-CSET counter_width_3=Disabled
-CSET counter_width_4=Disabled
-CSET counter_width_5=Disabled
-CSET counter_width_6=Disabled
-CSET counter_width_7=Disabled
-CSET counter_width_8=Disabled
-CSET counter_width_9=Disabled
-CSET data_port_width=96
-CSET data_same_as_trigger=false
-CSET enable_storage_qualification=true
-CSET enable_trigger_output_port=false
-CSET exclude_from_data_storage_1=true
-CSET exclude_from_data_storage_10=true
-CSET exclude_from_data_storage_11=true
-CSET exclude_from_data_storage_12=true
-CSET exclude_from_data_storage_13=true
-CSET exclude_from_data_storage_14=true
-CSET exclude_from_data_storage_15=true
-CSET exclude_from_data_storage_16=true
-CSET exclude_from_data_storage_2=true
-CSET exclude_from_data_storage_3=true
-CSET exclude_from_data_storage_4=true
-CSET exclude_from_data_storage_5=true
-CSET exclude_from_data_storage_6=true
-CSET exclude_from_data_storage_7=true
-CSET exclude_from_data_storage_8=true
-CSET exclude_from_data_storage_9=true
-CSET match_type_1=basic
-CSET match_type_10=basic
-CSET match_type_11=basic
-CSET match_type_12=basic
-CSET match_type_13=basic
-CSET match_type_14=basic
-CSET match_type_15=basic
-CSET match_type_16=basic
-CSET match_type_2=basic
-CSET match_type_3=basic
-CSET match_type_4=basic
-CSET match_type_5=basic
-CSET match_type_6=basic
-CSET match_type_7=basic
-CSET match_type_8=basic
-CSET match_type_9=basic
-CSET match_units_1=1
-CSET match_units_10=1
-CSET match_units_11=1
-CSET match_units_12=1
-CSET match_units_13=1
-CSET match_units_14=1
-CSET match_units_15=1
-CSET match_units_16=1
-CSET match_units_2=1
-CSET match_units_3=1
-CSET match_units_4=1
-CSET match_units_5=1
-CSET match_units_6=1
-CSET match_units_7=1
-CSET match_units_8=1
-CSET match_units_9=1
-CSET max_sequence_levels=1
-CSET number_of_trigger_ports=1
-CSET sample_data_depth=4096
-CSET sample_on=Rising
-CSET trigger_port_width_1=32
-CSET trigger_port_width_10=8
-CSET trigger_port_width_11=8
-CSET trigger_port_width_12=8
-CSET trigger_port_width_13=8
-CSET trigger_port_width_14=8
-CSET trigger_port_width_15=8
-CSET trigger_port_width_16=8
-CSET trigger_port_width_2=8
-CSET trigger_port_width_3=8
-CSET trigger_port_width_4=8
-CSET trigger_port_width_5=8
-CSET trigger_port_width_6=8
-CSET trigger_port_width_7=8
-CSET trigger_port_width_8=8
-CSET trigger_port_width_9=8
-CSET use_rpms=true
-# END Parameters
-GENERATE

diff --git a/dhwk/ila_core.xco b/dhwk/ila_core.xco
new file mode 100644 (file)
index 0000000..c0a3496
--- /dev/null
+++ b/dhwk/ila_core.xco
@@ -0,0 +1,115 @@
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s1500
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -4
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a
+# END Select
+# BEGIN Parameters
+CSET component_name=ila
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=96
+CSET data_same_as_trigger=false
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET exclude_from_data_storage_1=true
+CSET exclude_from_data_storage_10=true
+CSET exclude_from_data_storage_11=true
+CSET exclude_from_data_storage_12=true
+CSET exclude_from_data_storage_13=true
+CSET exclude_from_data_storage_14=true
+CSET exclude_from_data_storage_15=true
+CSET exclude_from_data_storage_16=true
+CSET exclude_from_data_storage_2=true
+CSET exclude_from_data_storage_3=true
+CSET exclude_from_data_storage_4=true
+CSET exclude_from_data_storage_5=true
+CSET exclude_from_data_storage_6=true
+CSET exclude_from_data_storage_7=true
+CSET exclude_from_data_storage_8=true
+CSET exclude_from_data_storage_9=true
+CSET match_type_1=basic
+CSET match_type_10=basic
+CSET match_type_11=basic
+CSET match_type_12=basic
+CSET match_type_13=basic
+CSET match_type_14=basic
+CSET match_type_15=basic
+CSET match_type_16=basic
+CSET match_type_2=basic
+CSET match_type_3=basic
+CSET match_type_4=basic
+CSET match_type_5=basic
+CSET match_type_6=basic
+CSET match_type_7=basic
+CSET match_type_8=basic
+CSET match_type_9=basic
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=1
+CSET sample_data_depth=4096
+CSET sample_on=Rising
+CSET trigger_port_width_1=32
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=8
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=true
+# END Parameters
+GENERATE

diff --git a/dhwk/vio.xco b/dhwk/vio.xco
deleted file mode 100644 (file)
index 7575b90..0000000
--- a/dhwk/vio.xco
+++ /dev/null
@@ -1,35 +0,0 @@
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = VHDL
-SET device = xc3s1500
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -4
-SET verilogsim = False
-SET vhdlsim = True
-# END Project Options
-# BEGIN Select
-SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.02.a
-# END Select
-# BEGIN Parameters
-CSET asynchronous_input_port_width=4
-CSET asynchronous_output_port_width=8
-CSET component_name=vio
-CSET enable_asynchronous_input_port=true
-CSET enable_asynchronous_output_port=false
-CSET enable_synchronous_input_port=false
-CSET enable_synchronous_output_port=true
-CSET invert_clock_input=false
-CSET synchronous_input_port_width=8
-CSET synchronous_output_port_width=1
-# END Parameters
-GENERATE

diff --git a/dhwk/vio_core.xco b/dhwk/vio_core.xco
new file mode 100644 (file)
index 0000000..7575b90
--- /dev/null
+++ b/dhwk/vio_core.xco
@@ -0,0 +1,35 @@
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s1500
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -4
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.02.a
+# END Select
+# BEGIN Parameters
+CSET asynchronous_input_port_width=4
+CSET asynchronous_output_port_width=8
+CSET component_name=vio
+CSET enable_asynchronous_input_port=true
+CSET enable_asynchronous_output_port=false
+CSET enable_synchronous_input_port=false
+CSET enable_synchronous_output_port=true
+CSET invert_clock_input=false
+CSET synchronous_input_port_width=8
+CSET synchronous_output_port_width=1
+# END Parameters
+GENERATE

diff --git a/ethernet/Makefile b/ethernet/Makefile
index e8a70313a0133ab59e0899fb6c40250cf813bb4f..f4480c98daf5e0ff5abf3b8788910301f632db99 100644 (file)
--- a/ethernet/Makefile
+++ b/ethernet/Makefile
@@ -1,15 +1,15 @@
 PROJECT := ethernet
 PROJECT := ethernet

-CLEANFILES := param.opt icon.vhd icon.vho icon_flist.txt icon_readme.txt icon_xmdf.tcl ila.vhd ila.vho ila_flist.txt ila_readme.txt ila_xmdf.tcl
+CLEANFILES := param.opt icon.* icon_flist.txt icon_readme.txt icon_xmdf.tcl ila.* ila_flist.txt ila_readme.txt ila_xmdf.tcl

 
 ethernet_all: ip all
 
 ip: icon.ngc ila.ngc
 
 
 ethernet_all: ip all
 
 ip: icon.ngc ila.ngc
 

-icon.ngc: icon.xco
+icon.ngc: icon_core.xco

        coregen -b $<
        -rmdir -p tmp/_cg
 
        coregen -b $<
        -rmdir -p tmp/_cg
 

-ila.ngc: ila.xco
+ila.ngc: ila_core.xco

        coregen -b $<
        -rmdir -p tmp/_cg
 
        coregen -b $<
        -rmdir -p tmp/_cg
 

diff --git a/ethernet/icon.xco b/ethernet/icon.xco
deleted file mode 100644 (file)
index bc65d9c..0000000
--- a/ethernet/icon.xco
+++ /dev/null
@@ -1,31 +0,0 @@
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = VHDL
-SET device = xc3s1500
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -4
-SET verilogsim = False
-SET vhdlsim = True
-# END Project Options
-# BEGIN Select
-SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a
-# END Select
-# BEGIN Parameters
-CSET component_name=icon
-CSET number_control_ports=1
-CSET use_ext_bscan=false
-CSET use_jtag_bufg=false
-CSET use_unused_bscan=false
-CSET user_scan_chain=USER1
-# END Parameters
-GENERATE

diff --git a/ethernet/icon_core.xco b/ethernet/icon_core.xco
new file mode 100644 (file)
index 0000000..bc65d9c
--- /dev/null
+++ b/ethernet/icon_core.xco
@@ -0,0 +1,31 @@
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s1500
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -4
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a
+# END Select
+# BEGIN Parameters
+CSET component_name=icon
+CSET number_control_ports=1
+CSET use_ext_bscan=false
+CSET use_jtag_bufg=false
+CSET use_unused_bscan=false
+CSET user_scan_chain=USER1
+# END Parameters
+GENERATE

diff --git a/ethernet/ila.xco b/ethernet/ila.xco
deleted file mode 100644 (file)
index 713d6d6..0000000
--- a/ethernet/ila.xco
+++ /dev/null
@@ -1,115 +0,0 @@
-# BEGIN Project Options
-SET addpads = False
-SET asysymbol = False
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = False
-SET designentry = VHDL
-SET device = xc3s1500
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = False
-SET foundationsym = False
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = False
-SET simulationfiles = Structural
-SET speedgrade = -4
-SET verilogsim = False
-SET vhdlsim = True
-# END Project Options
-# BEGIN Select
-SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a
-# END Select
-# BEGIN Parameters
-CSET component_name=ila
-CSET counter_width_1=Disabled
-CSET counter_width_10=Disabled
-CSET counter_width_11=Disabled
-CSET counter_width_12=Disabled
-CSET counter_width_13=Disabled
-CSET counter_width_14=Disabled
-CSET counter_width_15=Disabled
-CSET counter_width_16=Disabled
-CSET counter_width_2=Disabled
-CSET counter_width_3=Disabled
-CSET counter_width_4=Disabled
-CSET counter_width_5=Disabled
-CSET counter_width_6=Disabled
-CSET counter_width_7=Disabled
-CSET counter_width_8=Disabled
-CSET counter_width_9=Disabled
-CSET data_port_width=64
-CSET data_same_as_trigger=false
-CSET enable_storage_qualification=true
-CSET enable_trigger_output_port=false
-CSET exclude_from_data_storage_1=true
-CSET exclude_from_data_storage_10=true
-CSET exclude_from_data_storage_11=true
-CSET exclude_from_data_storage_12=true
-CSET exclude_from_data_storage_13=true
-CSET exclude_from_data_storage_14=true
-CSET exclude_from_data_storage_15=true
-CSET exclude_from_data_storage_16=true
-CSET exclude_from_data_storage_2=true
-CSET exclude_from_data_storage_3=true
-CSET exclude_from_data_storage_4=true
-CSET exclude_from_data_storage_5=true
-CSET exclude_from_data_storage_6=true
-CSET exclude_from_data_storage_7=true
-CSET exclude_from_data_storage_8=true
-CSET exclude_from_data_storage_9=true
-CSET match_type_1=basic
-CSET match_type_10=basic
-CSET match_type_11=basic
-CSET match_type_12=basic
-CSET match_type_13=basic
-CSET match_type_14=basic
-CSET match_type_15=basic
-CSET match_type_16=basic
-CSET match_type_2=basic
-CSET match_type_3=basic
-CSET match_type_4=basic
-CSET match_type_5=basic
-CSET match_type_6=basic
-CSET match_type_7=basic
-CSET match_type_8=basic
-CSET match_type_9=basic
-CSET match_units_1=1
-CSET match_units_10=1
-CSET match_units_11=1
-CSET match_units_12=1
-CSET match_units_13=1
-CSET match_units_14=1
-CSET match_units_15=1
-CSET match_units_16=1
-CSET match_units_2=1
-CSET match_units_3=1
-CSET match_units_4=1
-CSET match_units_5=1
-CSET match_units_6=1
-CSET match_units_7=1
-CSET match_units_8=1
-CSET match_units_9=1
-CSET max_sequence_levels=1
-CSET number_of_trigger_ports=1
-CSET sample_data_depth=2048
-CSET sample_on=Rising
-CSET trigger_port_width_1=32
-CSET trigger_port_width_10=8
-CSET trigger_port_width_11=8
-CSET trigger_port_width_12=8
-CSET trigger_port_width_13=8
-CSET trigger_port_width_14=8
-CSET trigger_port_width_15=8
-CSET trigger_port_width_16=8
-CSET trigger_port_width_2=8
-CSET trigger_port_width_3=8
-CSET trigger_port_width_4=8
-CSET trigger_port_width_5=8
-CSET trigger_port_width_6=8
-CSET trigger_port_width_7=8
-CSET trigger_port_width_8=8
-CSET trigger_port_width_9=8
-CSET use_rpms=true
-# END Parameters
-GENERATE

diff --git a/ethernet/ila_core.xco b/ethernet/ila_core.xco
new file mode 100644 (file)
index 0000000..713d6d6
--- /dev/null
+++ b/ethernet/ila_core.xco
@@ -0,0 +1,115 @@
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s1500
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -4
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a
+# END Select
+# BEGIN Parameters
+CSET component_name=ila
+CSET counter_width_1=Disabled
+CSET counter_width_10=Disabled
+CSET counter_width_11=Disabled
+CSET counter_width_12=Disabled
+CSET counter_width_13=Disabled
+CSET counter_width_14=Disabled
+CSET counter_width_15=Disabled
+CSET counter_width_16=Disabled
+CSET counter_width_2=Disabled
+CSET counter_width_3=Disabled
+CSET counter_width_4=Disabled
+CSET counter_width_5=Disabled
+CSET counter_width_6=Disabled
+CSET counter_width_7=Disabled
+CSET counter_width_8=Disabled
+CSET counter_width_9=Disabled
+CSET data_port_width=64
+CSET data_same_as_trigger=false
+CSET enable_storage_qualification=true
+CSET enable_trigger_output_port=false
+CSET exclude_from_data_storage_1=true
+CSET exclude_from_data_storage_10=true
+CSET exclude_from_data_storage_11=true
+CSET exclude_from_data_storage_12=true
+CSET exclude_from_data_storage_13=true
+CSET exclude_from_data_storage_14=true
+CSET exclude_from_data_storage_15=true
+CSET exclude_from_data_storage_16=true
+CSET exclude_from_data_storage_2=true
+CSET exclude_from_data_storage_3=true
+CSET exclude_from_data_storage_4=true
+CSET exclude_from_data_storage_5=true
+CSET exclude_from_data_storage_6=true
+CSET exclude_from_data_storage_7=true
+CSET exclude_from_data_storage_8=true
+CSET exclude_from_data_storage_9=true
+CSET match_type_1=basic
+CSET match_type_10=basic
+CSET match_type_11=basic
+CSET match_type_12=basic
+CSET match_type_13=basic
+CSET match_type_14=basic
+CSET match_type_15=basic
+CSET match_type_16=basic
+CSET match_type_2=basic
+CSET match_type_3=basic
+CSET match_type_4=basic
+CSET match_type_5=basic
+CSET match_type_6=basic
+CSET match_type_7=basic
+CSET match_type_8=basic
+CSET match_type_9=basic
+CSET match_units_1=1
+CSET match_units_10=1
+CSET match_units_11=1
+CSET match_units_12=1
+CSET match_units_13=1
+CSET match_units_14=1
+CSET match_units_15=1
+CSET match_units_16=1
+CSET match_units_2=1
+CSET match_units_3=1
+CSET match_units_4=1
+CSET match_units_5=1
+CSET match_units_6=1
+CSET match_units_7=1
+CSET match_units_8=1
+CSET match_units_9=1
+CSET max_sequence_levels=1
+CSET number_of_trigger_ports=1
+CSET sample_data_depth=2048
+CSET sample_on=Rising
+CSET trigger_port_width_1=32
+CSET trigger_port_width_10=8
+CSET trigger_port_width_11=8
+CSET trigger_port_width_12=8
+CSET trigger_port_width_13=8
+CSET trigger_port_width_14=8
+CSET trigger_port_width_15=8
+CSET trigger_port_width_16=8
+CSET trigger_port_width_2=8
+CSET trigger_port_width_3=8
+CSET trigger_port_width_4=8
+CSET trigger_port_width_5=8
+CSET trigger_port_width_6=8
+CSET trigger_port_width_7=8
+CSET trigger_port_width_8=8
+CSET trigger_port_width_9=8
+CSET use_rpms=true
+# END Parameters
+GENERATE