add wake option to t55xx read command
[proxmark3-svn] / armsrc / lfops.c
CommitLineData
e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
dc4300ba 19#include "usb_cdc.h" //test
e09f21fa 20
21/**
22 * Function to do a modulation and then get samples.
23 * @param delay_off
24 * @param period_0
25 * @param period_1
26 * @param command
27 */
21a615cb 28void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t period_0, uint32_t period_1, uint8_t *command)
e09f21fa 29{
30
e0165dcf 31 int divisor_used = 95; // 125 KHz
32 // see if 'h' was specified
e09f21fa 33
e0165dcf 34 if (command[strlen((char *) command) - 1] == 'h')
35 divisor_used = 88; // 134.8 KHz
e09f21fa 36
37 sample_config sc = { 0,0,1, divisor_used, 0};
38 setSamplingConfig(&sc);
39
40 /* Make sure the tag is reset */
41 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
42 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
43 SpinDelay(2500);
44
45 LFSetupFPGAForADC(sc.divisor, 1);
46
47 // And a little more time for the tag to fully power up
48 SpinDelay(2000);
49
e0165dcf 50 // now modulate the reader field
51 while(*command != '\0' && *command != ' ') {
52 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
53 LED_D_OFF();
54 SpinDelayUs(delay_off);
e09f21fa 55 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
56
e0165dcf 57 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
58 LED_D_ON();
59 if(*(command++) == '0')
60 SpinDelayUs(period_0);
61 else
62 SpinDelayUs(period_1);
63 }
64 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
65 LED_D_OFF();
66 SpinDelayUs(delay_off);
e09f21fa 67 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
68
e0165dcf 69 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
e09f21fa 70
e0165dcf 71 // now do the read
e09f21fa 72 DoAcquisition_config(false);
73}
74
75
76
77/* blank r/w tag data stream
78...0000000000000000 01111111
791010101010101010101010101010101010101010101010101010101010101010
800011010010100001
8101111111
82101010101010101[0]000...
83
84[5555fe852c5555555555555555fe0000]
85*/
86void ReadTItag(void)
87{
e0165dcf 88 // some hardcoded initial params
89 // when we read a TI tag we sample the zerocross line at 2Mhz
90 // TI tags modulate a 1 as 16 cycles of 123.2Khz
91 // TI tags modulate a 0 as 16 cycles of 134.2Khz
e09f21fa 92 #define FSAMPLE 2000000
93 #define FREQLO 123200
94 #define FREQHI 134200
95
e0165dcf 96 signed char *dest = (signed char *)BigBuf_get_addr();
97 uint16_t n = BigBuf_max_traceLen();
98 // 128 bit shift register [shift3:shift2:shift1:shift0]
99 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
100
101 int i, cycles=0, samples=0;
102 // how many sample points fit in 16 cycles of each frequency
103 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
104 // when to tell if we're close enough to one freq or another
105 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
106
107 // TI tags charge at 134.2Khz
108 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
109 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
110
111 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
112 // connects to SSP_DIN and the SSP_DOUT logic level controls
113 // whether we're modulating the antenna (high)
114 // or listening to the antenna (low)
115 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
116
117 // get TI tag data into the buffer
118 AcquireTiType();
119
120 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
121
122 for (i=0; i<n-1; i++) {
123 // count cycles by looking for lo to hi zero crossings
124 if ( (dest[i]<0) && (dest[i+1]>0) ) {
125 cycles++;
126 // after 16 cycles, measure the frequency
127 if (cycles>15) {
128 cycles=0;
129 samples=i-samples; // number of samples in these 16 cycles
130
131 // TI bits are coming to us lsb first so shift them
132 // right through our 128 bit right shift register
133 shift0 = (shift0>>1) | (shift1 << 31);
134 shift1 = (shift1>>1) | (shift2 << 31);
135 shift2 = (shift2>>1) | (shift3 << 31);
136 shift3 >>= 1;
137
138 // check if the cycles fall close to the number
139 // expected for either the low or high frequency
140 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
141 // low frequency represents a 1
142 shift3 |= (1<<31);
143 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
144 // high frequency represents a 0
145 } else {
146 // probably detected a gay waveform or noise
147 // use this as gaydar or discard shift register and start again
148 shift3 = shift2 = shift1 = shift0 = 0;
149 }
150 samples = i;
151
152 // for each bit we receive, test if we've detected a valid tag
153
154 // if we see 17 zeroes followed by 6 ones, we might have a tag
155 // remember the bits are backwards
156 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
157 // if start and end bytes match, we have a tag so break out of the loop
158 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
159 cycles = 0xF0B; //use this as a flag (ugly but whatever)
160 break;
161 }
162 }
163 }
164 }
165 }
166
167 // if flag is set we have a tag
168 if (cycles!=0xF0B) {
169 DbpString("Info: No valid tag detected.");
170 } else {
171 // put 64 bit data into shift1 and shift0
172 shift0 = (shift0>>24) | (shift1 << 8);
173 shift1 = (shift1>>24) | (shift2 << 8);
174
175 // align 16 bit crc into lower half of shift2
176 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
177
178 // if r/w tag, check ident match
e09f21fa 179 if (shift3 & (1<<15) ) {
e0165dcf 180 DbpString("Info: TI tag is rewriteable");
181 // only 15 bits compare, last bit of ident is not valid
e09f21fa 182 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
e0165dcf 183 DbpString("Error: Ident mismatch!");
184 } else {
185 DbpString("Info: TI tag ident is valid");
186 }
187 } else {
188 DbpString("Info: TI tag is readonly");
189 }
190
191 // WARNING the order of the bytes in which we calc crc below needs checking
192 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
193 // bytes in reverse or something
194 // calculate CRC
195 uint32_t crc=0;
196
197 crc = update_crc16(crc, (shift0)&0xff);
198 crc = update_crc16(crc, (shift0>>8)&0xff);
199 crc = update_crc16(crc, (shift0>>16)&0xff);
200 crc = update_crc16(crc, (shift0>>24)&0xff);
201 crc = update_crc16(crc, (shift1)&0xff);
202 crc = update_crc16(crc, (shift1>>8)&0xff);
203 crc = update_crc16(crc, (shift1>>16)&0xff);
204 crc = update_crc16(crc, (shift1>>24)&0xff);
205
206 Dbprintf("Info: Tag data: %x%08x, crc=%x",
207 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
208 if (crc != (shift2&0xffff)) {
209 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
210 } else {
211 DbpString("Info: CRC is good");
212 }
213 }
e09f21fa 214}
215
dc4300ba
D
216
217
e09f21fa 218void WriteTIbyte(uint8_t b)
219{
e0165dcf 220 int i = 0;
221
222 // modulate 8 bits out to the antenna
223 for (i=0; i<8; i++)
224 {
225 if (b&(1<<i)) {
226 // stop modulating antenna
227 LOW(GPIO_SSC_DOUT);
228 SpinDelayUs(1000);
229 // modulate antenna
230 HIGH(GPIO_SSC_DOUT);
231 SpinDelayUs(1000);
232 } else {
233 // stop modulating antenna
234 LOW(GPIO_SSC_DOUT);
235 SpinDelayUs(300);
236 // modulate antenna
237 HIGH(GPIO_SSC_DOUT);
238 SpinDelayUs(1700);
239 }
240 }
e09f21fa 241}
242
243void AcquireTiType(void)
244{
e0165dcf 245 int i, j, n;
246 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
247 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
e09f21fa 248 #define TIBUFLEN 1250
249
e0165dcf 250 // clear buffer
e09f21fa 251 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
e0165dcf 252 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
253
254 // Set up the synchronous serial port
255 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
256 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
257
258 // steal this pin from the SSP and use it to control the modulation
259 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
260 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
261
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
263 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
264
265 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
266 // 48/2 = 24 MHz clock must be divided by 12
267 AT91C_BASE_SSC->SSC_CMR = 12;
268
269 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
270 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
271 AT91C_BASE_SSC->SSC_TCMR = 0;
272 AT91C_BASE_SSC->SSC_TFMR = 0;
273
274 LED_D_ON();
275
276 // modulate antenna
277 HIGH(GPIO_SSC_DOUT);
278
279 // Charge TI tag for 50ms.
280 SpinDelay(50);
281
282 // stop modulating antenna and listen
283 LOW(GPIO_SSC_DOUT);
284
285 LED_D_OFF();
286
287 i = 0;
288 for(;;) {
289 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
290 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
291 i++; if(i >= TIBUFLEN) break;
292 }
293 WDT_HIT();
294 }
295
296 // return stolen pin to SSP
297 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
298 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
299
300 char *dest = (char *)BigBuf_get_addr();
301 n = TIBUFLEN*32;
302 // unpack buffer
303 for (i=TIBUFLEN-1; i>=0; i--) {
304 for (j=0; j<32; j++) {
305 if(BigBuf[i] & (1 << j)) {
306 dest[--n] = 1;
307 } else {
308 dest[--n] = -1;
309 }
310 }
311 }
e09f21fa 312}
313
dc4300ba
D
314
315
316
e09f21fa 317// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
318// if crc provided, it will be written with the data verbatim (even if bogus)
319// if not provided a valid crc will be computed from the data and written.
320void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
321{
dc4300ba
D
322
323
fff58476 324 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
e0165dcf 325 if(crc == 0) {
326 crc = update_crc16(crc, (idlo)&0xff);
327 crc = update_crc16(crc, (idlo>>8)&0xff);
328 crc = update_crc16(crc, (idlo>>16)&0xff);
329 crc = update_crc16(crc, (idlo>>24)&0xff);
330 crc = update_crc16(crc, (idhi)&0xff);
331 crc = update_crc16(crc, (idhi>>8)&0xff);
332 crc = update_crc16(crc, (idhi>>16)&0xff);
333 crc = update_crc16(crc, (idhi>>24)&0xff);
334 }
335 Dbprintf("Writing to tag: %x%08x, crc=%x",
336 (unsigned int) idhi, (unsigned int) idlo, crc);
337
338 // TI tags charge at 134.2Khz
339 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
340 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
341 // connects to SSP_DIN and the SSP_DOUT logic level controls
342 // whether we're modulating the antenna (high)
343 // or listening to the antenna (low)
344 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
345 LED_A_ON();
346
347 // steal this pin from the SSP and use it to control the modulation
348 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
349 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
350
351 // writing algorithm:
352 // a high bit consists of a field off for 1ms and field on for 1ms
353 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
354 // initiate a charge time of 50ms (field on) then immediately start writing bits
355 // start by writing 0xBB (keyword) and 0xEB (password)
356 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
357 // finally end with 0x0300 (write frame)
358 // all data is sent lsb firts
359 // finish with 15ms programming time
360
361 // modulate antenna
362 HIGH(GPIO_SSC_DOUT);
363 SpinDelay(50); // charge time
364
365 WriteTIbyte(0xbb); // keyword
366 WriteTIbyte(0xeb); // password
367 WriteTIbyte( (idlo )&0xff );
368 WriteTIbyte( (idlo>>8 )&0xff );
369 WriteTIbyte( (idlo>>16)&0xff );
370 WriteTIbyte( (idlo>>24)&0xff );
371 WriteTIbyte( (idhi )&0xff );
372 WriteTIbyte( (idhi>>8 )&0xff );
373 WriteTIbyte( (idhi>>16)&0xff );
374 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
375 WriteTIbyte( (crc )&0xff ); // crc lo
376 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
377 WriteTIbyte(0x00); // write frame lo
378 WriteTIbyte(0x03); // write frame hi
379 HIGH(GPIO_SSC_DOUT);
380 SpinDelay(50); // programming time
381
382 LED_A_OFF();
383
384 // get TI tag data into the buffer
385 AcquireTiType();
386
387 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
388 DbpString("Now use tiread to check");
e09f21fa 389}
390
391void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
392{
e0165dcf 393 int i;
394 uint8_t *tab = BigBuf_get_addr();
e09f21fa 395
e0165dcf 396 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
397 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
e09f21fa 398
e0165dcf 399 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
e09f21fa 400
e0165dcf 401 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
402 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
e09f21fa 403
404 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
405 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
406
e0165dcf 407 i = 0;
408 for(;;) {
409 //wait until SSC_CLK goes HIGH
410 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
83f3f8ac 411 if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
e0165dcf 412 DbpString("Stopped");
413 return;
414 }
415 WDT_HIT();
416 }
417 if (ledcontrol)
418 LED_D_ON();
419
420 if(tab[i])
421 OPEN_COIL();
422 else
423 SHORT_COIL();
424
425 if (ledcontrol)
426 LED_D_OFF();
427 //wait until SSC_CLK goes LOW
428 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
429 if(BUTTON_PRESS()) {
430 DbpString("Stopped");
431 return;
432 }
433 WDT_HIT();
434 }
435
436 i++;
437 if(i == period) {
438
439 i = 0;
440 if (gap) {
441 SHORT_COIL();
442 SpinDelayUs(gap);
443 }
444 }
445 }
e09f21fa 446}
447
e09f21fa 448#define DEBUG_FRAME_CONTENTS 1
449void SimulateTagLowFrequencyBidir(int divisor, int t0)
450{
451}
452
453// compose fc/8 fc/10 waveform (FSK2)
454static void fc(int c, int *n)
455{
e0165dcf 456 uint8_t *dest = BigBuf_get_addr();
457 int idx;
458
459 // for when we want an fc8 pattern every 4 logical bits
460 if(c==0) {
461 dest[((*n)++)]=1;
462 dest[((*n)++)]=1;
463 dest[((*n)++)]=1;
464 dest[((*n)++)]=1;
465 dest[((*n)++)]=0;
466 dest[((*n)++)]=0;
467 dest[((*n)++)]=0;
468 dest[((*n)++)]=0;
469 }
470
471 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
472 if(c==8) {
473 for (idx=0; idx<6; idx++) {
474 dest[((*n)++)]=1;
475 dest[((*n)++)]=1;
476 dest[((*n)++)]=1;
477 dest[((*n)++)]=1;
478 dest[((*n)++)]=0;
479 dest[((*n)++)]=0;
480 dest[((*n)++)]=0;
481 dest[((*n)++)]=0;
482 }
483 }
484
485 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
486 if(c==10) {
487 for (idx=0; idx<5; idx++) {
488 dest[((*n)++)]=1;
489 dest[((*n)++)]=1;
490 dest[((*n)++)]=1;
491 dest[((*n)++)]=1;
492 dest[((*n)++)]=1;
493 dest[((*n)++)]=0;
494 dest[((*n)++)]=0;
495 dest[((*n)++)]=0;
496 dest[((*n)++)]=0;
497 dest[((*n)++)]=0;
498 }
499 }
e09f21fa 500}
501// compose fc/X fc/Y waveform (FSKx)
712ebfa6 502static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 503{
e0165dcf 504 uint8_t *dest = BigBuf_get_addr();
505 uint8_t halfFC = fc/2;
506 uint8_t wavesPerClock = clock/fc;
507 uint8_t mod = clock % fc; //modifier
508 uint8_t modAdj = fc/mod; //how often to apply modifier
509 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
510 // loop through clock - step field clock
511 for (uint8_t idx=0; idx < wavesPerClock; idx++){
512 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
513 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
514 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
515 *n += fc;
516 }
517 if (mod>0) (*modCnt)++;
518 if ((mod>0) && modAdjOk){ //fsk2
519 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
520 memset(dest+(*n), 0, fc-halfFC);
521 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
522 *n += fc;
523 }
524 }
525 if (mod>0 && !modAdjOk){ //fsk1
526 memset(dest+(*n), 0, mod-(mod/2));
527 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
528 *n += mod;
529 }
e09f21fa 530}
531
532// prepare a waveform pattern in the buffer based on the ID given then
533// simulate a HID tag until the button is pressed
534void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
535{
e0165dcf 536 int n=0, i=0;
537 /*
538 HID tag bitstream format
539 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
540 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
541 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
542 A fc8 is inserted before every 4 bits
543 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
544 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
545 */
546
547 if (hi>0xFFF) {
548 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
549 return;
550 }
551 fc(0,&n);
552 // special start of frame marker containing invalid bit sequences
553 fc(8, &n); fc(8, &n); // invalid
554 fc(8, &n); fc(10, &n); // logical 0
555 fc(10, &n); fc(10, &n); // invalid
556 fc(8, &n); fc(10, &n); // logical 0
557
558 WDT_HIT();
559 // manchester encode bits 43 to 32
560 for (i=11; i>=0; i--) {
561 if ((i%4)==3) fc(0,&n);
562 if ((hi>>i)&1) {
563 fc(10, &n); fc(8, &n); // low-high transition
564 } else {
565 fc(8, &n); fc(10, &n); // high-low transition
566 }
567 }
568
569 WDT_HIT();
570 // manchester encode bits 31 to 0
571 for (i=31; i>=0; i--) {
572 if ((i%4)==3) fc(0,&n);
573 if ((lo>>i)&1) {
574 fc(10, &n); fc(8, &n); // low-high transition
575 } else {
576 fc(8, &n); fc(10, &n); // high-low transition
577 }
578 }
579
580 if (ledcontrol)
581 LED_A_ON();
582 SimulateTagLowFrequency(n, 0, ledcontrol);
583
584 if (ledcontrol)
585 LED_A_OFF();
e09f21fa 586}
587
588// prepare a waveform pattern in the buffer based on the ID given then
589// simulate a FSK tag until the button is pressed
590// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
591void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
592{
e0165dcf 593 int ledcontrol=1;
594 int n=0, i=0;
595 uint8_t fcHigh = arg1 >> 8;
596 uint8_t fcLow = arg1 & 0xFF;
597 uint16_t modCnt = 0;
598 uint8_t clk = arg2 & 0xFF;
599 uint8_t invert = (arg2 >> 8) & 1;
600
601 for (i=0; i<size; i++){
602 if (BitStream[i] == invert){
603 fcAll(fcLow, &n, clk, &modCnt);
604 } else {
605 fcAll(fcHigh, &n, clk, &modCnt);
606 }
607 }
608 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
609 /*Dbprintf("DEBUG: First 32:");
610 uint8_t *dest = BigBuf_get_addr();
611 i=0;
612 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
613 i+=16;
614 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
615 */
616 if (ledcontrol)
617 LED_A_ON();
618
619 SimulateTagLowFrequency(n, 0, ledcontrol);
620
621 if (ledcontrol)
622 LED_A_OFF();
e09f21fa 623}
624
625// compose ask waveform for one bit(ASK)
e0165dcf 626static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
e09f21fa 627{
e0165dcf 628 uint8_t *dest = BigBuf_get_addr();
629 uint8_t halfClk = clock/2;
630 // c = current bit 1 or 0
631 if (manchester==1){
632 memset(dest+(*n), c, halfClk);
633 memset(dest+(*n) + halfClk, c^1, halfClk);
634 } else {
635 memset(dest+(*n), c, clock);
636 }
637 *n += clock;
e09f21fa 638}
639
b41534d1 640static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
641{
e0165dcf 642 uint8_t *dest = BigBuf_get_addr();
643 uint8_t halfClk = clock/2;
644 if (c){
645 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
646 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
647 } else {
648 memset(dest+(*n), c ^ *phase, clock);
649 *phase ^= 1;
650 }
b41534d1 651
652}
653
e09f21fa 654// args clock, ask/man or askraw, invert, transmission separator
655void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
656{
e0165dcf 657 int ledcontrol = 1;
658 int n=0, i=0;
659 uint8_t clk = (arg1 >> 8) & 0xFF;
2b3af97d 660 uint8_t encoding = arg1 & 0xFF;
e0165dcf 661 uint8_t separator = arg2 & 1;
662 uint8_t invert = (arg2 >> 8) & 1;
663
664 if (encoding==2){ //biphase
665 uint8_t phase=0;
666 for (i=0; i<size; i++){
667 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
668 }
669 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
670 for (i=0; i<size; i++){
671 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
672 }
673 }
674 } else { // ask/manchester || ask/raw
675 for (i=0; i<size; i++){
676 askSimBit(BitStream[i]^invert, &n, clk, encoding);
677 }
678 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
679 for (i=0; i<size; i++){
680 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
681 }
682 }
683 }
684
685 if (separator==1) Dbprintf("sorry but separator option not yet available");
686
687 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
688 //DEBUG
689 //Dbprintf("First 32:");
690 //uint8_t *dest = BigBuf_get_addr();
691 //i=0;
692 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
693 //i+=16;
694 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
695
696 if (ledcontrol)
697 LED_A_ON();
698
699 SimulateTagLowFrequency(n, 0, ledcontrol);
700
701 if (ledcontrol)
702 LED_A_OFF();
e09f21fa 703}
704
705//carrier can be 2,4 or 8
706static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
707{
e0165dcf 708 uint8_t *dest = BigBuf_get_addr();
709 uint8_t halfWave = waveLen/2;
710 //uint8_t idx;
711 int i = 0;
712 if (phaseChg){
713 // write phase change
714 memset(dest+(*n), *curPhase^1, halfWave);
715 memset(dest+(*n) + halfWave, *curPhase, halfWave);
716 *n += waveLen;
717 *curPhase ^= 1;
718 i += waveLen;
719 }
720 //write each normal clock wave for the clock duration
721 for (; i < clk; i+=waveLen){
722 memset(dest+(*n), *curPhase, halfWave);
723 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
724 *n += waveLen;
725 }
e09f21fa 726}
727
728// args clock, carrier, invert,
729void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
730{
e0165dcf 731 int ledcontrol=1;
732 int n=0, i=0;
733 uint8_t clk = arg1 >> 8;
734 uint8_t carrier = arg1 & 0xFF;
735 uint8_t invert = arg2 & 0xFF;
736 uint8_t curPhase = 0;
737 for (i=0; i<size; i++){
738 if (BitStream[i] == curPhase){
739 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
740 } else {
741 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
742 }
743 }
744 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
745 //Dbprintf("DEBUG: First 32:");
746 //uint8_t *dest = BigBuf_get_addr();
747 //i=0;
748 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
749 //i+=16;
750 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
751
752 if (ledcontrol)
753 LED_A_ON();
754 SimulateTagLowFrequency(n, 0, ledcontrol);
755
756 if (ledcontrol)
757 LED_A_OFF();
e09f21fa 758}
759
760// loop to get raw HID waveform then FSK demodulate the TAG ID from it
761void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
762{
e0165dcf 763 uint8_t *dest = BigBuf_get_addr();
2eec55c8 764 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
765 size_t size;
e0165dcf 766 uint32_t hi2=0, hi=0, lo=0;
767 int idx=0;
768 // Configure to go in 125Khz listen mode
769 LFSetupFPGAForADC(95, true);
e09f21fa 770
d10e08ae 771 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e09f21fa 772
e0165dcf 773 WDT_HIT();
774 if (ledcontrol) LED_A_ON();
e09f21fa 775
776 DoAcquisition_default(-1,true);
777 // FSK demodulator
2eec55c8 778 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
779 size = 50*128*2; //big enough to catch 2 sequences of largest format
e09f21fa 780 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
e0165dcf 781
2eec55c8 782 if (idx>0 && lo>0 && (size==96 || size==192)){
783 // go over previously decoded manchester data and decode into usable tag ID
784 if (hi2 != 0){ //extra large HID tags 88/192 bits
e0165dcf 785 Dbprintf("TAG ID: %x%08x%08x (%d)",
786 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
2eec55c8 787 }else { //standard HID tags 44/96 bits
e0165dcf 788 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
789 uint8_t bitlen = 0;
790 uint32_t fc = 0;
791 uint32_t cardnum = 0;
e09f21fa 792 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
e0165dcf 793 uint32_t lo2=0;
794 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
795 uint8_t idx3 = 1;
e09f21fa 796 while(lo2 > 1){ //find last bit set to 1 (format len bit)
797 lo2=lo2 >> 1;
e0165dcf 798 idx3++;
799 }
e09f21fa 800 bitlen = idx3+19;
e0165dcf 801 fc =0;
802 cardnum=0;
e09f21fa 803 if(bitlen == 26){
e0165dcf 804 cardnum = (lo>>1)&0xFFFF;
805 fc = (lo>>17)&0xFF;
806 }
e09f21fa 807 if(bitlen == 37){
e0165dcf 808 cardnum = (lo>>1)&0x7FFFF;
809 fc = ((hi&0xF)<<12)|(lo>>20);
810 }
e09f21fa 811 if(bitlen == 34){
e0165dcf 812 cardnum = (lo>>1)&0xFFFF;
813 fc= ((hi&1)<<15)|(lo>>17);
814 }
e09f21fa 815 if(bitlen == 35){
e0165dcf 816 cardnum = (lo>>1)&0xFFFFF;
817 fc = ((hi&1)<<11)|(lo>>21);
818 }
819 }
820 else { //if bit 38 is not set then 37 bit format is used
821 bitlen= 37;
822 fc =0;
823 cardnum=0;
824 if(bitlen==37){
825 cardnum = (lo>>1)&0x7FFFF;
826 fc = ((hi&0xF)<<12)|(lo>>20);
827 }
828 }
829 //Dbprintf("TAG ID: %x%08x (%d)",
830 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
831 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
832 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
833 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
834 }
835 if (findone){
836 if (ledcontrol) LED_A_OFF();
837 *high = hi;
838 *low = lo;
839 return;
840 }
841 // reset
e0165dcf 842 }
2eec55c8 843 hi2 = hi = lo = idx = 0;
e0165dcf 844 WDT_HIT();
845 }
846 DbpString("Stopped");
847 if (ledcontrol) LED_A_OFF();
e09f21fa 848}
849
dbf6e824
CY
850// loop to get raw HID waveform then FSK demodulate the TAG ID from it
851void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
852{
853 uint8_t *dest = BigBuf_get_addr();
854 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
855 size_t size;
856 int idx=0;
857 // Configure to go in 125Khz listen mode
858 LFSetupFPGAForADC(95, true);
859
d10e08ae 860 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
dbf6e824
CY
861
862 WDT_HIT();
863 if (ledcontrol) LED_A_ON();
864
865 DoAcquisition_default(-1,true);
866 // FSK demodulator
867 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
868 size = 50*128*2; //big enough to catch 2 sequences of largest format
869 idx = AWIDdemodFSK(dest, &size);
870
871 if (idx>0 && size==96){
872 // Index map
873 // 0 10 20 30 40 50 60
874 // | | | | | | |
875 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
876 // -----------------------------------------------------------------------------
877 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
878 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
879 // |---26 bit---| |-----117----||-------------142-------------|
880 // b = format bit len, o = odd parity of last 3 bits
881 // f = facility code, c = card number
882 // w = wiegand parity
883 // (26 bit format shown)
884
885 //get raw ID before removing parities
886 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
887 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
888 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
889
890 size = removeParity(dest, idx+8, 4, 1, 88);
891 // ok valid card found!
892
893 // Index map
894 // 0 10 20 30 40 50 60
895 // | | | | | | |
896 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
897 // -----------------------------------------------------------------------------
898 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
899 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
900 // |26 bit| |-117--| |-----142------|
901 // b = format bit len, o = odd parity of last 3 bits
902 // f = facility code, c = card number
903 // w = wiegand parity
904 // (26 bit format shown)
905
906 uint32_t fc = 0;
907 uint32_t cardnum = 0;
908 uint32_t code1 = 0;
909 uint32_t code2 = 0;
910 uint8_t fmtLen = bytebits_to_byte(dest,8);
911 if (fmtLen==26){
912 fc = bytebits_to_byte(dest+9, 8);
913 cardnum = bytebits_to_byte(dest+17, 16);
914 code1 = bytebits_to_byte(dest+8,fmtLen);
915 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
916 } else {
917 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
918 if (fmtLen>32){
919 code1 = bytebits_to_byte(dest+8,fmtLen-32);
920 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
921 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
922 } else{
923 code1 = bytebits_to_byte(dest+8,fmtLen);
924 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
925 }
926 }
927 if (findone){
928 if (ledcontrol) LED_A_OFF();
929 return;
930 }
931 // reset
932 }
933 idx = 0;
934 WDT_HIT();
935 }
936 DbpString("Stopped");
937 if (ledcontrol) LED_A_OFF();
938}
939
e09f21fa 940void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
941{
e0165dcf 942 uint8_t *dest = BigBuf_get_addr();
943
944 size_t size=0, idx=0;
945 int clk=0, invert=0, errCnt=0, maxErr=20;
946 uint32_t hi=0;
947 uint64_t lo=0;
948 // Configure to go in 125Khz listen mode
949 LFSetupFPGAForADC(95, true);
950
d10e08ae 951 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e0165dcf 952
953 WDT_HIT();
954 if (ledcontrol) LED_A_ON();
955
956 DoAcquisition_default(-1,true);
957 size = BigBuf_max_traceLen();
e0165dcf 958 //askdemod and manchester decode
2eec55c8 959 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
fef74fdc 960 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
e0165dcf 961 WDT_HIT();
962
2eec55c8 963 if (errCnt<0) continue;
964
965 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
966 if (errCnt){
967 if (size>64){
968 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
969 hi,
970 (uint32_t)(lo>>32),
971 (uint32_t)lo,
972 (uint32_t)(lo&0xFFFF),
973 (uint32_t)((lo>>16LL) & 0xFF),
974 (uint32_t)(lo & 0xFFFFFF));
975 } else {
976 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
977 (uint32_t)(lo>>32),
978 (uint32_t)lo,
979 (uint32_t)(lo&0xFFFF),
980 (uint32_t)((lo>>16LL) & 0xFF),
981 (uint32_t)(lo & 0xFFFFFF));
e0165dcf 982 }
2eec55c8 983
e0165dcf 984 if (findone){
985 if (ledcontrol) LED_A_OFF();
986 *high=lo>>32;
987 *low=lo & 0xFFFFFFFF;
988 return;
989 }
e0165dcf 990 }
991 WDT_HIT();
2eec55c8 992 hi = lo = size = idx = 0;
993 clk = invert = errCnt = 0;
e0165dcf 994 }
995 DbpString("Stopped");
996 if (ledcontrol) LED_A_OFF();
e09f21fa 997}
998
999void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
1000{
e0165dcf 1001 uint8_t *dest = BigBuf_get_addr();
1002 int idx=0;
1003 uint32_t code=0, code2=0;
1004 uint8_t version=0;
1005 uint8_t facilitycode=0;
1006 uint16_t number=0;
1007 // Configure to go in 125Khz listen mode
1008 LFSetupFPGAForADC(95, true);
1009
d10e08ae 1010 while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
e0165dcf 1011 WDT_HIT();
1012 if (ledcontrol) LED_A_ON();
e09f21fa 1013 DoAcquisition_default(-1,true);
1014 //fskdemod and get start index
e0165dcf 1015 WDT_HIT();
1016 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
2eec55c8 1017 if (idx<0) continue;
1018 //valid tag found
1019
1020 //Index map
1021 //0 10 20 30 40 50 60
1022 //| | | | | | |
1023 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1024 //-----------------------------------------------------------------------------
1025 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
1026 //
1027 //XSF(version)facility:codeone+codetwo
1028 //Handle the data
1029 if(findone){ //only print binary if we are doing one
1030 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1031 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1032 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1033 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1034 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1035 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1036 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1037 }
1038 code = bytebits_to_byte(dest+idx,32);
1039 code2 = bytebits_to_byte(dest+idx+32,32);
1040 version = bytebits_to_byte(dest+idx+27,8); //14,4
1041 facilitycode = bytebits_to_byte(dest+idx+18,8);
1042 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1043
1044 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
1045 // if we're only looking for one tag
1046 if (findone){
1047 if (ledcontrol) LED_A_OFF();
1048 //LED_A_OFF();
1049 *high=code;
1050 *low=code2;
1051 return;
e0165dcf 1052 }
2eec55c8 1053 code=code2=0;
1054 version=facilitycode=0;
1055 number=0;
1056 idx=0;
1057
e0165dcf 1058 WDT_HIT();
1059 }
1060 DbpString("Stopped");
1061 if (ledcontrol) LED_A_OFF();
e09f21fa 1062}
1063
1064/*------------------------------
1065 * T5555/T5557/T5567 routines
1066 *------------------------------
1067 */
1068
1069/* T55x7 configuration register definitions */
1070#define T55x7_POR_DELAY 0x00000001
1071#define T55x7_ST_TERMINATOR 0x00000008
1072#define T55x7_PWD 0x00000010
1073#define T55x7_MAXBLOCK_SHIFT 5
1074#define T55x7_AOR 0x00000200
1075#define T55x7_PSKCF_RF_2 0
1076#define T55x7_PSKCF_RF_4 0x00000400
1077#define T55x7_PSKCF_RF_8 0x00000800
1078#define T55x7_MODULATION_DIRECT 0
1079#define T55x7_MODULATION_PSK1 0x00001000
1080#define T55x7_MODULATION_PSK2 0x00002000
1081#define T55x7_MODULATION_PSK3 0x00003000
1082#define T55x7_MODULATION_FSK1 0x00004000
1083#define T55x7_MODULATION_FSK2 0x00005000
1084#define T55x7_MODULATION_FSK1a 0x00006000
1085#define T55x7_MODULATION_FSK2a 0x00007000
1086#define T55x7_MODULATION_MANCHESTER 0x00008000
1087#define T55x7_MODULATION_BIPHASE 0x00010000
f4eadf8a 1088#define T55x7_MODULATION_DIPHASE 0x00018000
e09f21fa 1089#define T55x7_BITRATE_RF_8 0
1090#define T55x7_BITRATE_RF_16 0x00040000
1091#define T55x7_BITRATE_RF_32 0x00080000
1092#define T55x7_BITRATE_RF_40 0x000C0000
1093#define T55x7_BITRATE_RF_50 0x00100000
1094#define T55x7_BITRATE_RF_64 0x00140000
1095#define T55x7_BITRATE_RF_100 0x00180000
1096#define T55x7_BITRATE_RF_128 0x001C0000
1097
1098/* T5555 (Q5) configuration register definitions */
1099#define T5555_ST_TERMINATOR 0x00000001
1100#define T5555_MAXBLOCK_SHIFT 0x00000001
1101#define T5555_MODULATION_MANCHESTER 0
1102#define T5555_MODULATION_PSK1 0x00000010
1103#define T5555_MODULATION_PSK2 0x00000020
1104#define T5555_MODULATION_PSK3 0x00000030
1105#define T5555_MODULATION_FSK1 0x00000040
1106#define T5555_MODULATION_FSK2 0x00000050
1107#define T5555_MODULATION_BIPHASE 0x00000060
1108#define T5555_MODULATION_DIRECT 0x00000070
1109#define T5555_INVERT_OUTPUT 0x00000080
1110#define T5555_PSK_RF_2 0
1111#define T5555_PSK_RF_4 0x00000100
1112#define T5555_PSK_RF_8 0x00000200
1113#define T5555_USE_PWD 0x00000400
1114#define T5555_USE_AOR 0x00000800
1115#define T5555_BITRATE_SHIFT 12
1116#define T5555_FAST_WRITE 0x00004000
1117#define T5555_PAGE_SELECT 0x00008000
1118
1119/*
1120 * Relevant times in microsecond
1121 * To compensate antenna falling times shorten the write times
1122 * and enlarge the gap ones.
7cfc777b 1123 * Q5 tags seems to have issues when these values changes.
e09f21fa 1124 */
4a3f1a37 1125#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1126#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1127#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1128#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
7cfc777b 1129#define READ_GAP 52*8
1130
1131// VALUES TAKEN FROM EM4x function: SendForward
1132// START_GAP = 440; (55*8) cycles at 125Khz (8us = 1cycle)
1133// WRITE_GAP = 128; (16*8)
1134// WRITE_1 = 256 32*8; (32*8)
1135
1136// These timings work for 4469/4269/4305 (with the 55*8 above)
1137// WRITE_0 = 23*8 , 9*8 SpinDelayUs(23*8);
1138
1139// Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
1140// TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
1141// Hitag units (T0) have duration of 8 microseconds (us), which is 1/125000 per second (carrier)
1142// T0 = TIMER_CLOCK1 / 125000 = 192
1143// 1 Cycle = 8 microseconds(us) == 1 field clock
1144
1145void TurnReadLFOn(int delay) {
1146 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1147 // Give it a bit of time for the resonant antenna to settle.
1148 SpinDelayUs(delay); //155*8 //50*8
1149}
13d77ef9 1150
e09f21fa 1151// Write one bit to card
7cfc777b 1152void T55xxWriteBit(int bit) {
e0165dcf 1153 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
7cfc777b 1154 if (!bit)
e0165dcf 1155 SpinDelayUs(WRITE_0);
1156 else
1157 SpinDelayUs(WRITE_1);
1158 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1159 SpinDelayUs(WRITE_GAP);
e09f21fa 1160}
1161
1162// Write one card block in page 0, no lock
7cfc777b 1163void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode) {
1164 LED_A_ON();
1165
e0165dcf 1166 uint32_t i = 0;
1167
1168 // Set up FPGA, 125kHz
f4eadf8a 1169 LFSetupFPGAForADC(95, true);
e0165dcf 1170
7cfc777b 1171 // Trigger T55x7 in mode.
e0165dcf 1172 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1173 SpinDelayUs(START_GAP);
1174
7cfc777b 1175 // Opcode 10
e0165dcf 1176 T55xxWriteBit(1);
1177 T55xxWriteBit(0); //Page 0
1178 if (PwdMode == 1){
7cfc777b 1179 // Send Pwd
e0165dcf 1180 for (i = 0x80000000; i != 0; i >>= 1)
1181 T55xxWriteBit(Pwd & i);
1182 }
7cfc777b 1183 // Send Lock bit
e0165dcf 1184 T55xxWriteBit(0);
1185
7cfc777b 1186 // Send Data
e0165dcf 1187 for (i = 0x80000000; i != 0; i >>= 1)
1188 T55xxWriteBit(Data & i);
1189
7cfc777b 1190 // Send Block number
e0165dcf 1191 for (i = 0x04; i != 0; i >>= 1)
1192 T55xxWriteBit(Block & i);
1193
7cfc777b 1194 // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
e0165dcf 1195 // so wait a little more)
7cfc777b 1196 TurnReadLFOn(20 * 1000);
e09f21fa 1197
7cfc777b 1198 // turn field off
1199 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1200 cmd_send(CMD_ACK,0,0,0,0,0);
1201 LED_A_OFF();
13d77ef9 1202}
1203
e09f21fa 1204// Read one card block in page 0
8e99ec25 1205void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
7cfc777b 1206 LED_A_ON();
8e99ec25 1207 uint8_t PwdMode = arg0 & 0xFF;
1208 uint8_t wake = arg0 >> 8;
e0165dcf 1209 uint32_t i = 0;
e0165dcf 1210
7cfc777b 1211 //clear buffer now so it does not interfere with timing later
1212 BigBuf_Clear_ext(false);
f4eadf8a 1213
7cfc777b 1214 //make sure block is at max 7
1215 Block &= 0x7;
1216
1217 // Set up FPGA, 125kHz
f4eadf8a 1218 LFSetupFPGAForADC(95, true);
7cfc777b 1219 /*
f4eadf8a 1220 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1221
1222 // Connect the A/D to the peak-detected low-frequency path.
1223 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1224
1225 // Now set up the SSC to get the ADC samples that are now streaming at us.
1226 FpgaSetupSsc();
1227
1228 // Give it a bit of time for the resonant antenna to settle.
1229 //SpinDelayUs(8*200); //192FC
1230 SpinDelay(50);
7cfc777b 1231 */
f4eadf8a 1232
7cfc777b 1233 // Trigger T55x7 Direct Access Mode
e0165dcf 1234 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1235 SpinDelayUs(START_GAP);
1236
7cfc777b 1237 // Opcode 10
e0165dcf 1238 T55xxWriteBit(1);
1239 T55xxWriteBit(0); //Page 0
7cfc777b 1240
8e99ec25 1241 if (PwdMode || wake){
7cfc777b 1242 // Send Pwd
e0165dcf 1243 for (i = 0x80000000; i != 0; i >>= 1)
1244 T55xxWriteBit(Pwd & i);
1245 }
7cfc777b 1246
8e99ec25 1247 // reading a block - send rest of read block cmd else skip for wake command
1248 if (!wake) {
1249 // Send a zero bit separation
1250 T55xxWriteBit(0);
1251
1252 // Send Block number
1253 for (i = 0x04; i != 0; i >>= 1)
1254 T55xxWriteBit(Block & i);
1255 }
e0165dcf 1256
1257 // Turn field on to read the response
7cfc777b 1258 TurnReadLFOn(READ_GAP);
f4eadf8a 1259
7cfc777b 1260 // Acquisition
1261 doT55x7Acquisition();
e0165dcf 1262
7cfc777b 1263 // Turn the field off
e0165dcf 1264 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
7cfc777b 1265 cmd_send(CMD_ACK,0,0,0,0,0);
1266 LED_A_OFF();
e09f21fa 1267}
1268
1269// Read card traceability data (page 1)
1270void T55xxReadTrace(void){
7cfc777b 1271 LED_A_ON();
e0165dcf 1272
7cfc777b 1273 //clear buffer now so it does not interfere with timing later
1274 BigBuf_Clear_ext(false);
1275
1276 // Set up FPGA, 125kHz
1277 LFSetupFPGAForADC(95, true);
e0165dcf 1278
7cfc777b 1279 // Trigger T55x7 Direct Access Mode
e0165dcf 1280 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1281 SpinDelayUs(START_GAP);
1282
7cfc777b 1283 // Opcode 11
e0165dcf 1284 T55xxWriteBit(1);
1285 T55xxWriteBit(1); //Page 1
1286
1287 // Turn field on to read the response
7cfc777b 1288 TurnReadLFOn(READ_GAP);
e0165dcf 1289
7cfc777b 1290 // Acquisition
1291 doT55x7Acquisition();
e0165dcf 1292
7cfc777b 1293 // Turn the field off
1294 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
e0165dcf 1295 cmd_send(CMD_ACK,0,0,0,0,0);
7cfc777b 1296 LED_A_OFF();
e09f21fa 1297}
1298
1299/*-------------- Cloning routines -----------*/
1300// Copy HID id to card and setup block 0 config
1301void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1302{
e0165dcf 1303 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1304 int last_block = 0;
1305
1306 if (longFMT){
1307 // Ensure no more than 84 bits supplied
1308 if (hi2>0xFFFFF) {
1309 DbpString("Tags can only have 84 bits.");
1310 return;
1311 }
1312 // Build the 6 data blocks for supplied 84bit ID
1313 last_block = 6;
1314 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1315 for (int i=0;i<4;i++) {
1316 if (hi2 & (1<<(19-i)))
1317 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1318 else
1319 data1 |= (1<<((3-i)*2)); // 0 -> 01
1320 }
1321
1322 data2 = 0;
1323 for (int i=0;i<16;i++) {
1324 if (hi2 & (1<<(15-i)))
1325 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1326 else
1327 data2 |= (1<<((15-i)*2)); // 0 -> 01
1328 }
1329
1330 data3 = 0;
1331 for (int i=0;i<16;i++) {
1332 if (hi & (1<<(31-i)))
1333 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1334 else
1335 data3 |= (1<<((15-i)*2)); // 0 -> 01
1336 }
1337
1338 data4 = 0;
1339 for (int i=0;i<16;i++) {
1340 if (hi & (1<<(15-i)))
1341 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1342 else
1343 data4 |= (1<<((15-i)*2)); // 0 -> 01
1344 }
1345
1346 data5 = 0;
1347 for (int i=0;i<16;i++) {
1348 if (lo & (1<<(31-i)))
1349 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1350 else
1351 data5 |= (1<<((15-i)*2)); // 0 -> 01
1352 }
1353
1354 data6 = 0;
1355 for (int i=0;i<16;i++) {
1356 if (lo & (1<<(15-i)))
1357 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1358 else
1359 data6 |= (1<<((15-i)*2)); // 0 -> 01
1360 }
1361 }
1362 else {
1363 // Ensure no more than 44 bits supplied
1364 if (hi>0xFFF) {
1365 DbpString("Tags can only have 44 bits.");
1366 return;
1367 }
1368
1369 // Build the 3 data blocks for supplied 44bit ID
1370 last_block = 3;
1371
1372 data1 = 0x1D000000; // load preamble
1373
1374 for (int i=0;i<12;i++) {
1375 if (hi & (1<<(11-i)))
1376 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1377 else
1378 data1 |= (1<<((11-i)*2)); // 0 -> 01
1379 }
1380
1381 data2 = 0;
1382 for (int i=0;i<16;i++) {
1383 if (lo & (1<<(31-i)))
1384 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1385 else
1386 data2 |= (1<<((15-i)*2)); // 0 -> 01
1387 }
1388
1389 data3 = 0;
1390 for (int i=0;i<16;i++) {
1391 if (lo & (1<<(15-i)))
1392 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1393 else
1394 data3 |= (1<<((15-i)*2)); // 0 -> 01
1395 }
1396 }
1397
1398 LED_D_ON();
1399 // Program the data blocks for supplied ID
1400 // and the block 0 for HID format
1401 T55xxWriteBlock(data1,1,0,0);
1402 T55xxWriteBlock(data2,2,0,0);
1403 T55xxWriteBlock(data3,3,0,0);
1404
1405 if (longFMT) { // if long format there are 6 blocks
1406 T55xxWriteBlock(data4,4,0,0);
1407 T55xxWriteBlock(data5,5,0,0);
1408 T55xxWriteBlock(data6,6,0,0);
1409 }
1410
1411 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1412 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1413 T55x7_MODULATION_FSK2a |
1414 last_block << T55x7_MAXBLOCK_SHIFT,
1415 0,0,0);
1416
1417 LED_D_OFF();
1418
1419 DbpString("DONE!");
e09f21fa 1420}
1421
1422void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1423{
e0165dcf 1424 int data1=0, data2=0; //up to six blocks for long format
e09f21fa 1425
e0165dcf 1426 data1 = hi; // load preamble
1427 data2 = lo;
e09f21fa 1428
e0165dcf 1429 LED_D_ON();
1430 // Program the data blocks for supplied ID
1431 // and the block 0 for HID format
1432 T55xxWriteBlock(data1,1,0,0);
1433 T55xxWriteBlock(data2,2,0,0);
e09f21fa 1434
e0165dcf 1435 //Config Block
1436 T55xxWriteBlock(0x00147040,0,0,0);
1437 LED_D_OFF();
e09f21fa 1438
e0165dcf 1439 DbpString("DONE!");
e09f21fa 1440}
1441
1442// Define 9bit header for EM410x tags
1443#define EM410X_HEADER 0x1FF
1444#define EM410X_ID_LENGTH 40
1445
1446void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1447{
e0165dcf 1448 int i, id_bit;
1449 uint64_t id = EM410X_HEADER;
1450 uint64_t rev_id = 0; // reversed ID
1451 int c_parity[4]; // column parity
1452 int r_parity = 0; // row parity
1453 uint32_t clock = 0;
1454
1455 // Reverse ID bits given as parameter (for simpler operations)
1456 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1457 if (i < 32) {
1458 rev_id = (rev_id << 1) | (id_lo & 1);
1459 id_lo >>= 1;
1460 } else {
1461 rev_id = (rev_id << 1) | (id_hi & 1);
1462 id_hi >>= 1;
1463 }
1464 }
1465
1466 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1467 id_bit = rev_id & 1;
1468
1469 if (i % 4 == 0) {
1470 // Don't write row parity bit at start of parsing
1471 if (i)
1472 id = (id << 1) | r_parity;
1473 // Start counting parity for new row
1474 r_parity = id_bit;
1475 } else {
1476 // Count row parity
1477 r_parity ^= id_bit;
1478 }
1479
1480 // First elements in column?
1481 if (i < 4)
1482 // Fill out first elements
1483 c_parity[i] = id_bit;
1484 else
1485 // Count column parity
1486 c_parity[i % 4] ^= id_bit;
1487
1488 // Insert ID bit
1489 id = (id << 1) | id_bit;
1490 rev_id >>= 1;
1491 }
1492
1493 // Insert parity bit of last row
1494 id = (id << 1) | r_parity;
1495
1496 // Fill out column parity at the end of tag
1497 for (i = 0; i < 4; ++i)
1498 id = (id << 1) | c_parity[i];
1499
1500 // Add stop bit
1501 id <<= 1;
1502
1503 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1504 LED_D_ON();
1505
1506 // Write EM410x ID
1507 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1508 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1509
1510 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1511 if (card) {
1512 // Clock rate is stored in bits 8-15 of the card value
1513 clock = (card & 0xFF00) >> 8;
1514 Dbprintf("Clock rate: %d", clock);
7cfc777b 1515 switch (clock) {
1516 case 50:
1517 clock = T55x7_BITRATE_RF_50;
1518 case 40:
1519 clock = T55x7_BITRATE_RF_40;
e0165dcf 1520 case 32:
1521 clock = T55x7_BITRATE_RF_32;
1522 break;
1523 case 16:
1524 clock = T55x7_BITRATE_RF_16;
1525 break;
1526 case 0:
1527 // A value of 0 is assumed to be 64 for backwards-compatibility
1528 // Fall through...
1529 case 64:
1530 clock = T55x7_BITRATE_RF_64;
1531 break;
1532 default:
1533 Dbprintf("Invalid clock rate: %d", clock);
1534 return;
1535 }
1536
1537 // Writing configuration for T55x7 tag
1538 T55xxWriteBlock(clock |
1539 T55x7_MODULATION_MANCHESTER |
1540 2 << T55x7_MAXBLOCK_SHIFT,
1541 0, 0, 0);
1542 }
1543 else
1544 // Writing configuration for T5555(Q5) tag
1545 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1546 T5555_MODULATION_MANCHESTER |
1547 2 << T5555_MAXBLOCK_SHIFT,
1548 0, 0, 0);
1549
1550 LED_D_OFF();
1551 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1552 (uint32_t)(id >> 32), (uint32_t)id);
e09f21fa 1553}
1554
1555// Clone Indala 64-bit tag by UID to T55x7
1556void CopyIndala64toT55x7(int hi, int lo)
1557{
1558
e0165dcf 1559 //Program the 2 data blocks for supplied 64bit UID
1560 // and the block 0 for Indala64 format
1561 T55xxWriteBlock(hi,1,0,0);
1562 T55xxWriteBlock(lo,2,0,0);
1563 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1564 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1565 T55x7_MODULATION_PSK1 |
1566 2 << T55x7_MAXBLOCK_SHIFT,
1567 0, 0, 0);
1568 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1569 // T5567WriteBlock(0x603E1042,0);
e09f21fa 1570
e0165dcf 1571 DbpString("DONE!");
e09f21fa 1572
1573}
1574
1575void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1576{
1577
e0165dcf 1578 //Program the 7 data blocks for supplied 224bit UID
1579 // and the block 0 for Indala224 format
1580 T55xxWriteBlock(uid1,1,0,0);
1581 T55xxWriteBlock(uid2,2,0,0);
1582 T55xxWriteBlock(uid3,3,0,0);
1583 T55xxWriteBlock(uid4,4,0,0);
1584 T55xxWriteBlock(uid5,5,0,0);
1585 T55xxWriteBlock(uid6,6,0,0);
1586 T55xxWriteBlock(uid7,7,0,0);
1587 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1588 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1589 T55x7_MODULATION_PSK1 |
1590 7 << T55x7_MAXBLOCK_SHIFT,
1591 0,0,0);
1592 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1593 // T5567WriteBlock(0x603E10E2,0);
1594
1595 DbpString("DONE!");
e09f21fa 1596
1597}
1598
e09f21fa 1599//-----------------------------------
1600// EM4469 / EM4305 routines
1601//-----------------------------------
1602#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1603#define FWD_CMD_WRITE 0xA
1604#define FWD_CMD_READ 0x9
1605#define FWD_CMD_DISABLE 0x5
1606
1607
1608uint8_t forwardLink_data[64]; //array of forwarded bits
1609uint8_t * forward_ptr; //ptr for forward message preparation
1610uint8_t fwd_bit_sz; //forwardlink bit counter
1611uint8_t * fwd_write_ptr; //forwardlink bit pointer
1612
1613//====================================================================
1614// prepares command bits
1615// see EM4469 spec
1616//====================================================================
1617//--------------------------------------------------------------------
1618uint8_t Prepare_Cmd( uint8_t cmd ) {
e0165dcf 1619 //--------------------------------------------------------------------
e09f21fa 1620
e0165dcf 1621 *forward_ptr++ = 0; //start bit
1622 *forward_ptr++ = 0; //second pause for 4050 code
e09f21fa 1623
e0165dcf 1624 *forward_ptr++ = cmd;
1625 cmd >>= 1;
1626 *forward_ptr++ = cmd;
1627 cmd >>= 1;
1628 *forward_ptr++ = cmd;
1629 cmd >>= 1;
1630 *forward_ptr++ = cmd;
e09f21fa 1631
e0165dcf 1632 return 6; //return number of emited bits
e09f21fa 1633}
1634
1635//====================================================================
1636// prepares address bits
1637// see EM4469 spec
1638//====================================================================
1639
1640//--------------------------------------------------------------------
1641uint8_t Prepare_Addr( uint8_t addr ) {
e0165dcf 1642 //--------------------------------------------------------------------
e09f21fa 1643
e0165dcf 1644 register uint8_t line_parity;
e09f21fa 1645
e0165dcf 1646 uint8_t i;
1647 line_parity = 0;
1648 for(i=0;i<6;i++) {
1649 *forward_ptr++ = addr;
1650 line_parity ^= addr;
1651 addr >>= 1;
1652 }
e09f21fa 1653
e0165dcf 1654 *forward_ptr++ = (line_parity & 1);
e09f21fa 1655
e0165dcf 1656 return 7; //return number of emited bits
e09f21fa 1657}
1658
1659//====================================================================
1660// prepares data bits intreleaved with parity bits
1661// see EM4469 spec
1662//====================================================================
1663
1664//--------------------------------------------------------------------
1665uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
e0165dcf 1666 //--------------------------------------------------------------------
1667
1668 register uint8_t line_parity;
1669 register uint8_t column_parity;
1670 register uint8_t i, j;
1671 register uint16_t data;
1672
1673 data = data_low;
1674 column_parity = 0;
1675
1676 for(i=0; i<4; i++) {
1677 line_parity = 0;
1678 for(j=0; j<8; j++) {
1679 line_parity ^= data;
1680 column_parity ^= (data & 1) << j;
1681 *forward_ptr++ = data;
1682 data >>= 1;
1683 }
1684 *forward_ptr++ = line_parity;
1685 if(i == 1)
1686 data = data_hi;
1687 }
1688
1689 for(j=0; j<8; j++) {
1690 *forward_ptr++ = column_parity;
1691 column_parity >>= 1;
1692 }
1693 *forward_ptr = 0;
1694
1695 return 45; //return number of emited bits
e09f21fa 1696}
1697
1698//====================================================================
1699// Forward Link send function
1700// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1701// fwd_bit_count set with number of bits to be sent
1702//====================================================================
1703void SendForward(uint8_t fwd_bit_count) {
1704
e0165dcf 1705 fwd_write_ptr = forwardLink_data;
1706 fwd_bit_sz = fwd_bit_count;
1707
1708 LED_D_ON();
1709
7cfc777b 1710 // Set up FPGA, 125kHz
1711 LFSetupFPGAForADC(95, true);
e0165dcf 1712
1713 // force 1st mod pulse (start gap must be longer for 4305)
1714 fwd_bit_sz--; //prepare next bit modulation
1715 fwd_write_ptr++;
1716 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1717 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1718 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1719 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1720 SpinDelayUs(16*8); //16 cycles on (8us each)
1721
1722 // now start writting
1723 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1724 if(((*fwd_write_ptr++) & 1) == 1)
1725 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1726 else {
1727 //These timings work for 4469/4269/4305 (with the 55*8 above)
1728 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1729 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1730 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1731 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1732 SpinDelayUs(9*8); //16 cycles on (8us each)
1733 }
1734 }
e09f21fa 1735}
1736
1737void EM4xLogin(uint32_t Password) {
1738
e0165dcf 1739 uint8_t fwd_bit_count;
e09f21fa 1740
e0165dcf 1741 forward_ptr = forwardLink_data;
1742 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1743 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
e09f21fa 1744
e0165dcf 1745 SendForward(fwd_bit_count);
e09f21fa 1746
e0165dcf 1747 //Wait for command to complete
1748 SpinDelay(20);
e09f21fa 1749
1750}
1751
1752void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1753
e0165dcf 1754 uint8_t fwd_bit_count;
1755 uint8_t *dest = BigBuf_get_addr();
7cfc777b 1756 uint16_t bufferlength = BigBuf_max_traceLen();
1757 uint32_t i = 0;
1758
1759 // Clear destination buffer before sending the command
1760 memset(dest, 0x80, bufferlength);
e0165dcf 1761
1762 //If password mode do login
1763 if (PwdMode == 1) EM4xLogin(Pwd);
1764
1765 forward_ptr = forwardLink_data;
1766 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1767 fwd_bit_count += Prepare_Addr( Address );
1768
e0165dcf 1769 // Connect the A/D to the peak-detected low-frequency path.
1770 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1771 // Now set up the SSC to get the ADC samples that are now streaming at us.
1772 FpgaSetupSsc();
1773
1774 SendForward(fwd_bit_count);
1775
1776 // Now do the acquisition
1777 i = 0;
1778 for(;;) {
1779 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1780 AT91C_BASE_SSC->SSC_THR = 0x43;
1781 }
1782 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1783 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1784 i++;
7cfc777b 1785 if (i >= bufferlength) break;
e0165dcf 1786 }
1787 }
1788 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
7cfc777b 1789 cmd_send(CMD_ACK,0,0,0,0,0);
e0165dcf 1790 LED_D_OFF();
e09f21fa 1791}
1792
1793void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1794
e0165dcf 1795 uint8_t fwd_bit_count;
e09f21fa 1796
e0165dcf 1797 //If password mode do login
1798 if (PwdMode == 1) EM4xLogin(Pwd);
e09f21fa 1799
e0165dcf 1800 forward_ptr = forwardLink_data;
1801 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1802 fwd_bit_count += Prepare_Addr( Address );
1803 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
e09f21fa 1804
e0165dcf 1805 SendForward(fwd_bit_count);
e09f21fa 1806
e0165dcf 1807 //Wait for write to complete
1808 SpinDelay(20);
1809 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1810 LED_D_OFF();
e09f21fa 1811}
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