only start running, when the dcm is locked

diff --git a/galaxian/src/mc_clock.v b/galaxian/src/mc_clock.v
index 36925f3f3bee4be56cd942b2ad9688b126676fbe..b859754fca7794335daf7700452e6b35e1c475fa 100644 (file)
--- a/galaxian/src/mc_clock.v
+++ b/galaxian/src/mc_clock.v
@@ -18,6 +18,7 @@
 module mc_clock(\r
 \r
 I_CLK_36M,\r
+I_DCM_LOCKED,\r
 O_CLK_18M,\r
 O_CLK_12M,\r
 O_CLK_06M,\r
@@ -26,6 +27,7 @@ O_CLK_06Mn
 );\r
 \r
 input I_CLK_36M;\r
+input I_DCM_LOCKED;\r
 output O_CLK_18M;\r
 output O_CLK_12M;\r
 output O_CLK_06M;\r
@@ -46,17 +48,23 @@ initial clk_12m = 0;
 // 2/3 clock         (duty 66%)\r
 always @(posedge I_CLK_36M)\r
 begin\r
-   case (state)\r
-      2'd0: state <= 2'd1;\r
-      2'd1: state <= 2'd2;\r
-      2'd2: state <= 2'd0;\r
-      2'd3: state <= 2'd0;\r
-   endcase\r
+   if (I_DCM_LOCKED == 1) begin\r
+      case (state)\r
+         2'd0: state <= 2'd1;\r
+         2'd1: state <= 2'd2;\r
+         2'd2: state <= 2'd0;\r
+         2'd3: state <= 2'd0;\r
+      endcase\r
 \r
-   if (state == 2'd2)\r
+      if (state == 2'd2)\r
+         clk_12m = 0;\r
+      else\r
+         clk_12m = 1;\r
+   end\r
+   else begin\r
+      state <= 2'd0;\r
       clk_12m = 0;\r
-   else\r
-      clk_12m = 1;\r
+   end\r
 end\r
 \r
 assign O_CLK_12M = clk_12m;\r
@@ -64,7 +72,10 @@ assign O_CLK_12M = clk_12m;
 reg CLK_18M;\r
 always @(posedge I_CLK_36M)\r
 begin\r
-   CLK_18M <= ~ CLK_18M;\r
+   if (I_DCM_LOCKED == 1)\r
+      CLK_18M <= ~ CLK_18M;\r
+   else\r
+      CLK_18M <= 0;\r
 end\r
 assign O_CLK_18M = CLK_18M;\r
 \r

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index 99206f367ab52db4aab5ed63f99d91ed33da776e..c99fcd821674aeb81645821d2851ac1a23144f20 100644 (file)
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -95,11 +95,13 @@ wire   W_CLK_12M,WB_CLK_12M;
 wire   W_CLK_6M,WB_CLK_6M;\r
 wire   W_CLK_6Mn;\r
 wire   W_STARS_CLK;\r
+wire   W_DCM_LOCKED;\r
 \r
 mc_dcm clockgen(\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r
-.CLKFX_OUT(W_CLK_36M)\r
+.CLKFX_OUT(W_CLK_36M),\r
+.LOCKED_OUT(W_DCM_LOCKED)\r
 );\r
 \r
 //------ H&V COUNTER -------------------------\r
@@ -147,6 +149,7 @@ wire   [7:0]W_VID_DO;
 mc_clock MC_CLK(\r
 \r
 .I_CLK_36M(W_CLK_36M),\r
+.I_DCM_LOCKED(W_DCM_LOCKED),\r
 .O_CLK_18M(W_CLK_18M),\r
 .O_CLK_12M(WB_CLK_12M),\r
 .O_CLK_06M(WB_CLK_6M),\r