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a126332a 1 //-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
534983d7 12#include "iso14443a.h"
f8ada309 13
534983d7 14static uint32_t iso14a_timeout;
1e262141 15int rsamples = 0;
1e262141 16uint8_t trigger = 0;
b0127e65 17// the block number for the ISO14443-4 PCB
18static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 19
0194ce8f 20static uint8_t* free_buffer_pointer;
21
7bc95e2e 22//
23// ISO14443 timing:
24//
25// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
26#define REQUEST_GUARD_TIME (7000/16 + 1)
27// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
28#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
29// bool LastCommandWasRequest = FALSE;
30
31//
32// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
33//
d714d3ef 34// When the PM acts as reader and is receiving tag data, it takes
35// 3 ticks delay in the AD converter
36// 16 ticks until the modulation detector completes and sets curbit
37// 8 ticks until bit_to_arm is assigned from curbit
38// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 39// 4*16 ticks until we measure the time
40// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 41#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 42
43// When the PM acts as a reader and is sending, it takes
44// 4*16 ticks until we can write data to the sending hold register
45// 8*16 ticks until the SHR is transferred to the Sending Shift Register
46// 8 ticks until the first transfer starts
47// 8 ticks later the FPGA samples the data
48// 1 tick to assign mod_sig_coil
49#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
50
51// When the PM acts as tag and is receiving it takes
d714d3ef 52// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 53// 3 ticks for the A/D conversion,
54// 8 ticks on average until the start of the SSC transfer,
55// 8 ticks until the SSC samples the first data
56// 7*16 ticks to complete the transfer from FPGA to ARM
57// 8 ticks until the next ssp_clk rising edge
d714d3ef 58// 4*16 ticks until we measure the time
7bc95e2e 59// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 60#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 61
62// The FPGA will report its internal sending delay in
63uint16_t FpgaSendQueueDelay;
64// the 5 first bits are the number of bits buffered in mod_sig_buf
65// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
66#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
67
68// When the PM acts as tag and is sending, it takes
d714d3ef 69// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 70// 8*16 ticks until the SHR is transferred to the Sending Shift Register
71// 8 ticks until the first transfer starts
72// 8 ticks later the FPGA samples the data
73// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
74// + 1 tick to assign mod_sig_coil
d714d3ef 75#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 76
77// When the PM acts as sniffer and is receiving tag data, it takes
78// 3 ticks A/D conversion
d714d3ef 79// 14 ticks to complete the modulation detection
80// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 81// + the delays in transferring data - which is the same for
82// sniffing reader and tag data and therefore not relevant
d714d3ef 83#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 84
d714d3ef 85// When the PM acts as sniffer and is receiving reader data, it takes
86// 2 ticks delay in analogue RF receiver (for the falling edge of the
87// start bit, which marks the start of the communication)
7bc95e2e 88// 3 ticks A/D conversion
d714d3ef 89// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 90// + the delays in transferring data - which is the same for
91// sniffing reader and tag data and therefore not relevant
d714d3ef 92#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 93
94//variables used for timing purposes:
95//these are in ssp_clk cycles:
6a1f2d82 96static uint32_t NextTransferTime;
97static uint32_t LastTimeProxToAirStart;
98static uint32_t LastProxToAirDuration;
7bc95e2e 99
8f51ddb0 100// CARD TO READER - manchester
72934aa3 101// Sequence D: 11110000 modulation with subcarrier during first half
102// Sequence E: 00001111 modulation with subcarrier during second half
103// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 104// READER TO CARD - miller
72934aa3 105// Sequence X: 00001100 drop after half a period
106// Sequence Y: 00000000 no drop
107// Sequence Z: 11000000 drop at start
108#define SEC_D 0xf0
109#define SEC_E 0x0f
110#define SEC_F 0x00
111#define SEC_X 0x0c
112#define SEC_Y 0x00
113#define SEC_Z 0xc0
15c4dc5a 114
902cb3c0 115void iso14a_set_trigger(bool enable) {
534983d7 116 trigger = enable;
117}
118
b0127e65 119void iso14a_set_timeout(uint32_t timeout) {
120 iso14a_timeout = timeout;
19a700a8 121 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
b0127e65 122}
8556b852 123
19a700a8 124void iso14a_set_ATS_timeout(uint8_t *ats) {
19a700a8 125 uint8_t tb1;
126 uint8_t fwi;
127 uint32_t fwt;
128
129 if (ats[0] > 1) { // there is a format byte T0
130 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
4c0cf2d2 131
132 if ((ats[1] & 0x10) == 0x10) // there is an interface byte TA(1) preceding TB(1)
19a700a8 133 tb1 = ats[3];
4c0cf2d2 134 else
19a700a8 135 tb1 = ats[2];
4c0cf2d2 136
19a700a8 137 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
ca5bad3d 138 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
139 //fwt = 4096 * (1 << fwi);
19a700a8 140
ca5bad3d 141 iso14a_set_timeout(fwt/(8*16));
142 //iso14a_set_timeout(fwt/128);
19a700a8 143 }
144 }
145}
146
15c4dc5a 147//-----------------------------------------------------------------------------
148// Generate the parity value for a byte sequence
e30c654b 149//
15c4dc5a 150//-----------------------------------------------------------------------------
91c7a7cc 151void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par) {
6a1f2d82 152 uint16_t paritybit_cnt = 0;
153 uint16_t paritybyte_cnt = 0;
154 uint8_t parityBits = 0;
155
156 for (uint16_t i = 0; i < iLen; i++) {
157 // Generate the parity bits
f8ada309 158 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
6a1f2d82 159 if (paritybit_cnt == 7) {
160 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
161 parityBits = 0; // and advance to next Parity Byte
162 paritybyte_cnt++;
163 paritybit_cnt = 0;
164 } else {
165 paritybit_cnt++;
166 }
5f6d6c90 167 }
6a1f2d82 168
169 // save remaining parity bits
91c7a7cc 170 par[paritybyte_cnt] = parityBits;
15c4dc5a 171}
172
91c7a7cc 173void AppendCrc14443a(uint8_t* data, int len) {
5f6d6c90 174 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 175}
176
7bc95e2e 177//=============================================================================
178// ISO 14443 Type A - Miller decoder
179//=============================================================================
180// Basics:
181// This decoder is used when the PM3 acts as a tag.
182// The reader will generate "pauses" by temporarily switching of the field.
183// At the PM3 antenna we will therefore measure a modulated antenna voltage.
184// The FPGA does a comparison with a threshold and would deliver e.g.:
185// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
186// The Miller decoder needs to identify the following sequences:
187// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
188// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
189// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
190// Note 1: the bitstream may start at any time. We therefore need to sync.
191// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 192//-----------------------------------------------------------------------------
b62a5a84 193static tUart Uart;
15c4dc5a 194
d7aa3739 195// Lookup-Table to decide if 4 raw bits are a modulation.
0ec548dc 196// We accept the following:
197// 0001 - a 3 tick wide pause
198// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
199// 0111 - a 2 tick wide pause shifted left
200// 1001 - a 2 tick wide pause shifted right
d7aa3739 201const bool Mod_Miller_LUT[] = {
0ec548dc 202 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
203 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
d7aa3739 204};
0ec548dc 205#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
206#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 207
91c7a7cc 208void UartReset() {
7bc95e2e 209 Uart.state = STATE_UNSYNCD;
210 Uart.bitCount = 0;
211 Uart.len = 0; // number of decoded data bytes
6a1f2d82 212 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 213 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 214 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 215 Uart.startTime = 0;
216 Uart.endTime = 0;
46c65fed 217
218 Uart.byteCntMax = 0;
219 Uart.posCnt = 0;
220 Uart.syncBit = 9999;
7bc95e2e 221}
15c4dc5a 222
91c7a7cc 223void UartInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 224 Uart.output = data;
225 Uart.parity = parity;
0ec548dc 226 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
6a1f2d82 227 UartReset();
228}
d714d3ef 229
7bc95e2e 230// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 231static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time) {
0ec548dc 232 Uart.fourBits = (Uart.fourBits << 8) | bit;
7bc95e2e 233
0c8d25eb 234 if (Uart.state == STATE_UNSYNCD) { // not yet synced
91c7a7cc 235 Uart.syncBit = 9999; // not set
46c65fed 236
237 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
238 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
239 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
240
0ec548dc 241 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
46c65fed 242 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
243 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
0ec548dc 244 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
46c65fed 245 //
246#define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
247#define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
248
0ec548dc 249 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
250 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
251 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
252 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
253 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
254 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
255 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
256 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
257
258 if (Uart.syncBit != 9999) { // found a sync bit
91c7a7cc 259 Uart.startTime = non_real_time ? non_real_time : (GetCountSspClk() & 0xfffffff8);
260 Uart.startTime -= Uart.syncBit;
261 Uart.endTime = Uart.startTime;
262 Uart.state = STATE_START_OF_COMMUNICATION;
263 }
7bc95e2e 264 } else {
15c4dc5a 265
0ec548dc 266 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
267 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
d7aa3739 268 UartReset();
d7aa3739 269 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 270 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
271 UartReset();
7bc95e2e 272 } else {
273 Uart.bitCount++;
274 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
275 Uart.state = STATE_MILLER_Z;
276 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
277 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
278 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
279 Uart.parityBits <<= 1; // make room for the parity bit
280 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
281 Uart.bitCount = 0;
282 Uart.shiftReg = 0;
6a1f2d82 283 if((Uart.len&0x0007) == 0) { // every 8 data bytes
284 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
285 Uart.parityBits = 0;
286 }
15c4dc5a 287 }
7bc95e2e 288 }
d7aa3739 289 }
290 } else {
0ec548dc 291 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 292 Uart.bitCount++;
293 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
294 Uart.state = STATE_MILLER_X;
295 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
296 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
297 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
298 Uart.parityBits <<= 1; // make room for the new parity bit
299 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
300 Uart.bitCount = 0;
301 Uart.shiftReg = 0;
6a1f2d82 302 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
303 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
304 Uart.parityBits = 0;
305 }
7bc95e2e 306 }
d7aa3739 307 } else { // no modulation in both halves - Sequence Y
7bc95e2e 308 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 309 Uart.state = STATE_UNSYNCD;
6a1f2d82 310 Uart.bitCount--; // last "0" was part of EOC sequence
311 Uart.shiftReg <<= 1; // drop it
312 if(Uart.bitCount > 0) { // if we decoded some bits
313 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
314 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
315 Uart.parityBits <<= 1; // add a (void) parity bit
316 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
317 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
318 return TRUE;
319 } else if (Uart.len & 0x0007) { // there are some parity bits to store
320 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
321 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 322 }
323 if (Uart.len) {
6a1f2d82 324 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 325 } else {
0c8d25eb 326 UartReset(); // Nothing received - start over
7bc95e2e 327 }
15c4dc5a 328 }
7bc95e2e 329 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
330 UartReset();
7bc95e2e 331 } else { // a logic "0"
332 Uart.bitCount++;
333 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
334 Uart.state = STATE_MILLER_Y;
335 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
336 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
337 Uart.parityBits <<= 1; // make room for the parity bit
338 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
339 Uart.bitCount = 0;
340 Uart.shiftReg = 0;
6a1f2d82 341 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
342 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
343 Uart.parityBits = 0;
344 }
15c4dc5a 345 }
346 }
d7aa3739 347 }
15c4dc5a 348 }
7bc95e2e 349 }
7bc95e2e 350 return FALSE; // not finished yet, need more data
15c4dc5a 351}
352
353//=============================================================================
e691fc45 354// ISO 14443 Type A - Manchester decoder
15c4dc5a 355//=============================================================================
e691fc45 356// Basics:
7bc95e2e 357// This decoder is used when the PM3 acts as a reader.
e691fc45 358// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
359// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
360// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
361// The Manchester decoder needs to identify the following sequences:
362// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
363// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
364// 8 ticks unmodulated: Sequence F = end of communication
365// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 366// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 367// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 368static tDemod Demod;
15c4dc5a 369
d7aa3739 370// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 371// We accept three or four "1" in any position
7bc95e2e 372const bool Mod_Manchester_LUT[] = {
d7aa3739 373 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 374 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 375};
376
377#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
378#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 379
91c7a7cc 380void DemodReset() {
7bc95e2e 381 Demod.state = DEMOD_UNSYNCD;
382 Demod.len = 0; // number of decoded data bytes
6a1f2d82 383 Demod.parityLen = 0;
7bc95e2e 384 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
385 Demod.parityBits = 0; //
386 Demod.collisionPos = 0; // Position of collision bit
387 Demod.twoBits = 0xffff; // buffer for 2 Bits
388 Demod.highCnt = 0;
389 Demod.startTime = 0;
91c7a7cc 390 Demod.endTime = 0;
46c65fed 391 Demod.bitCount = 0;
392 Demod.syncBit = 0xFFFF;
393 Demod.samples = 0;
e691fc45 394}
15c4dc5a 395
91c7a7cc 396void DemodInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 397 Demod.output = data;
398 Demod.parity = parity;
399 DemodReset();
400}
401
7bc95e2e 402// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 403static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time) {
7bc95e2e 404 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 405
7bc95e2e 406 if (Demod.state == DEMOD_UNSYNCD) {
407
408 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
409 if (Demod.twoBits == 0x0000) {
410 Demod.highCnt++;
411 } else {
412 Demod.highCnt = 0;
413 }
414 } else {
415 Demod.syncBit = 0xFFFF; // not set
416 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
417 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
418 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
419 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
420 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
421 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
422 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
423 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 424 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 425 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
426 Demod.startTime -= Demod.syncBit;
427 Demod.bitCount = offset; // number of decoded data bits
e691fc45 428 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 429 }
7bc95e2e 430 }
7bc95e2e 431 } else {
15c4dc5a 432
7bc95e2e 433 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
434 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 435 if (!Demod.collisionPos) {
436 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
437 }
438 } // modulation in first half only - Sequence D = 1
7bc95e2e 439 Demod.bitCount++;
440 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
441 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 442 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 443 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 444 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
445 Demod.bitCount = 0;
446 Demod.shiftReg = 0;
6a1f2d82 447 if((Demod.len&0x0007) == 0) { // every 8 data bytes
448 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
449 Demod.parityBits = 0;
450 }
15c4dc5a 451 }
7bc95e2e 452 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
453 } else { // no modulation in first half
454 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 455 Demod.bitCount++;
7bc95e2e 456 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 457 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 458 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 459 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 460 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
461 Demod.bitCount = 0;
462 Demod.shiftReg = 0;
6a1f2d82 463 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
464 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
465 Demod.parityBits = 0;
466 }
15c4dc5a 467 }
7bc95e2e 468 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 469 } else { // no modulation in both halves - End of communication
6a1f2d82 470 if(Demod.bitCount > 0) { // there are some remaining data bits
471 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
472 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
473 Demod.parityBits <<= 1; // add a (void) parity bit
474 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
475 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
476 return TRUE;
477 } else if (Demod.len & 0x0007) { // there are some parity bits to store
478 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
479 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 480 }
481 if (Demod.len) {
d7aa3739 482 return TRUE; // we are finished with decoding the raw data sequence
483 } else { // nothing received. Start over
484 DemodReset();
e691fc45 485 }
15c4dc5a 486 }
7bc95e2e 487 }
e691fc45 488 }
e691fc45 489 return FALSE; // not finished yet, need more data
15c4dc5a 490}
491
492//=============================================================================
493// Finally, a `sniffer' for ISO 14443 Type A
494// Both sides of communication!
495//=============================================================================
496
497//-----------------------------------------------------------------------------
498// Record the sequence of commands sent by the reader to the tag, with
499// triggering so that we start recording at the point that the tag is moved
500// near the reader.
bc939371 501// "hf 14a sniff"
15c4dc5a 502//-----------------------------------------------------------------------------
d26849d4 503void RAMFUNC SniffIso14443a(uint8_t param) {
5cd9ec01
M
504 // param:
505 // bit 0 - trigger from first card answer
506 // bit 1 - trigger from first reader 7-bit request
5cd9ec01 507 LEDsoff();
5cd9ec01 508
99cf19d9 509 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
7bc95e2e 510
f71f4deb 511 // Allocate memory from BigBuf for some buffers
512 // free all previous allocations first
aaa1a9a2 513 BigBuf_free(); BigBuf_Clear_ext(false);
7838f4be 514 clear_trace();
515 set_tracing(TRUE);
516
5cd9ec01 517 // The command (reader -> tag) that we're receiving.
f71f4deb 518 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
519 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 520
5cd9ec01 521 // The response (tag -> reader) that we're receiving.
f71f4deb 522 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
523 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
524
525 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 526 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
527
7bc95e2e 528 uint8_t *data = dmaBuf;
529 uint8_t previous_data = 0;
5cd9ec01
M
530 int maxDataLen = 0;
531 int dataLen = 0;
7bc95e2e 532 bool TagIsActive = FALSE;
533 bool ReaderIsActive = FALSE;
534
5cd9ec01 535 // Set up the demodulator for tag -> reader responses.
6a1f2d82 536 DemodInit(receivedResponse, receivedResponsePar);
537
5cd9ec01 538 // Set up the demodulator for the reader -> tag commands
6a1f2d82 539 UartInit(receivedCmd, receivedCmdPar);
540
7bc95e2e 541 // Setup and start DMA.
57850d9d 542 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
543 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
544 return;
545 }
7bc95e2e 546
99cf19d9 547 // We won't start recording the frames that we acquire until we trigger;
548 // a good trigger condition to get started is probably when we see a
549 // response from the tag.
550 // triggered == FALSE -- to wait first for card
551 bool triggered = !(param & 0x03);
552
5cd9ec01 553 // And now we loop, receiving samples.
7bc95e2e 554 for(uint32_t rsamples = 0; TRUE; ) {
555
5cd9ec01
M
556 if(BUTTON_PRESS()) {
557 DbpString("cancelled by button");
7bc95e2e 558 break;
5cd9ec01 559 }
15c4dc5a 560
5cd9ec01
M
561 LED_A_ON();
562 WDT_HIT();
15c4dc5a 563
5cd9ec01
M
564 int register readBufDataP = data - dmaBuf;
565 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
566 if (readBufDataP <= dmaBufDataP){
567 dataLen = dmaBufDataP - readBufDataP;
568 } else {
7bc95e2e 569 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
570 }
571 // test for length of buffer
572 if(dataLen > maxDataLen) {
573 maxDataLen = dataLen;
f71f4deb 574 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 575 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
576 break;
5cd9ec01
M
577 }
578 }
579 if(dataLen < 1) continue;
580
581 // primary buffer was stopped( <-- we lost data!
582 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
583 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
584 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 585 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
586 }
587 // secondary buffer sets as primary, secondary buffer was stopped
588 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
589 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
590 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
591 }
592
593 LED_A_OFF();
7bc95e2e 594
595 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 596
7bc95e2e 597 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
598 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
599 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
600 LED_C_ON();
5cd9ec01 601
7bc95e2e 602 // check - if there is a short 7bit request from reader
603 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 604
7bc95e2e 605 if(triggered) {
6a1f2d82 606 if (!LogTrace(receivedCmd,
607 Uart.len,
608 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
609 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
610 Uart.parity,
611 TRUE)) break;
7bc95e2e 612 }
613 /* And ready to receive another command. */
614 UartReset();
615 /* And also reset the demod code, which might have been */
616 /* false-triggered by the commands from the reader. */
617 DemodReset();
618 LED_B_OFF();
619 }
620 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 621 }
3be2a5ae 622
7bc95e2e 623 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
624 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
625 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
626 LED_B_ON();
5cd9ec01 627
6a1f2d82 628 if (!LogTrace(receivedResponse,
629 Demod.len,
630 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
631 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
632 Demod.parity,
633 FALSE)) break;
5cd9ec01 634
7bc95e2e 635 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 636
7bc95e2e 637 // And ready to receive another response.
638 DemodReset();
0ec548dc 639 // And reset the Miller decoder including itS (now outdated) input buffer
640 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 641 LED_C_OFF();
642 }
643 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
644 }
5cd9ec01
M
645 }
646
7bc95e2e 647 previous_data = *data;
648 rsamples++;
5cd9ec01 649 data++;
d714d3ef 650 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
651 data = dmaBuf;
652 }
653 } // main cycle
654
bc939371 655 if (MF_DBGLEVEL >= 1) {
656 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
657 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
658 }
7bc95e2e 659 FpgaDisableSscDma();
91c7a7cc 660 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
bc939371 661 LEDsoff();
5ee53a0e 662 set_tracing(FALSE);
15c4dc5a 663}
664
15c4dc5a 665//-----------------------------------------------------------------------------
666// Prepare tag messages
667//-----------------------------------------------------------------------------
91c7a7cc 668static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity) {
8f51ddb0 669 ToSendReset();
15c4dc5a 670
671 // Correction bit, might be removed when not needed
672 ToSendStuffBit(0);
673 ToSendStuffBit(0);
674 ToSendStuffBit(0);
675 ToSendStuffBit(0);
676 ToSendStuffBit(1); // 1
677 ToSendStuffBit(0);
678 ToSendStuffBit(0);
679 ToSendStuffBit(0);
8f51ddb0 680
15c4dc5a 681 // Send startbit
72934aa3 682 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 683 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 684
6a1f2d82 685 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 686 uint8_t b = cmd[i];
15c4dc5a 687
688 // Data bits
6a1f2d82 689 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 690 if(b & 1) {
72934aa3 691 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 692 } else {
72934aa3 693 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
694 }
695 b >>= 1;
696 }
15c4dc5a 697
0014cb46 698 // Get the parity bit
6a1f2d82 699 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 700 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 701 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 702 } else {
72934aa3 703 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 704 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 705 }
8f51ddb0 706 }
15c4dc5a 707
8f51ddb0
M
708 // Send stopbit
709 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 710
8f51ddb0 711 // Convert from last byte pos to length
6fc68747 712 ++ToSendMax;
8f51ddb0
M
713}
714
91c7a7cc 715static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len) {
7504dc50 716 uint8_t par[MAX_PARITY_SIZE] = {0};
6a1f2d82 717 GetParity(cmd, len, par);
718 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 719}
720
91c7a7cc 721static void Code4bitAnswerAsTag(uint8_t cmd) {
91c7a7cc 722 uint8_t b = cmd;
8f51ddb0 723
5f6d6c90 724 ToSendReset();
8f51ddb0
M
725
726 // Correction bit, might be removed when not needed
727 ToSendStuffBit(0);
728 ToSendStuffBit(0);
729 ToSendStuffBit(0);
730 ToSendStuffBit(0);
731 ToSendStuffBit(1); // 1
732 ToSendStuffBit(0);
733 ToSendStuffBit(0);
734 ToSendStuffBit(0);
735
736 // Send startbit
737 ToSend[++ToSendMax] = SEC_D;
738
0194ce8f 739 for(uint8_t i = 0; i < 4; i++) {
8f51ddb0
M
740 if(b & 1) {
741 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 742 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
743 } else {
744 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 745 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
746 }
747 b >>= 1;
748 }
749
750 // Send stopbit
751 ToSend[++ToSendMax] = SEC_F;
752
5f6d6c90 753 // Convert from last byte pos to length
754 ToSendMax++;
15c4dc5a 755}
756
757//-----------------------------------------------------------------------------
758// Wait for commands from reader
759// Stop when button is pressed
760// Or return TRUE when command is captured
761//-----------------------------------------------------------------------------
91c7a7cc 762static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len) {
15c4dc5a 763 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
764 // only, since we are receiving, not transmitting).
765 // Signal field is off with the appropriate LED
766 LED_D_OFF();
767 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
768
ca5bad3d 769 // Now run a `software UART` on the stream of incoming samples.
6a1f2d82 770 UartInit(received, parity);
7bc95e2e 771
772 // clear RXRDY:
773 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 774
775 for(;;) {
776 WDT_HIT();
777
778 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 779
15c4dc5a 780 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 781 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
782 if(MillerDecoding(b, 0)) {
783 *len = Uart.len;
15c4dc5a 784 return TRUE;
785 }
7bc95e2e 786 }
15c4dc5a 787 }
788}
28afbd2b 789
ce02f6f9 790bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 791 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 792 // This will need the following byte array for a modulation sequence
793 // 144 data bits (18 * 8)
794 // 18 parity bits
795 // 2 Start and stop
796 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
797 // 1 just for the case
798 // ----------- +
799 // 166 bytes, since every bit that needs to be send costs us a byte
800 //
91c7a7cc 801 // Prepare the tag modulation bits from the message
802 CodeIso14443aAsTag(response_info->response,response_info->response_n);
803
804 // Make sure we do not exceed the free buffer space
805 if (ToSendMax > max_buffer_size) {
806 Dbprintf("Out of memory, when modulating bits for tag answer:");
807 Dbhexdump(response_info->response_n,response_info->response,false);
808 return FALSE;
809 }
810
811 // Copy the byte array, used for this modulation to the buffer position
812 memcpy(response_info->modulation,ToSend,ToSendMax);
813
814 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
815 response_info->modulation_n = ToSendMax;
816 response_info->ProxToAirDuration = LastProxToAirDuration;
817 return TRUE;
ce02f6f9 818}
819
f71f4deb 820// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
821// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
822// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
823// -> need 273 bytes buffer
c9216a92 824// 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
825// 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
826#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
f71f4deb 827
ce02f6f9 828bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
ca5bad3d 829 // Retrieve and store the current buffer index
830 response_info->modulation = free_buffer_pointer;
831
832 // Determine the maximum size we can use from our buffer
833 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
834
835 // Forward the prepare tag modulation function to the inner function
836 if (prepare_tag_modulation(response_info, max_buffer_size)) {
837 // Update the free buffer offset
838 free_buffer_pointer += ToSendMax;
839 return true;
840 } else {
841 return false;
842 }
ce02f6f9 843}
844
15c4dc5a 845//-----------------------------------------------------------------------------
846// Main loop of simulated tag: receive commands from reader, decide what
847// response to send, and send it.
0a856e29 848// 'hf 14a sim'
15c4dc5a 849//-----------------------------------------------------------------------------
91c7a7cc 850void SimulateIso14443aTag(int tagType, int flags, byte_t* data) {
0194ce8f 851
bf5d7992 852 #define ATTACK_KEY_COUNT 8 // keep same as define in cmdhfmf.c -> readerAttack()
e99acd00 853 // init pseudorand
854 fast_prand();
bf5d7992 855
0194ce8f 856 uint8_t sak = 0;
bc939371 857 uint32_t cuid = 0;
858 uint32_t nonce = 0;
859
32719adf 860 // PACK response to PWD AUTH for EV1/NTAG
0194ce8f 861 uint8_t response8[4] = {0,0,0,0};
862 // Counter for EV1/NTAG
863 uint32_t counters[] = {0,0,0};
32719adf 864
81cd0474 865 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
0194ce8f 866 uint8_t response1[] = {0,0};
6b23be6b 867
868 // Here, we collect CUID, block1, keytype1, NT1, NR1, AR1, CUID, block2, keytyp2, NT2, NR2, AR2
869 // it should also collect block, keytype.
870 uint8_t cardAUTHSC = 0;
871 uint8_t cardAUTHKEY = 0xff; // no authentication
872 // allow collecting up to 8 sets of nonces to allow recovery of up to 8 keys
bf5d7992 873
84bdbc19 874 nonces_t ar_nr_nonces[ATTACK_KEY_COUNT]; // for attack types moebius
875 memset(ar_nr_nonces, 0x00, sizeof(ar_nr_nonces));
876 uint8_t moebius_count = 0;
81cd0474 877
878 switch (tagType) {
0194ce8f 879 case 1: { // MIFARE Classic 1k
81cd0474 880 response1[0] = 0x04;
81cd0474 881 sak = 0x08;
882 } break;
883 case 2: { // MIFARE Ultralight
32719adf 884 response1[0] = 0x44;
81cd0474 885 sak = 0x00;
886 } break;
887 case 3: { // MIFARE DESFire
81cd0474 888 response1[0] = 0x04;
889 response1[1] = 0x03;
890 sak = 0x20;
891 } break;
0194ce8f 892 case 4: { // ISO/IEC 14443-4 - javacard (JCOP)
81cd0474 893 response1[0] = 0x04;
81cd0474 894 sak = 0x28;
895 } break;
3fe4ff4f 896 case 5: { // MIFARE TNP3XXX
3fe4ff4f 897 response1[0] = 0x01;
898 response1[1] = 0x0f;
899 sak = 0x01;
d26849d4 900 } break;
0194ce8f 901 case 6: { // MIFARE Mini 320b
d26849d4 902 response1[0] = 0x44;
d26849d4 903 sak = 0x09;
904 } break;
0194ce8f 905 case 7: { // NTAG
32719adf 906 response1[0] = 0x44;
32719adf 907 sak = 0x00;
908 // PACK
909 response8[0] = 0x80;
910 response8[1] = 0x80;
911 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
2b1f4228 912 // uid not supplied then get from emulator memory
913 if (data[0]==0) {
914 uint16_t start = 4 * (0+12);
915 uint8_t emdata[8];
916 emlGetMemBt( emdata, start, sizeof(emdata));
f38cfd66 917 memcpy(data, emdata, 3); // uid bytes 0-2
918 memcpy(data+3, emdata+4, 4); // uid bytes 3-7
2b1f4228 919 flags |= FLAG_7B_UID_IN_DATA;
920 }
32719adf 921 } break;
81cd0474 922 default: {
923 Dbprintf("Error: unkown tagtype (%d)",tagType);
924 return;
925 } break;
926 }
927
928 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 929 uint8_t response2[5] = {0x00};
81cd0474 930
0194ce8f 931 // For UID size 7,
c8b6da22 932 uint8_t response2a[5] = {0x00};
933
bc939371 934 if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA ) {
0194ce8f 935 response2[0] = 0x88; // Cascade Tag marker
d26849d4 936 response2[1] = data[0];
937 response2[2] = data[1];
938 response2[3] = data[2];
939
940 response2a[0] = data[3];
941 response2a[1] = data[4];
942 response2a[2] = data[5];
c3c241f3 943 response2a[3] = data[6]; //??
81cd0474 944 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
945
946 // Configure the ATQA and SAK accordingly
947 response1[0] |= 0x40;
948 sak |= 0x04;
bc939371 949
950 cuid = bytes_to_num(data+3, 4);
81cd0474 951 } else {
d26849d4 952 memcpy(response2, data, 4);
81cd0474 953 // Configure the ATQA and SAK accordingly
954 response1[0] &= 0xBF;
955 sak &= 0xFB;
bc939371 956 cuid = bytes_to_num(data, 4);
81cd0474 957 }
958
959 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
960 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
961
962 // Prepare the mandatory SAK (for 4 and 7 byte UID)
0194ce8f 963 uint8_t response3[3] = {sak, 0x00, 0x00};
81cd0474 964 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
965
966 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 967 uint8_t response3a[3] = {0x00};
81cd0474 968 response3a[0] = sak & 0xFB;
969 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
970
bf5d7992 971 // Tag NONCE.
972 uint8_t response5[4];
bf5d7992 973
0194ce8f 974 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
6a1f2d82 975 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
976 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
977 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
978 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 979 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
bc939371 980
2b1f4228 981 // Prepare GET_VERSION (different for UL EV-1 / NTAG)
f38cfd66 982 // uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
983 // uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
c9216a92 984 // Prepare CHK_TEARING
f38cfd66 985 // uint8_t response9[] = {0xBD,0x90,0x3f};
c9216a92 986
987 #define TAG_RESPONSE_COUNT 10
7bc95e2e 988 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
989 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
990 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
991 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
992 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
993 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
994 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
995 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
4c0cf2d2 996
495d7f13 997 { .response = response8, .response_n = sizeof(response8) } // EV1/NTAG PACK response
4c0cf2d2 998 };
f38cfd66 999 // { .response = response7_NTAG, .response_n = sizeof(response7_NTAG)}, // EV1/NTAG GET_VERSION response
1000 // { .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
4c0cf2d2 1001
7bc95e2e 1002
1003 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1004 // Such a response is less time critical, so we can prepare them on the fly
1005 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1006 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1007 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1008 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1009 tag_response_info_t dynamic_response_info = {
1010 .response = dynamic_response_buffer,
1011 .response_n = 0,
1012 .modulation = dynamic_modulation_buffer,
1013 .modulation_n = 0
1014 };
ce02f6f9 1015
99cf19d9 1016 // We need to listen to the high-frequency, peak-detected path.
1017 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1018
f71f4deb 1019 BigBuf_free_keep_EM();
0194ce8f 1020 clear_trace();
1021 set_tracing(TRUE);
f71f4deb 1022
1023 // allocate buffers:
1024 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1025 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1026 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1027
7bc95e2e 1028 // Prepare the responses of the anticollision phase
ce02f6f9 1029 // there will be not enough time to do this at the moment the reader sends it REQA
495d7f13 1030 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++)
7bc95e2e 1031 prepare_allocated_tag_modulation(&responses[i]);
15c4dc5a 1032
7bc95e2e 1033 int len = 0;
15c4dc5a 1034
1035 // To control where we are in the protocol
1036 int order = 0;
1037 int lastorder;
1038
1039 // Just to allow some checks
1040 int happened = 0;
1041 int happened2 = 0;
81cd0474 1042 int cmdsRecvd = 0;
7bc95e2e 1043 tag_response_info_t* p_response;
15c4dc5a 1044
254b70a4 1045 LED_A_ON();
0194ce8f 1046 for(;;) {
4c0cf2d2 1047 WDT_HIT();
1048
7bc95e2e 1049 // Clean receive command buffer
6a1f2d82 1050 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
84bdbc19 1051 Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
254b70a4 1052 break;
7e735c13 1053 }
7bc95e2e 1054 p_response = NULL;
1055
254b70a4 1056 // Okay, look at the command now.
1057 lastorder = order;
0194ce8f 1058 if(receivedCmd[0] == ISO14443A_CMD_REQA) { // Received a REQUEST
ce02f6f9 1059 p_response = &responses[0]; order = 1;
0194ce8f 1060 } else if(receivedCmd[0] == ISO14443A_CMD_WUPA) { // Received a WAKEUP
ce02f6f9 1061 p_response = &responses[0]; order = 6;
0194ce8f 1062 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received request for UID (cascade 1)
ce02f6f9 1063 p_response = &responses[1]; order = 2;
0194ce8f 1064 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received request for UID (cascade 2)
ce02f6f9 1065 p_response = &responses[2]; order = 20;
0194ce8f 1066 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received a SELECT (cascade 1)
ce02f6f9 1067 p_response = &responses[3]; order = 3;
0194ce8f 1068 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received a SELECT (cascade 2)
1069 p_response = &responses[4]; order = 30;
1070 } else if(receivedCmd[0] == ISO14443A_CMD_READBLOCK) { // Received a (plain) READ
32719adf 1071 uint8_t block = receivedCmd[1];
2b1f4228 1072 // if Ultralight or NTAG (4 byte blocks)
1073 if ( tagType == 7 || tagType == 2 ) {
f38cfd66 1074 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
2b1f4228 1075 uint16_t start = 4 * (block+12);
6b23be6b 1076 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1077 emlGetMemBt( emdata, start, 16);
1078 AppendCrc14443a(emdata, 16);
1079 EmSendCmdEx(emdata, sizeof(emdata), false);
2b1f4228 1080 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
32719adf 1081 p_response = NULL;
2b1f4228 1082 } else { // all other tags (16 byte block tags)
6b23be6b 1083 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1084 emlGetMemBt( emdata, block, 16);
1085 AppendCrc14443a(emdata, 16);
1086 EmSendCmdEx(emdata, sizeof(emdata), false);
f38cfd66 1087 // EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
32719adf 1088 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1089 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1090 p_response = NULL;
1091 }
0194ce8f 1092 } else if(receivedCmd[0] == MIFARE_ULEV1_FASTREAD) { // Received a FAST READ (ranged read)
91c7a7cc 1093 uint8_t emdata[MAX_FRAME_SIZE];
f38cfd66 1094 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
91c7a7cc 1095 int start = (receivedCmd[1]+12) * 4;
1096 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
1097 emlGetMemBt( emdata, start, len);
1098 AppendCrc14443a(emdata, len);
1099 EmSendCmdEx(emdata, len+2, false);
1100 p_response = NULL;
0194ce8f 1101 } else if(receivedCmd[0] == MIFARE_ULEV1_READSIG && tagType == 7) { // Received a READ SIGNATURE --
f38cfd66 1102 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
91c7a7cc 1103 uint16_t start = 4 * 4;
1104 uint8_t emdata[34];
1105 emlGetMemBt( emdata, start, 32);
1106 AppendCrc14443a(emdata, 32);
1107 EmSendCmdEx(emdata, sizeof(emdata), false);
1108 p_response = NULL;
0194ce8f 1109 } else if (receivedCmd[0] == MIFARE_ULEV1_READ_CNT && tagType == 7) { // Received a READ COUNTER --
e9a92fe2 1110 uint8_t index = receivedCmd[1];
16cfceb6 1111 uint8_t cmd[] = {0x00,0x00,0x00,0x14,0xa5};
e9a92fe2 1112 if ( counters[index] > 0) {
16cfceb6 1113 num_to_bytes(counters[index], 3, cmd);
1114 AppendCrc14443a(cmd, sizeof(cmd)-2);
e9a92fe2 1115 }
16cfceb6 1116 EmSendCmdEx(cmd,sizeof(cmd),false);
a126332a 1117 p_response = NULL;
0194ce8f 1118 } else if (receivedCmd[0] == MIFARE_ULEV1_INCR_CNT && tagType == 7) { // Received a INC COUNTER --
ce3d6bd2 1119 // number of counter
a126332a 1120 uint8_t counter = receivedCmd[1];
1121 uint32_t val = bytes_to_num(receivedCmd+2,4);
1122 counters[counter] = val;
1123
ce3d6bd2 1124 // send ACK
1125 uint8_t ack[] = {0x0a};
1126 EmSendCmdEx(ack,sizeof(ack),false);
91c7a7cc 1127 p_response = NULL;
0194ce8f 1128 } else if(receivedCmd[0] == MIFARE_ULEV1_CHECKTEAR && tagType == 7) { // Received a CHECK_TEARING_EVENT --
f38cfd66 1129 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
2b1f4228 1130 uint8_t emdata[3];
1131 uint8_t counter=0;
1132 if (receivedCmd[1]<3) counter = receivedCmd[1];
1133 emlGetMemBt( emdata, 10+counter, 1);
1134 AppendCrc14443a(emdata, sizeof(emdata)-2);
1135 EmSendCmdEx(emdata, sizeof(emdata), false);
b0300679 1136 p_response = NULL;
0194ce8f 1137 } else if(receivedCmd[0] == ISO14443A_CMD_HALT) { // Received a HALT
810f5379 1138 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1139 p_response = NULL;
57850d9d 1140 } else if(receivedCmd[0] == MIFARE_AUTH_KEYA || receivedCmd[0] == MIFARE_AUTH_KEYB) { // Received an authentication request
32719adf 1141 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
2b1f4228 1142 uint8_t emdata[10];
1143 emlGetMemBt( emdata, 0, 8 );
1144 AppendCrc14443a(emdata, sizeof(emdata)-2);
6b23be6b 1145 EmSendCmdEx(emdata, sizeof(emdata), false);
2b1f4228 1146 p_response = NULL;
32719adf 1147 } else {
84bdbc19 1148
1149 cardAUTHKEY = receivedCmd[0] - 0x60;
1150 cardAUTHSC = receivedCmd[1] / 4; // received block num
7e735c13 1151
84bdbc19 1152 // incease nonce at AUTH requests. this is time consuming.
7e735c13 1153 nonce = prand();
84bdbc19 1154 //num_to_bytes(nonce, 4, response5);
1155 num_to_bytes(nonce, 4, dynamic_response_info.response);
1156 dynamic_response_info.response_n = 4;
1157
1158 //prepare_tag_modulation(&responses[5], DYNAMIC_MODULATION_BUFFER_SIZE);
1159 prepare_tag_modulation(&dynamic_response_info, DYNAMIC_MODULATION_BUFFER_SIZE);
1160 p_response = &dynamic_response_info;
1161 //p_response = &responses[5];
1162 order = 7;
32719adf 1163 }
0194ce8f 1164 } else if(receivedCmd[0] == ISO14443A_CMD_RATS) { // Received a RATS request
7bc95e2e 1165 if (tagType == 1 || tagType == 2) { // RATS not supported
1166 EmSend4bit(CARD_NACK_NA);
1167 p_response = NULL;
1168 } else {
1169 p_response = &responses[6]; order = 70;
1170 }
6a1f2d82 1171 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
810f5379 1172 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1173 uint32_t nr = bytes_to_num(receivedCmd,4);
1174 uint32_t ar = bytes_to_num(receivedCmd+4,4);
7e735c13 1175
6b23be6b 1176 // Collect AR/NR per keytype & sector
bc939371 1177 if ( (flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) {
bf5d7992 1178
84bdbc19 1179 int8_t index = -1;
1180 int8_t empty = -1;
1181 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
1182 // find which index to use
1183 if ( (cardAUTHSC == ar_nr_nonces[i].sector) && (cardAUTHKEY == ar_nr_nonces[i].keytype))
1184 index = i;
1185
1186 // keep track of empty slots.
1187 if ( ar_nr_nonces[i].state == EMPTY)
1188 empty = i;
1189 }
1190 // if no empty slots. Choose first and overwrite.
1191 if ( index == -1 ) {
1192 if ( empty == -1 ) {
1193 index = 0;
1194 ar_nr_nonces[index].state = EMPTY;
1195 } else {
1196 index = empty;
1197 }
1198 }
1199
1200 switch(ar_nr_nonces[index].state) {
1201 case EMPTY: {
1202 // first nonce collect
1203 ar_nr_nonces[index].cuid = cuid;
1204 ar_nr_nonces[index].sector = cardAUTHSC;
1205 ar_nr_nonces[index].keytype = cardAUTHKEY;
1206 ar_nr_nonces[index].nonce = nonce;
1207 ar_nr_nonces[index].nr = nr;
1208 ar_nr_nonces[index].ar = ar;
1209 ar_nr_nonces[index].state = FIRST;
1210 break;
1211 }
1212 case FIRST : {
1213 // second nonce collect
1214 ar_nr_nonces[index].nonce2 = nonce;
1215 ar_nr_nonces[index].nr2 = nr;
1216 ar_nr_nonces[index].ar2 = ar;
1217 ar_nr_nonces[index].state = SECOND;
1218
1219 // send to client
1220 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, 0, 0, &ar_nr_nonces[index], sizeof(nonces_t));
bf5d7992 1221
84bdbc19 1222 ar_nr_nonces[index].state = EMPTY;
1223 ar_nr_nonces[index].sector = 0;
1224 ar_nr_nonces[index].keytype = 0;
1225
1226 moebius_count++;
1227 break;
d26849d4 1228 }
84bdbc19 1229 default: break;
d26849d4 1230 }
84bdbc19 1231 }
1232 p_response = NULL;
57850d9d 1233
0194ce8f 1234 } else if (receivedCmd[0] == MIFARE_ULC_AUTH_1 ) { // ULC authentication, or Desfire Authentication
1235 } else if (receivedCmd[0] == MIFARE_ULEV1_AUTH) { // NTAG / EV-1 authentication
32719adf 1236 if ( tagType == 7 ) {
f38cfd66 1237 uint16_t start = 13; // first 4 blocks of emu are [getversion answer - check tearing - pack - 0x00]
2b1f4228 1238 uint8_t emdata[4];
1239 emlGetMemBt( emdata, start, 2);
1240 AppendCrc14443a(emdata, 2);
1241 EmSendCmdEx(emdata, sizeof(emdata), false);
1242 p_response = NULL;
ce3d6bd2 1243 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
e98572a1 1244
91c7a7cc 1245 if ( MF_DBGLEVEL >= 3) Dbprintf("Auth attempt: %08x", pwd);
32719adf 1246 }
2b1f4228 1247 } else {
7bc95e2e 1248 // Check for ISO 14443A-4 compliant commands, look at left nibble
1249 switch (receivedCmd[0]) {
7838f4be 1250 case 0x02:
1251 case 0x03: { // IBlock (command no CID)
1252 dynamic_response_info.response[0] = receivedCmd[0];
1253 dynamic_response_info.response[1] = 0x90;
1254 dynamic_response_info.response[2] = 0x00;
1255 dynamic_response_info.response_n = 3;
1256 } break;
7bc95e2e 1257 case 0x0B:
7838f4be 1258 case 0x0A: { // IBlock (command CID)
7bc95e2e 1259 dynamic_response_info.response[0] = receivedCmd[0];
1260 dynamic_response_info.response[1] = 0x00;
1261 dynamic_response_info.response[2] = 0x90;
1262 dynamic_response_info.response[3] = 0x00;
1263 dynamic_response_info.response_n = 4;
1264 } break;
1265
1266 case 0x1A:
1267 case 0x1B: { // Chaining command
1268 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1269 dynamic_response_info.response_n = 2;
1270 } break;
1271
7e735c13 1272 case 0xAA:
1273 case 0xBB: {
7bc95e2e 1274 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1275 dynamic_response_info.response_n = 2;
1276 } break;
1277
7838f4be 1278 case 0xBA: { // ping / pong
1279 dynamic_response_info.response[0] = 0xAB;
1280 dynamic_response_info.response[1] = 0x00;
1281 dynamic_response_info.response_n = 2;
7bc95e2e 1282 } break;
1283
1284 case 0xCA:
1285 case 0xC2: { // Readers sends deselect command
7838f4be 1286 dynamic_response_info.response[0] = 0xCA;
1287 dynamic_response_info.response[1] = 0x00;
1288 dynamic_response_info.response_n = 2;
7bc95e2e 1289 } break;
1290
1291 default: {
1292 // Never seen this command before
810f5379 1293 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1294 Dbprintf("Received unknown command (len=%d):",len);
1295 Dbhexdump(len,receivedCmd,false);
1296 // Do not respond
1297 dynamic_response_info.response_n = 0;
1298 } break;
1299 }
ce02f6f9 1300
7bc95e2e 1301 if (dynamic_response_info.response_n > 0) {
1302 // Copy the CID from the reader query
1303 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1304
7bc95e2e 1305 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
7e735c13 1306 AppendCrc14443a(dynamic_response_info.response, dynamic_response_info.response_n);
7bc95e2e 1307 dynamic_response_info.response_n += 2;
ce02f6f9 1308
7bc95e2e 1309 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
84bdbc19 1310 DbpString("Error preparing tag response");
810f5379 1311 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1312 break;
1313 }
1314 p_response = &dynamic_response_info;
1315 }
81cd0474 1316 }
15c4dc5a 1317
1318 // Count number of wakeups received after a halt
1319 if(order == 6 && lastorder == 5) { happened++; }
1320
1321 // Count number of other messages after a halt
1322 if(order != 6 && lastorder == 5) { happened2++; }
1323
bc939371 1324 // comment this limit if you want to simulation longer
1325 if (!tracing) {
7e735c13 1326 DbpString("Trace Full. Simulation stopped.");
bc939371 1327 break;
1328 }
91c7a7cc 1329 // comment this limit if you want to simulation longer
15c4dc5a 1330 if(cmdsRecvd > 999) {
1331 DbpString("1000 commands later...");
254b70a4 1332 break;
15c4dc5a 1333 }
ce02f6f9 1334 cmdsRecvd++;
1335
1336 if (p_response != NULL) {
7bc95e2e 1337 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1338 // do the tracing for the previous reader request and this tag answer:
810f5379 1339 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1340 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1341
7bc95e2e 1342 EmLogTrace(Uart.output,
1343 Uart.len,
1344 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1345 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1346 Uart.parity,
7bc95e2e 1347 p_response->response,
1348 p_response->response_n,
1349 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1350 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1351 par);
7bc95e2e 1352 }
7bc95e2e 1353 }
15c4dc5a 1354
d26849d4 1355 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 1356 set_tracing(FALSE);
f71f4deb 1357 BigBuf_free_keep_EM();
c9216a92 1358 LED_A_OFF();
7e735c13 1359
1360 /*
bf5d7992 1361 if(flags & FLAG_NR_AR_ATTACK && MF_DBGLEVEL >= 1) {
7e735c13 1362
6b23be6b 1363 for ( uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
1364 if (ar_nr_collected[i] == 2) {
1365 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
1366 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
1367 ar_nr_resp[i].cuid, //UID
1368 ar_nr_resp[i].nonce, //NT
1369 ar_nr_resp[i].nr, //NR1
1370 ar_nr_resp[i].ar, //AR1
1371 ar_nr_resp[i].nr2, //NR2
1372 ar_nr_resp[i].ar2 //AR2
1373 );
1374 }
1375 }
7e735c13 1376
6b23be6b 1377 for ( uint8_t i = ATTACK_KEY_COUNT; i < ATTACK_KEY_COUNT*2; i++) {
1378 if (ar_nr_collected[i] == 2) {
1379 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
1380 Dbprintf("../tools/mfkey/mfkey32v2 %08x %08x %08x %08x %08x %08x %08x",
1381 ar_nr_resp[i].cuid, //UID
1382 ar_nr_resp[i].nonce, //NT
1383 ar_nr_resp[i].nr, //NR1
1384 ar_nr_resp[i].ar, //AR1
1385 ar_nr_resp[i].nonce2,//NT2
1386 ar_nr_resp[i].nr2, //NR2
1387 ar_nr_resp[i].ar2 //AR2
1388 );
1389 }
1390 }
1391 }
7e735c13 1392 */
1393
0de8e387 1394 if (MF_DBGLEVEL >= 4){
84bdbc19 1395 Dbprintf("-[ Wake ups after halt [%d]", happened);
1396 Dbprintf("-[ Messages after halt [%d]", happened2);
1397 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
1398 Dbprintf("-[ Num of moebius tries [%d]", moebius_count);
0de8e387 1399 }
e99acd00 1400
1401 cmd_send(CMD_ACK,1,0,0,0,0);
15c4dc5a 1402}
1403
9492e0b0 1404// prepare a delayed transfer. This simply shifts ToSend[] by a number
1405// of bits specified in the delay parameter.
0194ce8f 1406void PrepareDelayedTransfer(uint16_t delay) {
7504dc50 1407 delay &= 0x07;
1408 if (!delay) return;
1409
9492e0b0 1410 uint8_t bitmask = 0;
1411 uint8_t bits_to_shift = 0;
1412 uint8_t bits_shifted = 0;
7504dc50 1413 uint16_t i = 0;
1414
1415 for (i = 0; i < delay; ++i)
1416 bitmask |= (0x01 << i);
2285d9dd 1417
6fc68747 1418 ToSend[++ToSendMax] = 0x00;
7504dc50 1419
1420 for (i = 0; i < ToSendMax; ++i) {
9492e0b0 1421 bits_to_shift = ToSend[i] & bitmask;
1422 ToSend[i] = ToSend[i] >> delay;
1423 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1424 bits_shifted = bits_to_shift;
1425 }
1426 }
9492e0b0 1427
7bc95e2e 1428
1429//-------------------------------------------------------------------------------------
15c4dc5a 1430// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1431// Parameter timing:
7bc95e2e 1432// if NULL: transfer at next possible time, taking into account
1433// request guard time and frame delay time
1434// if == 0: transfer immediately and return time of transfer
9492e0b0 1435// if != 0: delay transfer until time specified
7bc95e2e 1436//-------------------------------------------------------------------------------------
0194ce8f 1437static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing) {
9492e0b0 1438 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1439
7bc95e2e 1440 uint32_t ThisTransferTime = 0;
e30c654b 1441
9492e0b0 1442 if (timing) {
ca5bad3d 1443 if(*timing == 0) { // Measure time
7bc95e2e 1444 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
ca5bad3d 1445 } else {
1446 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1447 }
1448 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1449 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
7bc95e2e 1450 LastTimeProxToAirStart = *timing;
1451 } else {
1452 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
7504dc50 1453
7bc95e2e 1454 while(GetCountSspClk() < ThisTransferTime);
7504dc50 1455
7bc95e2e 1456 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1457 }
1458
7bc95e2e 1459 // clear TXRDY
1460 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1461
7bc95e2e 1462 uint16_t c = 0;
9492e0b0 1463 for(;;) {
1464 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1465 AT91C_BASE_SSC->SSC_THR = cmd[c];
4c0cf2d2 1466 ++c;
5ebcb867 1467 if(c >= len)
9492e0b0 1468 break;
9492e0b0 1469 }
1470 }
7bc95e2e 1471
1472 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1473}
1474
15c4dc5a 1475//-----------------------------------------------------------------------------
195af472 1476// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1477//-----------------------------------------------------------------------------
6b23be6b 1478void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity) {
7bc95e2e 1479 int i, j;
5ebcb867 1480 int last = 0;
7bc95e2e 1481 uint8_t b;
e30c654b 1482
7bc95e2e 1483 ToSendReset();
e30c654b 1484
7bc95e2e 1485 // Start of Communication (Seq. Z)
1486 ToSend[++ToSendMax] = SEC_Z;
1487 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
7bc95e2e 1488
1489 size_t bytecount = nbytes(bits);
1490 // Generate send structure for the data bits
1491 for (i = 0; i < bytecount; i++) {
1492 // Get the current byte to send
1493 b = cmd[i];
1494 size_t bitsleft = MIN((bits-(i*8)),8);
1495
1496 for (j = 0; j < bitsleft; j++) {
1497 if (b & 1) {
1498 // Sequence X
1499 ToSend[++ToSendMax] = SEC_X;
1500 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1501 last = 1;
1502 } else {
1503 if (last == 0) {
1504 // Sequence Z
1505 ToSend[++ToSendMax] = SEC_Z;
1506 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1507 } else {
1508 // Sequence Y
1509 ToSend[++ToSendMax] = SEC_Y;
1510 last = 0;
1511 }
1512 }
1513 b >>= 1;
1514 }
1515
6a1f2d82 1516 // Only transmit parity bit if we transmitted a complete byte
0ec548dc 1517 if (j == 8 && parity != NULL) {
7bc95e2e 1518 // Get the parity bit
6a1f2d82 1519 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1520 // Sequence X
1521 ToSend[++ToSendMax] = SEC_X;
1522 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1523 last = 1;
1524 } else {
1525 if (last == 0) {
1526 // Sequence Z
1527 ToSend[++ToSendMax] = SEC_Z;
1528 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1529 } else {
1530 // Sequence Y
1531 ToSend[++ToSendMax] = SEC_Y;
1532 last = 0;
1533 }
1534 }
1535 }
1536 }
e30c654b 1537
7bc95e2e 1538 // End of Communication: Logic 0 followed by Sequence Y
1539 if (last == 0) {
1540 // Sequence Z
1541 ToSend[++ToSendMax] = SEC_Z;
1542 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1543 } else {
1544 // Sequence Y
1545 ToSend[++ToSendMax] = SEC_Y;
1546 last = 0;
1547 }
1548 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1549
7bc95e2e 1550 // Convert to length of command:
4b78d6b3 1551 ++ToSendMax;
15c4dc5a 1552}
1553
195af472 1554//-----------------------------------------------------------------------------
1555// Prepare reader command to send to FPGA
1556//-----------------------------------------------------------------------------
0194ce8f 1557void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity) {
ca5bad3d 1558 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1559}
1560
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1561//-----------------------------------------------------------------------------
1562// Wait for commands from reader
1563// Stop when button is pressed (return 1) or field was gone (return 2)
1564// Or return 0 when command is captured
1565//-----------------------------------------------------------------------------
0194ce8f 1566static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity) {
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1567 *len = 0;
1568
1569 uint32_t timer = 0, vtime = 0;
1570 int analogCnt = 0;
1571 int analogAVG = 0;
1572
1573 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1574 // only, since we are receiving, not transmitting).
1575 // Signal field is off with the appropriate LED
1576 LED_D_OFF();
1577 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1578
1579 // Set ADC to read field strength
1580 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1581 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1582 ADC_MODE_PRESCALE(63) |
1583 ADC_MODE_STARTUP_TIME(1) |
1584 ADC_MODE_SAMPLE_HOLD_TIME(15);
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1585 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1586 // start ADC
1587 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1588
1589 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1590 UartInit(received, parity);
7bc95e2e 1591
1592 // Clear RXRDY:
1593 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1594
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1595 for(;;) {
1596 WDT_HIT();
1597
1598 if (BUTTON_PRESS()) return 1;
1599
1600 // test if the field exists
1601 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1602 analogCnt++;
1603 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1604 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1605 if (analogCnt >= 32) {
0c8d25eb 1606 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
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1607 vtime = GetTickCount();
1608 if (!timer) timer = vtime;
1609 // 50ms no field --> card to idle state
1610 if (vtime - timer > 50) return 2;
1611 } else
1612 if (timer) timer = 0;
1613 analogCnt = 0;
1614 analogAVG = 0;
1615 }
1616 }
7bc95e2e 1617
9ca155ba 1618 // receive and test the miller decoding
7bc95e2e 1619 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1620 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1621 if(MillerDecoding(b, 0)) {
1622 *len = Uart.len;
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1623 return 0;
1624 }
7bc95e2e 1625 }
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1626 }
1627}
1628
0194ce8f 1629int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded) {
7bc95e2e 1630 uint8_t b;
1631 uint16_t i = 0;
1632 uint32_t ThisTransferTime;
1633
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1634 // Modulate Manchester
1635 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1636
1637 // include correction bit if necessary
1638 if (Uart.parityBits & 0x01) {
1639 correctionNeeded = TRUE;
1640 }
0194ce8f 1641 // 1236, so correction bit needed
1642 i = (correctionNeeded) ? 0 : 1;
7bc95e2e 1643
d714d3ef 1644 // clear receiving shift register and holding register
7bc95e2e 1645 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1646 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1647 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1648 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1649
7bc95e2e 1650 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
b070f4e4 1651 for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
7bc95e2e 1652 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1653 if (AT91C_BASE_SSC->SSC_RHR) break;
1654 }
1655
1656 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1657
1658 // Clear TXRDY:
1659 AT91C_BASE_SSC->SSC_THR = SEC_F;
1660
9ca155ba 1661 // send cycle
bb42a03e 1662 for(; i < respLen; ) {
9ca155ba 1663 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1664 AT91C_BASE_SSC->SSC_THR = resp[i++];
1665 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1666 }
7bc95e2e 1667
17ad0e09 1668 if(BUTTON_PRESS()) break;
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1669 }
1670
7bc95e2e 1671 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
4b78d6b3 1672 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3; // twich /8 ?? >>3,
0c8d25eb 1673 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
7bc95e2e 1674 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1675 AT91C_BASE_SSC->SSC_THR = SEC_F;
1676 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1677 i++;
1678 }
1679 }
7bc95e2e 1680 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
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1681 return 0;
1682}
1683
7bc95e2e 1684int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1685 Code4bitAnswerAsTag(resp);
0a39986e 1686 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1687 // do the tracing for the previous reader request and this tag answer:
5ebcb867 1688 uint8_t par[1] = {0x00};
6a1f2d82 1689 GetParity(&resp, 1, par);
7bc95e2e 1690 EmLogTrace(Uart.output,
1691 Uart.len,
1692 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1693 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1694 Uart.parity,
7bc95e2e 1695 &resp,
1696 1,
1697 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1698 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1699 par);
0a39986e 1700 return res;
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1701}
1702
8f51ddb0 1703int EmSend4bit(uint8_t resp){
7bc95e2e 1704 return EmSend4bitEx(resp, false);
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M
1705}
1706
6a1f2d82 1707int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1708 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1709 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1710 // do the tracing for the previous reader request and this tag answer:
1711 EmLogTrace(Uart.output,
1712 Uart.len,
1713 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1714 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1715 Uart.parity,
7bc95e2e 1716 resp,
1717 respLen,
1718 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1719 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1720 par);
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1721 return res;
1722}
1723
6a1f2d82 1724int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
5ebcb867 1725 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1726 GetParity(resp, respLen, par);
1727 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
8f51ddb0
M
1728}
1729
6a1f2d82 1730int EmSendCmd(uint8_t *resp, uint16_t respLen){
5ebcb867 1731 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1732 GetParity(resp, respLen, par);
1733 return EmSendCmdExPar(resp, respLen, false, par);
8f51ddb0
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1734}
1735
6a1f2d82 1736int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1737 return EmSendCmdExPar(resp, respLen, false, par);
1738}
1739
6a1f2d82 1740bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1741 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1742{
810f5379 1743 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1744 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1745 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1746 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1747 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1748 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1749 reader_EndTime = tag_StartTime - exact_fdt;
1750 reader_StartTime = reader_EndTime - reader_modlen;
5ebcb867 1751
810f5379 1752 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE))
1753 return FALSE;
1754 else
1755 return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1756
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1757}
1758
15c4dc5a 1759//-----------------------------------------------------------------------------
1760// Wait a certain time for tag response
1761// If a response is captured return TRUE
e691fc45 1762// If it takes too long return FALSE
15c4dc5a 1763//-----------------------------------------------------------------------------
0194ce8f 1764static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset) {
46c65fed 1765 uint32_t c = 0x00;
e691fc45 1766
15c4dc5a 1767 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1768 // only, since we are receiving, not transmitting).
1769 // Signal field is on with the appropriate LED
1770 LED_D_ON();
1771 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1772
534983d7 1773 // Now get the answer from the card
6a1f2d82 1774 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1775
7bc95e2e 1776 // clear RXRDY:
1777 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1778
15c4dc5a 1779 for(;;) {
534983d7 1780 WDT_HIT();
15c4dc5a 1781
534983d7 1782 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1783 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1784 if(ManchesterDecoding(b, offset, 0)) {
1785 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1786 return TRUE;
19a700a8 1787 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
7bc95e2e 1788 return FALSE;
15c4dc5a 1789 }
534983d7 1790 }
1791 }
15c4dc5a 1792}
1793
0194ce8f 1794void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing) {
72e6d462 1795
6a1f2d82 1796 CodeIso14443aBitsAsReaderPar(frame, bits, par);
7bc95e2e 1797 // Send command to tag
1798 TransmitFor14443a(ToSend, ToSendMax, timing);
0194ce8f 1799 if(trigger) LED_A_ON();
dfc3c505 1800
4b78d6b3 1801 LogTrace(frame, nbytes(bits), (LastTimeProxToAirStart<<4) + DELAY_ARM2AIR_AS_READER, ((LastTimeProxToAirStart + LastProxToAirDuration)<<4) + DELAY_ARM2AIR_AS_READER, par, TRUE);
15c4dc5a 1802}
1803
0194ce8f 1804void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing) {
ca5bad3d 1805 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1806}
15c4dc5a 1807
0194ce8f 1808void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing) {
72e6d462 1809 // Generate parity and redirect
1810 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1811 GetParity(frame, len/8, par);
1812 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1813}
1814
0194ce8f 1815void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing) {
72e6d462 1816 // Generate parity and redirect
1817 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1818 GetParity(frame, len, par);
1819 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1820}
1821
0194ce8f 1822int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity) {
1823 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset))
1824 return FALSE;
1825 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
e691fc45 1826 return Demod.len;
1827}
1828
91c7a7cc 1829int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity) {
0194ce8f 1830 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0))
1831 return FALSE;
91c7a7cc 1832 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
e691fc45 1833 return Demod.len;
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1834}
1835
c188b1b9 1836// performs iso14443a anticollision (optional) and card select procedure
1837// fills the uid and cuid pointer unless NULL
1838// fills the card info record unless NULL
1839// if anticollision is false, then the UID must be provided in uid_ptr[]
1840// and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1841int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades) {
f8850434 1842 uint8_t wupa[] = { ISO14443A_CMD_WUPA }; // 0x26 - ISO14443A_CMD_REQA 0x52 - ISO14443A_CMD_WUPA
1843 uint8_t sel_all[] = { ISO14443A_CMD_ANTICOLL_OR_SELECT,0x20 };
1844 uint8_t sel_uid[] = { ISO14443A_CMD_ANTICOLL_OR_SELECT,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1845 uint8_t rats[] = { ISO14443A_CMD_RATS,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
4c0cf2d2 1846 uint8_t resp[MAX_FRAME_SIZE] = {0}; // theoretically. A usual RATS will be much smaller
1847 uint8_t resp_par[MAX_PARITY_SIZE] = {0};
1848 byte_t uid_resp[4] = {0};
1849 size_t uid_resp_len = 0;
6a1f2d82 1850
1851 uint8_t sak = 0x04; // cascade uid
1852 int cascade_level = 0;
1853 int len;
1854
1855 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
c188b1b9 1856 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
7bc95e2e 1857
6a1f2d82 1858 // Receive the ATQA
1859 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1860
1861 if(p_hi14a_card) {
1862 memcpy(p_hi14a_card->atqa, resp, 2);
1863 p_hi14a_card->uidlen = 0;
1864 memset(p_hi14a_card->uid,0,10);
1865 }
5f6d6c90 1866
c188b1b9 1867 if (anticollision) {
4c0cf2d2 1868 // clear uid
1869 if (uid_ptr)
1870 memset(uid_ptr,0,10);
c188b1b9 1871 }
79a73ab2 1872
5fba8581 1873 // reset the PCB block number
1874 iso14_pcb_blocknum = 0;
1875
0ec548dc 1876 // check for proprietary anticollision:
4c0cf2d2 1877 if ((resp[0] & 0x1F) == 0) return 3;
0ec548dc 1878
6a1f2d82 1879 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1880 // which case we need to make a cascade 2 request and select - this is a long UID
1881 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1882 for(; sak & 0x04; cascade_level++) {
1883 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1884 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1885
c188b1b9 1886 if (anticollision) {
6a1f2d82 1887 // SELECT_ALL
4c0cf2d2 1888 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1889 if (!ReaderReceive(resp, resp_par)) return 0;
1890
1891 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1892 memset(uid_resp, 0, 4);
1893 uint16_t uid_resp_bits = 0;
1894 uint16_t collision_answer_offset = 0;
1895 // anti-collision-loop:
1896 while (Demod.collisionPos) {
1897 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1898 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1899 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1900 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1901 }
1902 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1903 uid_resp_bits++;
1904 // construct anticollosion command:
1905 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1906 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1907 sel_uid[2+i] = uid_resp[i];
1908 }
1909 collision_answer_offset = uid_resp_bits%8;
1910 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1911 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
6a1f2d82 1912 }
4c0cf2d2 1913 // finally, add the last bits and BCC of the UID
1914 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1915 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1916 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1917 }
e691fc45 1918
4c0cf2d2 1919 } else { // no collision, use the response to SELECT_ALL as current uid
1920 memcpy(uid_resp, resp, 4);
1921 }
1922
c188b1b9 1923 } else {
1924 if (cascade_level < num_cascades - 1) {
1925 uid_resp[0] = 0x88;
1926 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1927 } else {
1928 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1929 }
1930 }
6a1f2d82 1931 uid_resp_len = 4;
5f6d6c90 1932
6a1f2d82 1933 // calculate crypto UID. Always use last 4 Bytes.
4c0cf2d2 1934 if(cuid_ptr)
6a1f2d82 1935 *cuid_ptr = bytes_to_num(uid_resp, 4);
e30c654b 1936
6a1f2d82 1937 // Construct SELECT UID command
1938 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
c188b1b9 1939 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
6a1f2d82 1940 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1941 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1942 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1943
1944 // Receive the SAK
1945 if (!ReaderReceive(resp, resp_par)) return 0;
4c0cf2d2 1946
6a1f2d82 1947 sak = resp[0];
1948
810f5379 1949 // Test if more parts of the uid are coming
6a1f2d82 1950 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1951 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1952 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1953 uid_resp[0] = uid_resp[1];
1954 uid_resp[1] = uid_resp[2];
1955 uid_resp[2] = uid_resp[3];
6a1f2d82 1956 uid_resp_len = 3;
1957 }
5f6d6c90 1958
4c0cf2d2 1959 if(uid_ptr && anticollision)
6a1f2d82 1960 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
5f6d6c90 1961
6a1f2d82 1962 if(p_hi14a_card) {
1963 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1964 p_hi14a_card->uidlen += uid_resp_len;
1965 }
1966 }
79a73ab2 1967
6a1f2d82 1968 if(p_hi14a_card) {
1969 p_hi14a_card->sak = sak;
1970 p_hi14a_card->ats_len = 0;
1971 }
534983d7 1972
3fe4ff4f 1973 // non iso14443a compliant tag
1974 if( (sak & 0x20) == 0) return 2;
534983d7 1975
6a1f2d82 1976 // Request for answer to select
1977 AppendCrc14443a(rats, 2);
1978 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1979
6a1f2d82 1980 if (!(len = ReaderReceive(resp, resp_par))) return 0;
3fe4ff4f 1981
6a1f2d82 1982 if(p_hi14a_card) {
1983 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1984 p_hi14a_card->ats_len = len;
1985 }
5f6d6c90 1986
19a700a8 1987 // set default timeout based on ATS
1988 iso14a_set_ATS_timeout(resp);
6a1f2d82 1989 return 1;
7e758047 1990}
15c4dc5a 1991
7bc95e2e 1992void iso14443a_setup(uint8_t fpga_minor_mode) {
be818b14 1993
7cc204bf 1994 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1995 // Set up the synchronous serial port
1996 FpgaSetupSsc();
7bc95e2e 1997 // connect Demodulated Signal to ADC:
7e758047 1998 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
91c7a7cc 1999
ca5bad3d 2000 LED_D_OFF();
7e758047 2001 // Signal field is on with the appropriate LED
ca5bad3d 2002 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD ||
2003 fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN)
7bc95e2e 2004 LED_D_ON();
6fc68747 2005
be818b14 2006 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
d5bded10 2007
2008 SpinDelay(20);
6fc68747 2009
2010 // Start the timer
2011 StartCountSspClk();
be818b14 2012
2013 // Prepare the demodulation functions
2014 DemodReset();
2015 UartReset();
2016 NextTransferTime = 2 * DELAY_ARM2AIR_AS_READER;
d5bded10 2017 iso14a_set_timeout(10*106); // 20ms default
7e758047 2018}
15c4dc5a 2019
6a1f2d82 2020int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
810f5379 2021 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
534983d7 2022 uint8_t real_cmd[cmd_len+4];
2023 real_cmd[0] = 0x0a; //I-Block
b0127e65 2024 // put block number into the PCB
2025 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 2026 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
2027 memcpy(real_cmd+2, cmd, cmd_len);
2028 AppendCrc14443a(real_cmd,cmd_len+2);
2029
9492e0b0 2030 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 2031 size_t len = ReaderReceive(data, parity);
ca5bad3d 2032 //DATA LINK ERROR
2033 if (!len) return 0;
2034
6a1f2d82 2035 uint8_t *data_bytes = (uint8_t *) data;
ca5bad3d 2036
b0127e65 2037 // if we received an I- or R(ACK)-Block with a block number equal to the
2038 // current block number, toggle the current block number
ca5bad3d 2039 if (len >= 4 // PCB+CID+CRC = 4 bytes
b0127e65 2040 && ((data_bytes[0] & 0xC0) == 0 // I-Block
2041 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2042 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
2043 {
2044 iso14_pcb_blocknum ^= 1;
2045 }
2046
534983d7 2047 return len;
2048}
2049
be818b14 2050
7e758047 2051//-----------------------------------------------------------------------------
2052// Read an ISO 14443a tag. Send out commands and store answers.
7e758047 2053//-----------------------------------------------------------------------------
91c7a7cc 2054void ReaderIso14443a(UsbCommand *c) {
534983d7 2055 iso14a_command_t param = c->arg[0];
04bc1c66 2056 size_t len = c->arg[1] & 0xffff;
2057 size_t lenbits = c->arg[1] >> 16;
2058 uint32_t timeout = c->arg[2];
91c7a7cc 2059 uint8_t *cmd = c->d.asBytes;
9492e0b0 2060 uint32_t arg0 = 0;
810f5379 2061 byte_t buf[USB_CMD_DATA_SIZE] = {0x00};
2062 uint8_t par[MAX_PARITY_SIZE] = {0x00};
902cb3c0 2063
810f5379 2064 if (param & ISO14A_CONNECT)
3000dc4e 2065 clear_trace();
e691fc45 2066
3000dc4e 2067 set_tracing(TRUE);
e30c654b 2068
810f5379 2069 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 2070 iso14a_set_trigger(TRUE);
15c4dc5a 2071
810f5379 2072 if (param & ISO14A_CONNECT) {
7bc95e2e 2073 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 2074 if(!(param & ISO14A_NO_SELECT)) {
2075 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
c188b1b9 2076 arg0 = iso14443a_select_card(NULL,card,NULL, true, 0);
91c7a7cc 2077 cmd_send(CMD_ACK, arg0, card->uidlen, 0, buf, sizeof(iso14a_card_select_t));
6fc68747 2078 // if it fails, the cmdhf14a.c client quites.. however this one still executes.
2079 if ( arg0 == 0 ) return;
5f6d6c90 2080 }
534983d7 2081 }
e30c654b 2082
810f5379 2083 if (param & ISO14A_SET_TIMEOUT)
04bc1c66 2084 iso14a_set_timeout(timeout);
e30c654b 2085
810f5379 2086 if (param & ISO14A_APDU) {
902cb3c0 2087 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 2088 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2089 }
e30c654b 2090
810f5379 2091 if (param & ISO14A_RAW) {
0f7279b2 2092 if (param & ISO14A_APPEND_CRC) {
2093 if (param & ISO14A_TOPAZMODE)
0ec548dc 2094 AppendCrc14443b(cmd,len);
0f7279b2 2095 else
d26849d4 2096 AppendCrc14443a(cmd,len);
0f7279b2 2097
534983d7 2098 len += 2;
c7324bef 2099 if (lenbits) lenbits += 16;
15c4dc5a 2100 }
0f7279b2 2101 if (lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2102 if (param & ISO14A_TOPAZMODE) {
0ec548dc 2103 int bits_to_send = lenbits;
2104 uint16_t i = 0;
2105 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2106 bits_to_send -= 7;
2107 while (bits_to_send > 0) {
2108 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2109 bits_to_send -= 8;
2110 }
2111 } else {
6a1f2d82 2112 GetParity(cmd, lenbits/8, par);
0ec548dc 2113 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2114 }
2115 } else { // want to send complete bytes only
0f7279b2 2116 if (param & ISO14A_TOPAZMODE) {
0ec548dc 2117 uint16_t i = 0;
2118 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2119 while (i < len) {
2120 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2121 }
5f6d6c90 2122 } else {
0ec548dc 2123 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2124 }
5f6d6c90 2125 }
6a1f2d82 2126 arg0 = ReaderReceive(buf, par);
9492e0b0 2127 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2128 }
15c4dc5a 2129
810f5379 2130 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 2131 iso14a_set_trigger(FALSE);
15c4dc5a 2132
810f5379 2133 if (param & ISO14A_NO_DISCONNECT)
534983d7 2134 return;
15c4dc5a 2135
15c4dc5a 2136 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 2137 set_tracing(FALSE);
15c4dc5a 2138 LEDsoff();
15c4dc5a 2139}
b0127e65 2140
1c611bbd 2141// Determine the distance between two nonces.
2142// Assume that the difference is small, but we don't know which is first.
2143// Therefore try in alternating directions.
2144int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2145
ca5bad3d 2146 if (nt1 == nt2) return 0;
ca5bad3d 2147
91c7a7cc 2148 uint32_t nttmp1 = nt1;
2149 uint32_t nttmp2 = nt2;
2150
30daf914 2151 // 0xFFFF -- Half up and half down to find distance between nonces
2152 for (uint16_t i = 1; i < 32768/8; i += 8) {
bc939371 2153 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i;
be818b14 2154 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+1;
be818b14 2155 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+2;
be818b14 2156 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+3;
be818b14 2157 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+4;
be818b14 2158 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+5;
be818b14 2159 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+6;
be818b14 2160 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+7;
30daf914 2161
2162 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -i;
2163 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+1);
2164 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+2);
2165 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+3);
2166 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+4);
2167 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+5);
2168 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+6);
be818b14 2169 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+7);
2170 }
91c7a7cc 2171 // either nt1 or nt2 are invalid nonces
2172 return(-99999);
e772353f 2173}
2174
1c611bbd 2175//-----------------------------------------------------------------------------
2176// Recover several bits of the cypher stream. This implements (first stages of)
2177// the algorithm described in "The Dark Side of Security by Obscurity and
2178// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2179// (article by Nicolas T. Courtois, 2009)
2180//-----------------------------------------------------------------------------
f38cfd66 2181
df007486 2182void ReaderMifare(bool first_try, uint8_t block, uint8_t keytype ) {
2183
2184 uint8_t mf_auth[] = { keytype, block, 0x00, 0x00 };
b0300679 2185 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2186 uint8_t uid[10] = {0,0,0,0,0,0,0,0,0,0};
2187 uint8_t par_list[8] = {0,0,0,0,0,0,0,0};
2188 uint8_t ks_list[8] = {0,0,0,0,0,0,0,0};
495d7f13 2189 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = {0x00};
2190 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b0300679 2191 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2192 byte_t nt_diff = 0;
6a1f2d82 2193 uint32_t nt = 0;
b0300679 2194 uint32_t previous_nt = 0;
b0300679 2195 uint32_t cuid = 0;
2196
91c7a7cc 2197 int32_t catch_up_cycles = 0;
2198 int32_t last_catch_up = 0;
2199 int32_t isOK = 0;
2200 int32_t nt_distance = 0;
b0300679 2201
4c0cf2d2 2202 uint16_t elapsed_prng_sequences = 1;
1c611bbd 2203 uint16_t consecutive_resyncs = 0;
0de8e387 2204 uint16_t unexpected_random = 0;
2205 uint16_t sync_tries = 0;
b0300679 2206
bc939371 2207 // static variables here, is re-used in the next call
b0300679 2208 static uint32_t nt_attacked = 0;
2209 static uint32_t sync_time = 0;
91c7a7cc 2210 static uint32_t sync_cycles = 0;
b0300679 2211 static uint8_t par_low = 0;
2212 static uint8_t mf_nr_ar3 = 0;
91c7a7cc 2213
b0300679 2214 #define PRNG_SEQUENCE_LENGTH (1 << 16)
2215 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2216 #define MAX_SYNC_TRIES 32
df007486 2217
2218 AppendCrc14443a(mf_auth, 2);
2219
91c7a7cc 2220 BigBuf_free(); BigBuf_Clear_ext(false);
4b78d6b3 2221 clear_trace();
5fba8581 2222 set_tracing(FALSE);
91c7a7cc 2223 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
4c0cf2d2 2224
6067df30 2225 sync_time = GetCountSspClk() & 0xfffffff8;
ed8c2aeb 2226 sync_cycles = PRNG_SEQUENCE_LENGTH; // Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
f38cfd66 2227 nt_attacked = 0;
2228
dd83c457 2229 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare::Sync %u", sync_time);
f38cfd66 2230
6067df30 2231 if (first_try) {
f38cfd66 2232 mf_nr_ar3 = 0;
91c7a7cc 2233 par_low = 0;
4c0cf2d2 2234 } else {
b0300679 2235 // we were unsuccessful on a previous call.
2236 // Try another READER nonce (first 3 parity bits remain the same)
2237 ++mf_nr_ar3;
4c0cf2d2 2238 mf_nr_ar[3] = mf_nr_ar3;
2239 par[0] = par_low;
2240 }
91c7a7cc 2241
2242 bool have_uid = FALSE;
2243 uint8_t cascade_levels = 0;
2244
4c0cf2d2 2245 LED_C_ON();
91c7a7cc 2246 uint16_t i;
2247 for(i = 0; TRUE; ++i) {
4c0cf2d2 2248
1c611bbd 2249 WDT_HIT();
e30c654b 2250
1c611bbd 2251 // Test if the action was cancelled
c830303d 2252 if(BUTTON_PRESS()) {
2253 isOK = -1;
1c611bbd 2254 break;
2255 }
2256
91c7a7cc 2257 // this part is from Piwi's faster nonce collecting part in Hardnested.
2258 if (!have_uid) { // need a full select cycle to get the uid first
2259 iso14a_card_select_t card_info;
2260 if(!iso14443a_select_card(uid, &card_info, &cuid, true, 0)) {
2261 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (ALL)");
2262 break;
2263 }
2264 switch (card_info.uidlen) {
2265 case 4 : cascade_levels = 1; break;
2266 case 7 : cascade_levels = 2; break;
2267 case 10: cascade_levels = 3; break;
2268 default: break;
2269 }
2270 have_uid = TRUE;
2271 } else { // no need for anticollision. We can directly select the card
2272 if(!iso14443a_select_card(uid, NULL, &cuid, false, cascade_levels)) {
2273 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (UID)");
2274 continue;
2275 }
1c611bbd 2276 }
4c0cf2d2 2277
91c7a7cc 2278 // Sending timeslot of ISO14443a frame
2279 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles + catch_up_cycles;
4b78d6b3 2280 catch_up_cycles = 0;
2281
2282 // if we missed the sync time already, advance to the next nonce repeat
91c7a7cc 2283 while( GetCountSspClk() > sync_time) {
4b78d6b3 2284 ++elapsed_prng_sequences;
91c7a7cc 2285 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles;
2286 }
2287
2288 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2289 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2290
91c7a7cc 2291 // Receive the (4 Byte) "random" nonce from TAG
4c0cf2d2 2292 if (!ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2293 continue;
1c611bbd 2294
4b78d6b3 2295 previous_nt = nt;
2296 nt = bytes_to_num(receivedAnswer, 4);
2297
91c7a7cc 2298 // Transmit reader nonce with fake par
2299 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2300
6067df30 2301 // we didn't calibrate our clock yet,
2302 // iceman: has to be calibrated every time.
bcacb316 2303 if (previous_nt && !nt_attacked) {
91c7a7cc 2304
2305 nt_distance = dist_nt(previous_nt, nt);
2306
2307 // if no distance between, then we are in sync.
1c611bbd 2308 if (nt_distance == 0) {
2309 nt_attacked = nt;
0de8e387 2310 } else {
c830303d 2311 if (nt_distance == -99999) { // invalid nonce received
91c7a7cc 2312 ++unexpected_random;
3bc7b13d 2313 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
c830303d 2314 isOK = -3; // Card has an unpredictable PRNG. Give up
2315 break;
91c7a7cc 2316 } else {
2317 if (sync_cycles <= 0) sync_cycles += PRNG_SEQUENCE_LENGTH;
2318 LED_B_OFF();
c830303d 2319 continue; // continue trying...
2320 }
1c611bbd 2321 }
4c0cf2d2 2322
0de8e387 2323 if (++sync_tries > MAX_SYNC_TRIES) {
91c7a7cc 2324 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2325 break;
0de8e387 2326 }
4c0cf2d2 2327
4b78d6b3 2328 sync_cycles = (sync_cycles - nt_distance)/elapsed_prng_sequences;
91c7a7cc 2329
4c0cf2d2 2330 if (sync_cycles <= 0)
0de8e387 2331 sync_cycles += PRNG_SEQUENCE_LENGTH;
4c0cf2d2 2332
91c7a7cc 2333 if (MF_DBGLEVEL >= 4)
3bc7b13d 2334 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
4c0cf2d2 2335
91c7a7cc 2336 LED_B_OFF();
1c611bbd 2337 continue;
2338 }
2339 }
91c7a7cc 2340 LED_B_OFF();
1c611bbd 2341
ed8c2aeb 2342 if ( (nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
4c0cf2d2 2343
91c7a7cc 2344 catch_up_cycles = ABS(dist_nt(nt_attacked, nt));
c830303d 2345 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
1c611bbd 2346 catch_up_cycles = 0;
2347 continue;
91c7a7cc 2348 }
4c0cf2d2 2349 // average?
3bc7b13d 2350 catch_up_cycles /= elapsed_prng_sequences;
4c0cf2d2 2351
1c611bbd 2352 if (catch_up_cycles == last_catch_up) {
4a71da5a 2353 ++consecutive_resyncs;
4c0cf2d2 2354 } else {
1c611bbd 2355 last_catch_up = catch_up_cycles;
2356 consecutive_resyncs = 0;
4b78d6b3 2357 }
4c0cf2d2 2358
1c611bbd 2359 if (consecutive_resyncs < 3) {
91c7a7cc 2360 if (MF_DBGLEVEL >= 4)
2361 Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, catch_up_cycles, consecutive_resyncs);
4c0cf2d2 2362 } else {
2363 sync_cycles += catch_up_cycles;
2364
91c7a7cc 2365 if (MF_DBGLEVEL >= 4)
2366 Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, catch_up_cycles, sync_cycles);
4c0cf2d2 2367
3bc7b13d 2368 last_catch_up = 0;
2369 catch_up_cycles = 0;
2370 consecutive_resyncs = 0;
1c611bbd 2371 }
2372 continue;
2373 }
2374
1c611bbd 2375 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
91c7a7cc 2376 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2377 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2378
495d7f13 2379 if (nt_diff == 0)
6a1f2d82 2380 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2381
6a1f2d82 2382 par_list[nt_diff] = SwapBits(par[0], 8);
91c7a7cc 2383 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; // xor with NACK value to get keystream
1c611bbd 2384
2385 // Test if the information is complete
2386 if (nt_diff == 0x07) {
2387 isOK = 1;
2388 break;
2389 }
2390
2391 nt_diff = (nt_diff + 1) & 0x07;
2392 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2393 par[0] = par_low;
4b78d6b3 2394
1c611bbd 2395 } else {
b0300679 2396 // No NACK.
495d7f13 2397 if (nt_diff == 0 && first_try) {
6a1f2d82 2398 par[0]++;
5ebcb867 2399 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
c830303d 2400 isOK = -2;
2401 break;
2402 }
1c611bbd 2403 } else {
b0300679 2404 // Why this?
6a1f2d82 2405 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2406 }
2407 }
4b78d6b3 2408
91c7a7cc 2409 // reset the resyncs since we got a complete transaction on right time.
4b78d6b3 2410 consecutive_resyncs = 0;
91c7a7cc 2411 } // end for loop
1c611bbd 2412
1c611bbd 2413 mf_nr_ar[3] &= 0x1F;
5ebcb867 2414
bc939371 2415 if (MF_DBGLEVEL >= 4) Dbprintf("Number of sent auth requestes: %u", i);
d26849d4 2416
b0300679 2417 uint8_t buf[28] = {0x00};
91c7a7cc 2418 memset(buf, 0x00, sizeof(buf));
b0300679 2419 num_to_bytes(cuid, 4, buf);
1c611bbd 2420 num_to_bytes(nt, 4, buf + 4);
2421 memcpy(buf + 8, par_list, 8);
2422 memcpy(buf + 16, ks_list, 8);
2423 memcpy(buf + 24, mf_nr_ar, 4);
2424
91c7a7cc 2425 cmd_send(CMD_ACK, isOK, 0, 0, buf, sizeof(buf) );
1c611bbd 2426
1c611bbd 2427 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2428 LEDsoff();
99cf19d9 2429 set_tracing(FALSE);
20f9a2a1 2430}
1c611bbd 2431
f38cfd66 2432
0de8e387 2433/**
d2f487af 2434 *MIFARE 1K simulate.
2435 *
2436 *@param flags :
0194ce8f 2437 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2438 * FLAG_4B_UID_IN_DATA - use 4-byte UID in the data-section
2439 * FLAG_7B_UID_IN_DATA - use 7-byte UID in the data-section
2440 * FLAG_10B_UID_IN_DATA - use 10-byte UID in the data-section
2441 * FLAG_UID_IN_EMUL - use 4-byte UID from emulator memory
2442 * FLAG_NR_AR_ATTACK - collect NR_AR responses for bruteforcing later
d2f487af 2443 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2444 */
91c7a7cc 2445void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain) {
e99acd00 2446
2447 // init pseudorand
2448 fast_prand( GetTickCount() );
2449
50193c1e 2450 int cardSTATE = MFEMUL_NOFIELD;
0194ce8f 2451 int _UID_LEN = 0; // 4, 7, 10
9ca155ba 2452 int vHf = 0; // in mV
0194ce8f 2453 int res = 0;
0a39986e
M
2454 uint32_t selTimer = 0;
2455 uint32_t authTimer = 0;
6a1f2d82 2456 uint16_t len = 0;
8f51ddb0 2457 uint8_t cardWRBL = 0;
9ca155ba
M
2458 uint8_t cardAUTHSC = 0;
2459 uint8_t cardAUTHKEY = 0xff; // no authentication
2460 uint32_t cuid = 0;
51969283 2461 uint32_t ans = 0;
0014cb46
M
2462 uint32_t cardINTREG = 0;
2463 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2464 struct Crypto1State mpcs = {0, 0};
2465 struct Crypto1State *pcs;
2466 pcs = &mpcs;
f38cfd66 2467 uint32_t numReads = 0; // Counts numer of times reader read a block
5ebcb867 2468 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2469 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2470 uint8_t response[MAX_MIFARE_FRAME_SIZE] = {0x00};
2471 uint8_t response_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
9ca155ba 2472
bc939371 2473 uint8_t atqa[] = {0x04, 0x00}; // Mifare classic 1k
2474 uint8_t sak_4[] = {0x0C, 0x00, 0x00}; // CL1 - 4b uid
2475 uint8_t sak_7[] = {0x0C, 0x00, 0x00}; // CL2 - 7b uid
2476 uint8_t sak_10[] = {0x0C, 0x00, 0x00}; // CL3 - 10b uid
f38cfd66 2477 // uint8_t sak[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
0194ce8f 2478
2479 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2480 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2481 uint8_t rUIDBCC3[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2482
bf5d7992 2483 // TAG Nonce - Authenticate response
2484 uint8_t rAUTH_NT[4];
2485 uint32_t nonce = prand();
2486 num_to_bytes(nonce, 4, rAUTH_NT);
2487
f38cfd66 2488 // uint8_t rAUTH_NT[] = {0x55, 0x41, 0x49, 0x92};// nonce from nested? why this?
d2f487af 2489 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
bf5d7992 2490
bc939371 2491 // Here, we collect CUID, NT, NR, AR, CUID2, NT2, NR2, AR2
d2f487af 2492 // This can be used in a reader-only attack.
84bdbc19 2493 nonces_t ar_nr_nonces[ATTACK_KEY_COUNT];
2494 memset(ar_nr_nonces, 0x00, sizeof(ar_nr_nonces));
0014cb46 2495
f38cfd66 2496 // -- Determine the UID
0194ce8f 2497 // Can be set from emulator memory or incoming data
2498 // Length: 4,7,or 10 bytes
bc939371 2499 if ( (flags & FLAG_UID_IN_EMUL) == FLAG_UID_IN_EMUL)
2500 emlGetMemBt(datain, 0, 10); // load 10bytes from EMUL to the datain pointer. to be used below.
2501
2502 if ( (flags & FLAG_4B_UID_IN_DATA) == FLAG_4B_UID_IN_DATA) {
0194ce8f 2503 memcpy(rUIDBCC1, datain, 4);
2504 _UID_LEN = 4;
bc939371 2505 } else if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA) {
0194ce8f 2506 memcpy(&rUIDBCC1[1], datain, 3);
2507 memcpy( rUIDBCC2, datain+3, 4);
2508 _UID_LEN = 7;
bc939371 2509 } else if ( (flags & FLAG_10B_UID_IN_DATA) == FLAG_10B_UID_IN_DATA) {
0194ce8f 2510 memcpy(&rUIDBCC1[1], datain, 3);
bc939371 2511 memcpy(&rUIDBCC2[1], datain+3, 3);
2512 memcpy( rUIDBCC3, datain+6, 4);
0194ce8f 2513 _UID_LEN = 10;
d2f487af 2514 }
7bc95e2e 2515
0194ce8f 2516 switch (_UID_LEN) {
2517 case 4:
bc939371 2518 sak_4[0] &= 0xFB;
0194ce8f 2519 // save CUID
b6e05350 2520 cuid = bytes_to_num(rUIDBCC1, 4);
0194ce8f 2521 // BCC
2522 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
bc939371 2523 if (MF_DBGLEVEL >= 2) {
0194ce8f 2524 Dbprintf("4B UID: %02x%02x%02x%02x",
2525 rUIDBCC1[0],
2526 rUIDBCC1[1],
2527 rUIDBCC1[2],
2528 rUIDBCC1[3]
2529 );
2530 }
2531 break;
2532 case 7:
2533 atqa[0] |= 0x40;
bc939371 2534 sak_7[0] &= 0xFB;
0194ce8f 2535 // save CUID
b6e05350 2536 cuid = bytes_to_num(rUIDBCC2, 4);
bc939371 2537 // CascadeTag, CT
2538 rUIDBCC1[0] = 0x88;
0194ce8f 2539 // BCC
2540 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2541 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
bc939371 2542 if (MF_DBGLEVEL >= 2) {
0194ce8f 2543 Dbprintf("7B UID: %02x %02x %02x %02x %02x %02x %02x",
0194ce8f 2544 rUIDBCC1[1],
2545 rUIDBCC1[2],
2546 rUIDBCC1[3],
2547 rUIDBCC2[0],
2548 rUIDBCC2[1],
2549 rUIDBCC2[2],
2550 rUIDBCC2[3]
2551 );
2552 }
2553 break;
2554 case 10:
bc939371 2555 atqa[0] |= 0x80;
2556 sak_10[0] &= 0xFB;
0194ce8f 2557 // save CUID
b6e05350 2558 cuid = bytes_to_num(rUIDBCC3, 4);
bc939371 2559 // CascadeTag, CT
2560 rUIDBCC1[0] = 0x88;
2561 rUIDBCC2[0] = 0x88;
0194ce8f 2562 // BCC
2563 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
0194ce8f 2564 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2565 rUIDBCC3[4] = rUIDBCC3[0] ^ rUIDBCC3[1] ^ rUIDBCC3[2] ^ rUIDBCC3[3];
bc939371 2566
2567 if (MF_DBGLEVEL >= 2) {
0194ce8f 2568 Dbprintf("10B UID: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
0194ce8f 2569 rUIDBCC1[1],
2570 rUIDBCC1[2],
2571 rUIDBCC1[3],
0194ce8f 2572 rUIDBCC2[1],
2573 rUIDBCC2[2],
2574 rUIDBCC2[3],
2575 rUIDBCC3[0],
2576 rUIDBCC3[1],
2577 rUIDBCC3[2],
2578 rUIDBCC3[3]
2579 );
2580 }
2581 break;
2582 default:
2583 break;
d2f487af 2584 }
bc939371 2585 // calc some crcs
2586 ComputeCrc14443(CRC_14443_A, sak_4, 1, &sak_4[1], &sak_4[2]);
2587 ComputeCrc14443(CRC_14443_A, sak_7, 1, &sak_7[1], &sak_7[2]);
2588 ComputeCrc14443(CRC_14443_A, sak_10, 1, &sak_10[1], &sak_10[2]);
2589
99cf19d9 2590 // We need to listen to the high-frequency, peak-detected path.
2591 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2592
2593 // free eventually allocated BigBuf memory but keep Emulator Memory
2594 BigBuf_free_keep_EM();
99cf19d9 2595 clear_trace();
2596 set_tracing(TRUE);
2597
7bc95e2e 2598 bool finished = FALSE;
2b1f4228 2599 while (!BUTTON_PRESS() && !finished && !usb_poll_validate_length()) {
9ca155ba 2600 WDT_HIT();
9ca155ba
M
2601
2602 // find reader field
9ca155ba 2603 if (cardSTATE == MFEMUL_NOFIELD) {
0c8d25eb 2604 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
9ca155ba 2605 if (vHf > MF_MINFIELDV) {
0014cb46 2606 cardSTATE_TO_IDLE();
9ca155ba
M
2607 LED_A_ON();
2608 }
2609 }
0194ce8f 2610 if (cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2611
f38cfd66 2612 // Now, get data
6a1f2d82 2613 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2614 if (res == 2) { //Field is off!
2615 cardSTATE = MFEMUL_NOFIELD;
2616 LEDsoff();
2617 continue;
7bc95e2e 2618 } else if (res == 1) {
f38cfd66 2619 break; // return value 1 means button press
7bc95e2e 2620 }
2621
d2f487af 2622 // REQ or WUP request in ANY state and WUP in HALTED state
57850d9d 2623 // this if-statement doesn't match the specification above. (iceman)
0194ce8f 2624 if (len == 1 && ((receivedCmd[0] == ISO14443A_CMD_REQA && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == ISO14443A_CMD_WUPA)) {
d2f487af 2625 selTimer = GetTickCount();
0194ce8f 2626 EmSendCmdEx(atqa, sizeof(atqa), (receivedCmd[0] == ISO14443A_CMD_WUPA));
d2f487af 2627 cardSTATE = MFEMUL_SELECT1;
d2f487af 2628 crypto1_destroy(pcs);
2629 cardAUTHKEY = 0xff;
0194ce8f 2630 LEDsoff();
bf5d7992 2631 nonce = prand();
d2f487af 2632 continue;
0a39986e 2633 }
7bc95e2e 2634
50193c1e 2635 switch (cardSTATE) {
d2f487af 2636 case MFEMUL_NOFIELD:
2637 case MFEMUL_HALTED:
50193c1e 2638 case MFEMUL_IDLE:{
6a1f2d82 2639 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2640 break;
2641 }
2642 case MFEMUL_SELECT1:{
0194ce8f 2643 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT && receivedCmd[1] == 0x20)) {
d2f487af 2644 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2645 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2646 break;
9ca155ba 2647 }
9ca155ba 2648 // select card
0a39986e 2649 if (len == 9 &&
0194ce8f 2650 ( receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT &&
2651 receivedCmd[1] == 0x70 &&
2652 memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2653
2654 // SAK 4b
2655 EmSendCmd(sak_4, sizeof(sak_4));
2656 switch(_UID_LEN){
2657 case 4:
2658 cardSTATE = MFEMUL_WORK;
2659 LED_B_ON();
2660 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2661 continue;
2662 case 7:
2663 case 10:
2664 cardSTATE = MFEMUL_SELECT2;
2665 continue;
2666 default:break;
8556b852 2667 }
0194ce8f 2668 } else {
2669 cardSTATE_TO_IDLE();
2670 }
2671 break;
2672 }
2673 case MFEMUL_SELECT2:{
2674 if (!len) {
2675 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2676 break;
2677 }
2678 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 && receivedCmd[1] == 0x20)) {
2679 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2680 break;
2681 }
2682 if (len == 9 &&
2683 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 &&
2684 receivedCmd[1] == 0x70 &&
2685 memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0) ) {
2686
2687 EmSendCmd(sak_7, sizeof(sak_7));
2688 switch(_UID_LEN){
2689 case 7:
2690 cardSTATE = MFEMUL_WORK;
2691 LED_B_ON();
2692 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2693 continue;
2694 case 10:
2695 cardSTATE = MFEMUL_SELECT3;
2696 continue;
2697 default:break;
2698 }
bc939371 2699 }
2700 cardSTATE_TO_IDLE();
0194ce8f 2701 break;
2702 }
2703 case MFEMUL_SELECT3:{
2704 if (!len) {
2705 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2706 break;
2707 }
2708 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 && receivedCmd[1] == 0x20)) {
2709 EmSendCmd(rUIDBCC3, sizeof(rUIDBCC3));
2710 break;
2711 }
2712 if (len == 9 &&
2713 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 &&
2714 receivedCmd[1] == 0x70 &&
2715 memcmp(&receivedCmd[2], rUIDBCC3, 4) == 0) ) {
2716
2717 EmSendCmd(sak_10, sizeof(sak_10));
2718 cardSTATE = MFEMUL_WORK;
2719 LED_B_ON();
2720 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol3 time: %d", GetTickCount() - selTimer);
2721 break;
9ca155ba 2722 }
bc939371 2723 cardSTATE_TO_IDLE();
50193c1e
M
2724 break;
2725 }
d2f487af 2726 case MFEMUL_AUTH1:{
495d7f13 2727 if( len != 8) {
d2f487af 2728 cardSTATE_TO_IDLE();
6a1f2d82 2729 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2730 break;
2731 }
0c8d25eb 2732
bc939371 2733 uint32_t nr = bytes_to_num(receivedCmd, 4);
2734 uint32_t ar = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2735
84bdbc19 2736 // Collect AR/NR per keytype & sector
2737 if ( (flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) {
bf5d7992 2738
84bdbc19 2739 int8_t index = -1;
2740 int8_t empty = -1;
2741 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
2742 // find which index to use
2743 if ( (cardAUTHSC == ar_nr_nonces[i].sector) && (cardAUTHKEY == ar_nr_nonces[i].keytype))
2744 index = i;
2745
2746 // keep track of empty slots.
2747 if ( ar_nr_nonces[i].state == EMPTY)
2748 empty = i;
2749 }
2750 // if no empty slots. Choose first and overwrite.
2751 if ( index == -1 ) {
2752 if ( empty == -1 ) {
2753 index = 0;
2754 ar_nr_nonces[index].state = EMPTY;
2755 } else {
2756 index = empty;
b6e05350 2757 }
b6e05350 2758 }
b6e05350 2759
84bdbc19 2760 switch(ar_nr_nonces[index].state) {
2761 case EMPTY: {
2762 // first nonce collect
2763 ar_nr_nonces[index].cuid = cuid;
2764 ar_nr_nonces[index].sector = cardAUTHSC;
2765 ar_nr_nonces[index].keytype = cardAUTHKEY;
2766 ar_nr_nonces[index].nonce = nonce;
2767 ar_nr_nonces[index].nr = nr;
2768 ar_nr_nonces[index].ar = ar;
2769 ar_nr_nonces[index].state = FIRST;
2770 break;
2771 }
2772 case FIRST : {
2773 // second nonce collect
2774 ar_nr_nonces[index].nonce2 = nonce;
2775 ar_nr_nonces[index].nr2 = nr;
2776 ar_nr_nonces[index].ar2 = ar;
2777 ar_nr_nonces[index].state = SECOND;
2778
2779 // send to client
2780 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, 0, 0, &ar_nr_nonces[index], sizeof(nonces_t));
2781
2782 ar_nr_nonces[index].state = EMPTY;
2783 ar_nr_nonces[index].sector = 0;
2784 ar_nr_nonces[index].keytype = 0;
2785 break;
2786 }
2787 default: break;
2788 }
2789 }
b6e05350
MF
2790
2791 /*
84bdbc19 2792 // Interactive mode flag, means we need to send ACK
b6e05350 2793
0194ce8f 2794 crypto1_word(pcs, ar , 1);
2795 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2796
2797 test if auth OK
2798 if (cardRr != prng_successor(nonce, 64)){
c3c241f3 2799
0194ce8f 2800 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2801 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2802 cardRr, prng_successor(nonce, 64));
2803 Shouldn't we respond anything here?
2804 Right now, we don't nack or anything, which causes the
2805 reader to do a WUPA after a while. /Martin
2806 -- which is the correct response. /piwi
2807 cardSTATE_TO_IDLE();
2808 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2809 break;
2810 }
2811 */
2812
d2f487af 2813 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
d2f487af 2814 num_to_bytes(ans, 4, rAUTH_AT);
d2f487af 2815 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2816 LED_C_ON();
bc939371 2817
495d7f13 2818 if (MF_DBGLEVEL >= 4) {
2819 Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2820 cardAUTHSC,
2821 cardAUTHKEY == 0 ? 'A' : 'B',
2822 GetTickCount() - authTimer
2823 );
2824 }
0014cb46 2825 cardSTATE = MFEMUL_WORK;
0194ce8f 2826 break;
50193c1e 2827 }
7bc95e2e 2828 case MFEMUL_WORK:{
2829 if (len == 0) {
6a1f2d82 2830 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2831 break;
0194ce8f 2832 }
d2f487af 2833 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2834
495d7f13 2835 if(encrypted_data)
51969283 2836 mf_crypto1_decrypt(pcs, receivedCmd, len);
7bc95e2e 2837
0194ce8f 2838 if (len == 4 && (receivedCmd[0] == MIFARE_AUTH_KEYA ||
2839 receivedCmd[0] == MIFARE_AUTH_KEYB) ) {
2840
d2f487af 2841 authTimer = GetTickCount();
2842 cardAUTHSC = receivedCmd[1] / 4; // received block num
0194ce8f 2843 cardAUTHKEY = receivedCmd[0] - 0x60; // & 1
2844 crypto1_destroy(pcs);
d2f487af 2845 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2846
0194ce8f 2847 if (!encrypted_data) {
2848 // first authentication
f38cfd66 2849 crypto1_word(pcs, cuid ^ nonce, 0);// Update crypto state
d2f487af 2850 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
0194ce8f 2851
2852 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2853
2854 } else {
2855 // nested authentication
7bc95e2e 2856 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2857 num_to_bytes(ans, 4, rAUTH_AT);
0194ce8f 2858
2859 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
d2f487af 2860 }
0c8d25eb 2861
d2f487af 2862 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
d2f487af 2863 cardSTATE = MFEMUL_AUTH1;
2864 break;
51969283 2865 }
7bc95e2e 2866
8f51ddb0
M
2867 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2868 // BUT... ACK --> NACK
2869 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2870 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2871 break;
2872 }
2873
2874 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2875 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2876 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2877 break;
0a39986e
M
2878 }
2879
7bc95e2e 2880 if(len != 4) {
6a1f2d82 2881 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2882 break;
2883 }
d2f487af 2884
0194ce8f 2885 if ( receivedCmd[0] == ISO14443A_CMD_READBLOCK ||
2886 receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK ||
2887 receivedCmd[0] == MIFARE_CMD_INC ||
2888 receivedCmd[0] == MIFARE_CMD_DEC ||
2889 receivedCmd[0] == MIFARE_CMD_RESTORE ||
2890 receivedCmd[0] == MIFARE_CMD_TRANSFER ) {
2891
7bc95e2e 2892 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2893 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2894 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2895 break;
2896 }
2897
7bc95e2e 2898 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2899 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2900 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2901 break;
2902 }
d2f487af 2903 }
2904 // read block
0194ce8f 2905 if (receivedCmd[0] == ISO14443A_CMD_READBLOCK) {
2906 if (MF_DBGLEVEL >= 4) Dbprintf("Reader reading block %d (0x%02x)", receivedCmd[1], receivedCmd[1]);
495d7f13 2907
8f51ddb0
M
2908 emlGetMem(response, receivedCmd[1], 1);
2909 AppendCrc14443a(response, 16);
6a1f2d82 2910 mf_crypto1_encrypt(pcs, response, 18, response_par);
2911 EmSendCmdPar(response, 18, response_par);
d2f487af 2912 numReads++;
12d708fe 2913 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
d2f487af 2914 Dbprintf("%d reads done, exiting", numReads);
2915 finished = true;
2916 }
0a39986e
M
2917 break;
2918 }
0a39986e 2919 // write block
0194ce8f 2920 if (receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK) {
2921 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)", receivedCmd[1], receivedCmd[1]);
8f51ddb0 2922 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2923 cardSTATE = MFEMUL_WRITEBL2;
2924 cardWRBL = receivedCmd[1];
0a39986e 2925 break;
7bc95e2e 2926 }
0014cb46 2927 // increment, decrement, restore
0194ce8f 2928 if ( receivedCmd[0] == MIFARE_CMD_INC ||
2929 receivedCmd[0] == MIFARE_CMD_DEC ||
2930 receivedCmd[0] == MIFARE_CMD_RESTORE) {
2931
2932 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2933
d2f487af 2934 if (emlCheckValBl(receivedCmd[1])) {
c3c241f3 2935 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2936 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2937 break;
2938 }
2939 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0194ce8f 2940 if (receivedCmd[0] == MIFARE_CMD_INC) cardSTATE = MFEMUL_INTREG_INC;
2941 if (receivedCmd[0] == MIFARE_CMD_DEC) cardSTATE = MFEMUL_INTREG_DEC;
2942 if (receivedCmd[0] == MIFARE_CMD_RESTORE) cardSTATE = MFEMUL_INTREG_REST;
0014cb46 2943 cardWRBL = receivedCmd[1];
0014cb46
M
2944 break;
2945 }
0014cb46 2946 // transfer
0194ce8f 2947 if (receivedCmd[0] == MIFARE_CMD_TRANSFER) {
2948 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)", receivedCmd[0], receivedCmd[1], receivedCmd[1]);
0014cb46
M
2949 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2950 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2951 else
2952 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2953 break;
2954 }
9ca155ba 2955 // halt
0194ce8f 2956 if (receivedCmd[0] == ISO14443A_CMD_HALT && receivedCmd[1] == 0x00) {
9ca155ba 2957 LED_B_OFF();
0a39986e 2958 LED_C_OFF();
0014cb46
M
2959 cardSTATE = MFEMUL_HALTED;
2960 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2961 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2962 break;
9ca155ba 2963 }
d2f487af 2964 // RATS
0194ce8f 2965 if (receivedCmd[0] == ISO14443A_CMD_RATS) {
8f51ddb0
M
2966 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2967 break;
2968 }
d2f487af 2969 // command not allowed
2970 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2971 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2972 break;
8f51ddb0
M
2973 }
2974 case MFEMUL_WRITEBL2:{
495d7f13 2975 if (len == 18) {
8f51ddb0
M
2976 mf_crypto1_decrypt(pcs, receivedCmd, len);
2977 emlSetMem(receivedCmd, cardWRBL, 1);
2978 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2979 cardSTATE = MFEMUL_WORK;
51969283 2980 } else {
0014cb46 2981 cardSTATE_TO_IDLE();
6a1f2d82 2982 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2983 }
8f51ddb0 2984 break;
50193c1e 2985 }
0014cb46
M
2986 case MFEMUL_INTREG_INC:{
2987 mf_crypto1_decrypt(pcs, receivedCmd, len);
2988 memcpy(&ans, receivedCmd, 4);
2989 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2990 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2991 cardSTATE_TO_IDLE();
2992 break;
7bc95e2e 2993 }
6a1f2d82 2994 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2995 cardINTREG = cardINTREG + ans;
2996 cardSTATE = MFEMUL_WORK;
2997 break;
2998 }
2999 case MFEMUL_INTREG_DEC:{
3000 mf_crypto1_decrypt(pcs, receivedCmd, len);
3001 memcpy(&ans, receivedCmd, 4);
3002 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
3003 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
3004 cardSTATE_TO_IDLE();
3005 break;
3006 }
6a1f2d82 3007 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
3008 cardINTREG = cardINTREG - ans;
3009 cardSTATE = MFEMUL_WORK;
3010 break;
3011 }
3012 case MFEMUL_INTREG_REST:{
3013 mf_crypto1_decrypt(pcs, receivedCmd, len);
3014 memcpy(&ans, receivedCmd, 4);
3015 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
3016 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
3017 cardSTATE_TO_IDLE();
3018 break;
3019 }
6a1f2d82 3020 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
3021 cardSTATE = MFEMUL_WORK;
3022 break;
3023 }
50193c1e 3024 }
50193c1e
M
3025 }
3026
bf5d7992 3027 if (MF_DBGLEVEL >= 1)
3028 Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
5ee53a0e 3029
e99acd00 3030 cmd_send(CMD_ACK,1,0,0,0,0); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
91c7a7cc 3031 LEDsoff();
5ee53a0e 3032 set_tracing(FALSE);
15c4dc5a 3033}
b62a5a84 3034
d2f487af 3035
b62a5a84
M
3036//-----------------------------------------------------------------------------
3037// MIFARE sniffer.
3038//
0194ce8f 3039// if no activity for 2sec, it sends the collected data to the client.
b62a5a84 3040//-----------------------------------------------------------------------------
bc939371 3041// "hf mf sniff"
5cd9ec01 3042void RAMFUNC SniffMifare(uint8_t param) {
bc939371 3043
b62a5a84 3044 LEDsoff();
810f5379 3045
aaa1a9a2 3046 // free eventually allocated BigBuf memory
3047 BigBuf_free(); BigBuf_Clear_ext(false);
3000dc4e
MHS
3048 clear_trace();
3049 set_tracing(TRUE);
b62a5a84 3050
b62a5a84 3051 // The command (reader -> tag) that we're receiving.
810f5379 3052 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
495d7f13 3053 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
810f5379 3054
b62a5a84 3055 // The response (tag -> reader) that we're receiving.
495d7f13 3056 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE] = {0x00};
3057 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b62a5a84 3058
99cf19d9 3059 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
3060
f71f4deb 3061 // allocate the DMA buffer, used to stream samples from the FPGA
0194ce8f 3062 // [iceman] is this sniffed data unsigned?
f71f4deb 3063 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 3064 uint8_t *data = dmaBuf;
3065 uint8_t previous_data = 0;
5cd9ec01
M
3066 int maxDataLen = 0;
3067 int dataLen = 0;
7bc95e2e 3068 bool ReaderIsActive = FALSE;
3069 bool TagIsActive = FALSE;
3070
b62a5a84 3071 // Set up the demodulator for tag -> reader responses.
6a1f2d82 3072 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
3073
3074 // Set up the demodulator for the reader -> tag commands
6a1f2d82 3075 UartInit(receivedCmd, receivedCmdPar);
b62a5a84 3076
57850d9d 3077 // Setup and start DMA.
3078 // set transfer address and number of bytes. Start transfer.
3079 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
3080 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
3081 return;
3082 }
b62a5a84 3083
b62a5a84 3084 LED_D_OFF();
0194ce8f 3085
39864b0b 3086 MfSniffInit();
b62a5a84 3087
b62a5a84 3088 // And now we loop, receiving samples.
0194ce8f 3089 for(uint32_t sniffCounter = 0;; ) {
91c7a7cc 3090
3091 LED_A_ON();
3092 WDT_HIT();
7bc95e2e 3093
5cd9ec01
M
3094 if(BUTTON_PRESS()) {
3095 DbpString("cancelled by button");
7bc95e2e 3096 break;
5cd9ec01 3097 }
91c7a7cc 3098
7bc95e2e 3099 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3100 // check if a transaction is completed (timeout after 2000ms).
3101 // if yes, stop the DMA transfer and send what we have so far to the client
3102 if (MfSniffSend(2000)) {
3103 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3104 sniffCounter = 0;
3105 data = dmaBuf;
3106 maxDataLen = 0;
3107 ReaderIsActive = FALSE;
3108 TagIsActive = FALSE;
57850d9d 3109 // Setup and start DMA. set transfer address and number of bytes. Start transfer.
3110 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
3111 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
3112 return;
3113 }
39864b0b 3114 }
39864b0b 3115 }
7bc95e2e 3116
3117 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3118 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
495d7f13 3119
3120 if (readBufDataP <= dmaBufDataP) // we are processing the same block of data which is currently being transferred
7bc95e2e 3121 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
495d7f13 3122 else
7bc95e2e 3123 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
495d7f13 3124
5cd9ec01 3125 // test for length of buffer
7bc95e2e 3126 if(dataLen > maxDataLen) { // we are more behind than ever...
3127 maxDataLen = dataLen;
f71f4deb 3128 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 3129 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 3130 break;
b62a5a84
M
3131 }
3132 }
5cd9ec01 3133 if(dataLen < 1) continue;
b62a5a84 3134
7bc95e2e 3135 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
3136 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3137 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3138 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
91c7a7cc 3139 Dbprintf("RxEmpty ERROR, data length:%d", dataLen); // temporary
5cd9ec01
M
3140 }
3141 // secondary buffer sets as primary, secondary buffer was stopped
3142 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3143 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
3144 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3145 }
5cd9ec01
M
3146
3147 LED_A_OFF();
b62a5a84 3148
7bc95e2e 3149 if (sniffCounter & 0x01) {
b62a5a84 3150
495d7f13 3151 // no need to try decoding tag data if the reader is sending
3152 if(!TagIsActive) {
7bc95e2e 3153 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3154 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3155 LED_C_INV();
495d7f13 3156
6a1f2d82 3157 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 3158
f8ada309 3159 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3160 DemodReset();
3161 }
3162 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3163 }
3164
495d7f13 3165 // no need to try decoding tag data if the reader is sending
3166 if(!ReaderIsActive) {
7bc95e2e 3167 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3168 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3169 LED_C_INV();
b62a5a84 3170
6a1f2d82 3171 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 3172
7bc95e2e 3173 DemodReset();
0ec548dc 3174 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3175 }
3176 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3177 }
b62a5a84
M
3178 }
3179
7bc95e2e 3180 previous_data = *data;
3181 sniffCounter++;
5cd9ec01 3182 data++;
495d7f13 3183
3184 if(data == dmaBuf + DMA_BUFFER_SIZE)
5cd9ec01 3185 data = dmaBuf;
7bc95e2e 3186
b62a5a84 3187 } // main cycle
bc939371 3188
3189 if (MF_DBGLEVEL >= 1) Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3190
55acbb2a 3191 FpgaDisableSscDma();
39864b0b 3192 MfSniffEnd();
91c7a7cc 3193 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3194 LEDsoff();
5ee53a0e 3195 set_tracing(FALSE);
3803d529 3196}
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