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a126332a 1 //-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
e30c654b 13#include "proxmark3.h"
15c4dc5a 14#include "apps.h"
f7e3ed82 15#include "util.h"
9ab7a6c7 16#include "string.h"
902cb3c0 17#include "cmd.h"
15c4dc5a 18#include "iso14443crc.h"
534983d7 19#include "iso14443a.h"
6fc68747 20#include "iso14443b.h"
20f9a2a1
M
21#include "crapto1.h"
22#include "mifareutil.h"
3000dc4e 23#include "BigBuf.h"
f8ada309 24#include "parity.h"
25
534983d7 26static uint32_t iso14a_timeout;
1e262141 27int rsamples = 0;
1e262141 28uint8_t trigger = 0;
b0127e65 29// the block number for the ISO14443-4 PCB
30static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 31
7bc95e2e 32//
33// ISO14443 timing:
34//
35// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
36#define REQUEST_GUARD_TIME (7000/16 + 1)
37// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
38#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
39// bool LastCommandWasRequest = FALSE;
40
41//
42// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
43//
d714d3ef 44// When the PM acts as reader and is receiving tag data, it takes
45// 3 ticks delay in the AD converter
46// 16 ticks until the modulation detector completes and sets curbit
47// 8 ticks until bit_to_arm is assigned from curbit
48// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 49// 4*16 ticks until we measure the time
50// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 51#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 52
53// When the PM acts as a reader and is sending, it takes
54// 4*16 ticks until we can write data to the sending hold register
55// 8*16 ticks until the SHR is transferred to the Sending Shift Register
56// 8 ticks until the first transfer starts
57// 8 ticks later the FPGA samples the data
58// 1 tick to assign mod_sig_coil
59#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
60
61// When the PM acts as tag and is receiving it takes
d714d3ef 62// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 63// 3 ticks for the A/D conversion,
64// 8 ticks on average until the start of the SSC transfer,
65// 8 ticks until the SSC samples the first data
66// 7*16 ticks to complete the transfer from FPGA to ARM
67// 8 ticks until the next ssp_clk rising edge
d714d3ef 68// 4*16 ticks until we measure the time
7bc95e2e 69// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 70#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 71
72// The FPGA will report its internal sending delay in
73uint16_t FpgaSendQueueDelay;
74// the 5 first bits are the number of bits buffered in mod_sig_buf
75// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
76#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
77
78// When the PM acts as tag and is sending, it takes
d714d3ef 79// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 80// 8*16 ticks until the SHR is transferred to the Sending Shift Register
81// 8 ticks until the first transfer starts
82// 8 ticks later the FPGA samples the data
83// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
84// + 1 tick to assign mod_sig_coil
d714d3ef 85#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 86
87// When the PM acts as sniffer and is receiving tag data, it takes
88// 3 ticks A/D conversion
d714d3ef 89// 14 ticks to complete the modulation detection
90// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 91// + the delays in transferring data - which is the same for
92// sniffing reader and tag data and therefore not relevant
d714d3ef 93#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 94
d714d3ef 95// When the PM acts as sniffer and is receiving reader data, it takes
96// 2 ticks delay in analogue RF receiver (for the falling edge of the
97// start bit, which marks the start of the communication)
7bc95e2e 98// 3 ticks A/D conversion
d714d3ef 99// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 100// + the delays in transferring data - which is the same for
101// sniffing reader and tag data and therefore not relevant
d714d3ef 102#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 103
104//variables used for timing purposes:
105//these are in ssp_clk cycles:
6a1f2d82 106static uint32_t NextTransferTime;
107static uint32_t LastTimeProxToAirStart;
108static uint32_t LastProxToAirDuration;
7bc95e2e 109
8f51ddb0 110// CARD TO READER - manchester
72934aa3 111// Sequence D: 11110000 modulation with subcarrier during first half
112// Sequence E: 00001111 modulation with subcarrier during second half
113// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 114// READER TO CARD - miller
72934aa3 115// Sequence X: 00001100 drop after half a period
116// Sequence Y: 00000000 no drop
117// Sequence Z: 11000000 drop at start
118#define SEC_D 0xf0
119#define SEC_E 0x0f
120#define SEC_F 0x00
121#define SEC_X 0x0c
122#define SEC_Y 0x00
123#define SEC_Z 0xc0
15c4dc5a 124
902cb3c0 125void iso14a_set_trigger(bool enable) {
534983d7 126 trigger = enable;
127}
128
b0127e65 129void iso14a_set_timeout(uint32_t timeout) {
130 iso14a_timeout = timeout;
19a700a8 131 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
b0127e65 132}
8556b852 133
19a700a8 134void iso14a_set_ATS_timeout(uint8_t *ats) {
19a700a8 135 uint8_t tb1;
136 uint8_t fwi;
137 uint32_t fwt;
138
139 if (ats[0] > 1) { // there is a format byte T0
140 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
4c0cf2d2 141
142 if ((ats[1] & 0x10) == 0x10) // there is an interface byte TA(1) preceding TB(1)
19a700a8 143 tb1 = ats[3];
4c0cf2d2 144 else
19a700a8 145 tb1 = ats[2];
4c0cf2d2 146
19a700a8 147 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
ca5bad3d 148 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
149 //fwt = 4096 * (1 << fwi);
19a700a8 150
ca5bad3d 151 iso14a_set_timeout(fwt/(8*16));
152 //iso14a_set_timeout(fwt/128);
19a700a8 153 }
154 }
155}
156
15c4dc5a 157//-----------------------------------------------------------------------------
158// Generate the parity value for a byte sequence
e30c654b 159//
15c4dc5a 160//-----------------------------------------------------------------------------
91c7a7cc 161void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par) {
6a1f2d82 162 uint16_t paritybit_cnt = 0;
163 uint16_t paritybyte_cnt = 0;
164 uint8_t parityBits = 0;
165
166 for (uint16_t i = 0; i < iLen; i++) {
167 // Generate the parity bits
f8ada309 168 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
6a1f2d82 169 if (paritybit_cnt == 7) {
170 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
171 parityBits = 0; // and advance to next Parity Byte
172 paritybyte_cnt++;
173 paritybit_cnt = 0;
174 } else {
175 paritybit_cnt++;
176 }
5f6d6c90 177 }
6a1f2d82 178
179 // save remaining parity bits
91c7a7cc 180 par[paritybyte_cnt] = parityBits;
15c4dc5a 181}
182
91c7a7cc 183void AppendCrc14443a(uint8_t* data, int len) {
5f6d6c90 184 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 185}
186
7bc95e2e 187//=============================================================================
188// ISO 14443 Type A - Miller decoder
189//=============================================================================
190// Basics:
191// This decoder is used when the PM3 acts as a tag.
192// The reader will generate "pauses" by temporarily switching of the field.
193// At the PM3 antenna we will therefore measure a modulated antenna voltage.
194// The FPGA does a comparison with a threshold and would deliver e.g.:
195// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
196// The Miller decoder needs to identify the following sequences:
197// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
198// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
199// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
200// Note 1: the bitstream may start at any time. We therefore need to sync.
201// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 202//-----------------------------------------------------------------------------
b62a5a84 203static tUart Uart;
15c4dc5a 204
d7aa3739 205// Lookup-Table to decide if 4 raw bits are a modulation.
0ec548dc 206// We accept the following:
207// 0001 - a 3 tick wide pause
208// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
209// 0111 - a 2 tick wide pause shifted left
210// 1001 - a 2 tick wide pause shifted right
d7aa3739 211const bool Mod_Miller_LUT[] = {
0ec548dc 212 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
213 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
d7aa3739 214};
0ec548dc 215#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
216#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 217
91c7a7cc 218void UartReset() {
7bc95e2e 219 Uart.state = STATE_UNSYNCD;
220 Uart.bitCount = 0;
221 Uart.len = 0; // number of decoded data bytes
6a1f2d82 222 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 223 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 224 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 225 Uart.startTime = 0;
226 Uart.endTime = 0;
46c65fed 227
228 Uart.byteCntMax = 0;
229 Uart.posCnt = 0;
230 Uart.syncBit = 9999;
7bc95e2e 231}
15c4dc5a 232
91c7a7cc 233void UartInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 234 Uart.output = data;
235 Uart.parity = parity;
0ec548dc 236 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
6a1f2d82 237 UartReset();
238}
d714d3ef 239
7bc95e2e 240// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 241static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time) {
0ec548dc 242 Uart.fourBits = (Uart.fourBits << 8) | bit;
7bc95e2e 243
0c8d25eb 244 if (Uart.state == STATE_UNSYNCD) { // not yet synced
91c7a7cc 245 Uart.syncBit = 9999; // not set
46c65fed 246
247 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
248 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
249 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
250
0ec548dc 251 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
46c65fed 252 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
253 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
0ec548dc 254 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
46c65fed 255 //
256#define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
257#define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
258
0ec548dc 259 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
260 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
261 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
262 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
263 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
264 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
265 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
266 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
267
268 if (Uart.syncBit != 9999) { // found a sync bit
91c7a7cc 269 Uart.startTime = non_real_time ? non_real_time : (GetCountSspClk() & 0xfffffff8);
270 Uart.startTime -= Uart.syncBit;
271 Uart.endTime = Uart.startTime;
272 Uart.state = STATE_START_OF_COMMUNICATION;
273 }
7bc95e2e 274 } else {
15c4dc5a 275
0ec548dc 276 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
277 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
d7aa3739 278 UartReset();
d7aa3739 279 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 280 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
281 UartReset();
7bc95e2e 282 } else {
283 Uart.bitCount++;
284 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
285 Uart.state = STATE_MILLER_Z;
286 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
287 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
288 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
289 Uart.parityBits <<= 1; // make room for the parity bit
290 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
291 Uart.bitCount = 0;
292 Uart.shiftReg = 0;
6a1f2d82 293 if((Uart.len&0x0007) == 0) { // every 8 data bytes
294 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
295 Uart.parityBits = 0;
296 }
15c4dc5a 297 }
7bc95e2e 298 }
d7aa3739 299 }
300 } else {
0ec548dc 301 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 302 Uart.bitCount++;
303 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
304 Uart.state = STATE_MILLER_X;
305 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
306 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
307 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
308 Uart.parityBits <<= 1; // make room for the new parity bit
309 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
310 Uart.bitCount = 0;
311 Uart.shiftReg = 0;
6a1f2d82 312 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
313 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
314 Uart.parityBits = 0;
315 }
7bc95e2e 316 }
d7aa3739 317 } else { // no modulation in both halves - Sequence Y
7bc95e2e 318 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 319 Uart.state = STATE_UNSYNCD;
6a1f2d82 320 Uart.bitCount--; // last "0" was part of EOC sequence
321 Uart.shiftReg <<= 1; // drop it
322 if(Uart.bitCount > 0) { // if we decoded some bits
323 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
324 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
325 Uart.parityBits <<= 1; // add a (void) parity bit
326 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
327 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
328 return TRUE;
329 } else if (Uart.len & 0x0007) { // there are some parity bits to store
330 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
331 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 332 }
333 if (Uart.len) {
6a1f2d82 334 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 335 } else {
0c8d25eb 336 UartReset(); // Nothing received - start over
7bc95e2e 337 }
15c4dc5a 338 }
7bc95e2e 339 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
340 UartReset();
7bc95e2e 341 } else { // a logic "0"
342 Uart.bitCount++;
343 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
344 Uart.state = STATE_MILLER_Y;
345 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
346 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
347 Uart.parityBits <<= 1; // make room for the parity bit
348 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
349 Uart.bitCount = 0;
350 Uart.shiftReg = 0;
6a1f2d82 351 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
352 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
353 Uart.parityBits = 0;
354 }
15c4dc5a 355 }
356 }
d7aa3739 357 }
15c4dc5a 358 }
7bc95e2e 359 }
7bc95e2e 360 return FALSE; // not finished yet, need more data
15c4dc5a 361}
362
7bc95e2e 363
364
15c4dc5a 365//=============================================================================
e691fc45 366// ISO 14443 Type A - Manchester decoder
15c4dc5a 367//=============================================================================
e691fc45 368// Basics:
7bc95e2e 369// This decoder is used when the PM3 acts as a reader.
e691fc45 370// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
371// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
372// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
373// The Manchester decoder needs to identify the following sequences:
374// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
375// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
376// 8 ticks unmodulated: Sequence F = end of communication
377// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 378// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 379// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 380static tDemod Demod;
15c4dc5a 381
d7aa3739 382// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 383// We accept three or four "1" in any position
7bc95e2e 384const bool Mod_Manchester_LUT[] = {
d7aa3739 385 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 386 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 387};
388
389#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
390#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 391
91c7a7cc 392void DemodReset() {
7bc95e2e 393 Demod.state = DEMOD_UNSYNCD;
394 Demod.len = 0; // number of decoded data bytes
6a1f2d82 395 Demod.parityLen = 0;
7bc95e2e 396 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
397 Demod.parityBits = 0; //
398 Demod.collisionPos = 0; // Position of collision bit
399 Demod.twoBits = 0xffff; // buffer for 2 Bits
400 Demod.highCnt = 0;
401 Demod.startTime = 0;
91c7a7cc 402 Demod.endTime = 0;
46c65fed 403 Demod.bitCount = 0;
404 Demod.syncBit = 0xFFFF;
405 Demod.samples = 0;
e691fc45 406}
15c4dc5a 407
91c7a7cc 408void DemodInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 409 Demod.output = data;
410 Demod.parity = parity;
411 DemodReset();
412}
413
7bc95e2e 414// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 415static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time) {
7bc95e2e 416 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 417
7bc95e2e 418 if (Demod.state == DEMOD_UNSYNCD) {
419
420 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
421 if (Demod.twoBits == 0x0000) {
422 Demod.highCnt++;
423 } else {
424 Demod.highCnt = 0;
425 }
426 } else {
427 Demod.syncBit = 0xFFFF; // not set
428 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
429 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
430 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
431 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
432 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
433 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
434 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
435 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 436 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 437 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
438 Demod.startTime -= Demod.syncBit;
439 Demod.bitCount = offset; // number of decoded data bits
e691fc45 440 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 441 }
7bc95e2e 442 }
7bc95e2e 443 } else {
15c4dc5a 444
7bc95e2e 445 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
446 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 447 if (!Demod.collisionPos) {
448 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
449 }
450 } // modulation in first half only - Sequence D = 1
7bc95e2e 451 Demod.bitCount++;
452 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
453 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 454 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 455 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 456 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
457 Demod.bitCount = 0;
458 Demod.shiftReg = 0;
6a1f2d82 459 if((Demod.len&0x0007) == 0) { // every 8 data bytes
460 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
461 Demod.parityBits = 0;
462 }
15c4dc5a 463 }
7bc95e2e 464 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
465 } else { // no modulation in first half
466 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 467 Demod.bitCount++;
7bc95e2e 468 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 469 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 470 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 471 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 472 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
473 Demod.bitCount = 0;
474 Demod.shiftReg = 0;
6a1f2d82 475 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
476 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
477 Demod.parityBits = 0;
478 }
15c4dc5a 479 }
7bc95e2e 480 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 481 } else { // no modulation in both halves - End of communication
6a1f2d82 482 if(Demod.bitCount > 0) { // there are some remaining data bits
483 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
484 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
485 Demod.parityBits <<= 1; // add a (void) parity bit
486 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
487 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
488 return TRUE;
489 } else if (Demod.len & 0x0007) { // there are some parity bits to store
490 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
491 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 492 }
493 if (Demod.len) {
d7aa3739 494 return TRUE; // we are finished with decoding the raw data sequence
495 } else { // nothing received. Start over
496 DemodReset();
e691fc45 497 }
15c4dc5a 498 }
7bc95e2e 499 }
e691fc45 500 }
e691fc45 501 return FALSE; // not finished yet, need more data
15c4dc5a 502}
503
504//=============================================================================
505// Finally, a `sniffer' for ISO 14443 Type A
506// Both sides of communication!
507//=============================================================================
508
509//-----------------------------------------------------------------------------
510// Record the sequence of commands sent by the reader to the tag, with
511// triggering so that we start recording at the point that the tag is moved
512// near the reader.
513//-----------------------------------------------------------------------------
d26849d4 514void RAMFUNC SniffIso14443a(uint8_t param) {
5cd9ec01
M
515 // param:
516 // bit 0 - trigger from first card answer
517 // bit 1 - trigger from first reader 7-bit request
5cd9ec01 518 LEDsoff();
5cd9ec01 519
99cf19d9 520 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
7bc95e2e 521
f71f4deb 522 // Allocate memory from BigBuf for some buffers
523 // free all previous allocations first
aaa1a9a2 524 BigBuf_free(); BigBuf_Clear_ext(false);
7838f4be 525 clear_trace();
526 set_tracing(TRUE);
527
5cd9ec01 528 // The command (reader -> tag) that we're receiving.
f71f4deb 529 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
530 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 531
5cd9ec01 532 // The response (tag -> reader) that we're receiving.
f71f4deb 533 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
534 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
535
536 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 537 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
538
7bc95e2e 539 uint8_t *data = dmaBuf;
540 uint8_t previous_data = 0;
5cd9ec01
M
541 int maxDataLen = 0;
542 int dataLen = 0;
7bc95e2e 543 bool TagIsActive = FALSE;
544 bool ReaderIsActive = FALSE;
545
5cd9ec01 546 // Set up the demodulator for tag -> reader responses.
6a1f2d82 547 DemodInit(receivedResponse, receivedResponsePar);
548
5cd9ec01 549 // Set up the demodulator for the reader -> tag commands
6a1f2d82 550 UartInit(receivedCmd, receivedCmdPar);
551
7bc95e2e 552 // Setup and start DMA.
5cd9ec01 553 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 554
99cf19d9 555 // We won't start recording the frames that we acquire until we trigger;
556 // a good trigger condition to get started is probably when we see a
557 // response from the tag.
558 // triggered == FALSE -- to wait first for card
559 bool triggered = !(param & 0x03);
560
5cd9ec01 561 // And now we loop, receiving samples.
7bc95e2e 562 for(uint32_t rsamples = 0; TRUE; ) {
563
5cd9ec01
M
564 if(BUTTON_PRESS()) {
565 DbpString("cancelled by button");
7bc95e2e 566 break;
5cd9ec01 567 }
15c4dc5a 568
5cd9ec01
M
569 LED_A_ON();
570 WDT_HIT();
15c4dc5a 571
5cd9ec01
M
572 int register readBufDataP = data - dmaBuf;
573 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
574 if (readBufDataP <= dmaBufDataP){
575 dataLen = dmaBufDataP - readBufDataP;
576 } else {
7bc95e2e 577 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
578 }
579 // test for length of buffer
580 if(dataLen > maxDataLen) {
581 maxDataLen = dataLen;
f71f4deb 582 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 583 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
584 break;
5cd9ec01
M
585 }
586 }
587 if(dataLen < 1) continue;
588
589 // primary buffer was stopped( <-- we lost data!
590 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
591 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
592 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 593 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
594 }
595 // secondary buffer sets as primary, secondary buffer was stopped
596 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
597 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
598 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
599 }
600
601 LED_A_OFF();
7bc95e2e 602
603 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 604
7bc95e2e 605 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
606 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
607 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
608 LED_C_ON();
5cd9ec01 609
7bc95e2e 610 // check - if there is a short 7bit request from reader
611 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 612
7bc95e2e 613 if(triggered) {
6a1f2d82 614 if (!LogTrace(receivedCmd,
615 Uart.len,
616 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
617 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
618 Uart.parity,
619 TRUE)) break;
7bc95e2e 620 }
621 /* And ready to receive another command. */
622 UartReset();
623 /* And also reset the demod code, which might have been */
624 /* false-triggered by the commands from the reader. */
625 DemodReset();
626 LED_B_OFF();
627 }
628 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 629 }
3be2a5ae 630
7bc95e2e 631 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
632 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
633 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
634 LED_B_ON();
5cd9ec01 635
6a1f2d82 636 if (!LogTrace(receivedResponse,
637 Demod.len,
638 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
639 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
640 Demod.parity,
641 FALSE)) break;
5cd9ec01 642
7bc95e2e 643 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 644
7bc95e2e 645 // And ready to receive another response.
646 DemodReset();
0ec548dc 647 // And reset the Miller decoder including itS (now outdated) input buffer
648 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 649 LED_C_OFF();
650 }
651 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
652 }
5cd9ec01
M
653 }
654
7bc95e2e 655 previous_data = *data;
656 rsamples++;
5cd9ec01 657 data++;
d714d3ef 658 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
659 data = dmaBuf;
660 }
661 } // main cycle
662
7bc95e2e 663 FpgaDisableSscDma();
7838f4be 664 LEDsoff();
665
7bc95e2e 666 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
3000dc4e 667 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
5ee53a0e 668
91c7a7cc 669 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 670 set_tracing(FALSE);
15c4dc5a 671}
672
15c4dc5a 673//-----------------------------------------------------------------------------
674// Prepare tag messages
675//-----------------------------------------------------------------------------
91c7a7cc 676static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity) {
8f51ddb0 677 ToSendReset();
15c4dc5a 678
679 // Correction bit, might be removed when not needed
680 ToSendStuffBit(0);
681 ToSendStuffBit(0);
682 ToSendStuffBit(0);
683 ToSendStuffBit(0);
684 ToSendStuffBit(1); // 1
685 ToSendStuffBit(0);
686 ToSendStuffBit(0);
687 ToSendStuffBit(0);
8f51ddb0 688
15c4dc5a 689 // Send startbit
72934aa3 690 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 691 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 692
6a1f2d82 693 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 694 uint8_t b = cmd[i];
15c4dc5a 695
696 // Data bits
6a1f2d82 697 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 698 if(b & 1) {
72934aa3 699 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 700 } else {
72934aa3 701 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
702 }
703 b >>= 1;
704 }
15c4dc5a 705
0014cb46 706 // Get the parity bit
6a1f2d82 707 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 708 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 709 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 710 } else {
72934aa3 711 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 712 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 713 }
8f51ddb0 714 }
15c4dc5a 715
8f51ddb0
M
716 // Send stopbit
717 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 718
8f51ddb0 719 // Convert from last byte pos to length
6fc68747 720 ++ToSendMax;
8f51ddb0
M
721}
722
91c7a7cc 723static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len) {
7504dc50 724 uint8_t par[MAX_PARITY_SIZE] = {0};
6a1f2d82 725 GetParity(cmd, len, par);
726 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 727}
728
91c7a7cc 729static void Code4bitAnswerAsTag(uint8_t cmd) {
8f51ddb0 730 int i;
91c7a7cc 731 uint8_t b = cmd;
8f51ddb0 732
5f6d6c90 733 ToSendReset();
8f51ddb0
M
734
735 // Correction bit, might be removed when not needed
736 ToSendStuffBit(0);
737 ToSendStuffBit(0);
738 ToSendStuffBit(0);
739 ToSendStuffBit(0);
740 ToSendStuffBit(1); // 1
741 ToSendStuffBit(0);
742 ToSendStuffBit(0);
743 ToSendStuffBit(0);
744
745 // Send startbit
746 ToSend[++ToSendMax] = SEC_D;
747
8f51ddb0
M
748 for(i = 0; i < 4; i++) {
749 if(b & 1) {
750 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 751 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
752 } else {
753 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 754 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
755 }
756 b >>= 1;
757 }
758
759 // Send stopbit
760 ToSend[++ToSendMax] = SEC_F;
761
5f6d6c90 762 // Convert from last byte pos to length
763 ToSendMax++;
15c4dc5a 764}
765
766//-----------------------------------------------------------------------------
767// Wait for commands from reader
768// Stop when button is pressed
769// Or return TRUE when command is captured
770//-----------------------------------------------------------------------------
91c7a7cc 771static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len) {
15c4dc5a 772 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
773 // only, since we are receiving, not transmitting).
774 // Signal field is off with the appropriate LED
775 LED_D_OFF();
776 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
777
ca5bad3d 778 // Now run a `software UART` on the stream of incoming samples.
6a1f2d82 779 UartInit(received, parity);
7bc95e2e 780
781 // clear RXRDY:
782 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 783
784 for(;;) {
785 WDT_HIT();
786
787 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 788
15c4dc5a 789 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 790 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
791 if(MillerDecoding(b, 0)) {
792 *len = Uart.len;
15c4dc5a 793 return TRUE;
794 }
7bc95e2e 795 }
15c4dc5a 796 }
797}
28afbd2b 798
6a1f2d82 799static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
7bc95e2e 800int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
28afbd2b 801int EmSend4bit(uint8_t resp);
6a1f2d82 802int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
803int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
804int EmSendCmd(uint8_t *resp, uint16_t respLen);
805int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
806bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
807 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
15c4dc5a 808
117d9ec2 809static uint8_t* free_buffer_pointer;
ce02f6f9 810
811typedef struct {
ca5bad3d 812 uint8_t* response;
813 size_t response_n;
814 uint8_t* modulation;
815 size_t modulation_n;
816 uint32_t ProxToAirDuration;
ce02f6f9 817} tag_response_info_t;
818
ce02f6f9 819bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 820 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 821 // This will need the following byte array for a modulation sequence
822 // 144 data bits (18 * 8)
823 // 18 parity bits
824 // 2 Start and stop
825 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
826 // 1 just for the case
827 // ----------- +
828 // 166 bytes, since every bit that needs to be send costs us a byte
829 //
91c7a7cc 830 // Prepare the tag modulation bits from the message
831 CodeIso14443aAsTag(response_info->response,response_info->response_n);
832
833 // Make sure we do not exceed the free buffer space
834 if (ToSendMax > max_buffer_size) {
835 Dbprintf("Out of memory, when modulating bits for tag answer:");
836 Dbhexdump(response_info->response_n,response_info->response,false);
837 return FALSE;
838 }
839
840 // Copy the byte array, used for this modulation to the buffer position
841 memcpy(response_info->modulation,ToSend,ToSendMax);
842
843 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
844 response_info->modulation_n = ToSendMax;
845 response_info->ProxToAirDuration = LastProxToAirDuration;
846 return TRUE;
ce02f6f9 847}
848
f71f4deb 849
850// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
851// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
852// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
853// -> need 273 bytes buffer
c9216a92 854// 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
855// 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
856#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
f71f4deb 857
ce02f6f9 858bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
ca5bad3d 859 // Retrieve and store the current buffer index
860 response_info->modulation = free_buffer_pointer;
861
862 // Determine the maximum size we can use from our buffer
863 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
864
865 // Forward the prepare tag modulation function to the inner function
866 if (prepare_tag_modulation(response_info, max_buffer_size)) {
867 // Update the free buffer offset
868 free_buffer_pointer += ToSendMax;
869 return true;
870 } else {
871 return false;
872 }
ce02f6f9 873}
874
15c4dc5a 875//-----------------------------------------------------------------------------
876// Main loop of simulated tag: receive commands from reader, decide what
877// response to send, and send it.
878//-----------------------------------------------------------------------------
91c7a7cc 879void SimulateIso14443aTag(int tagType, int flags, byte_t* data) {
a126332a 880 uint32_t counters[] = {0,0,0};
d26849d4 881 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
882 // This can be used in a reader-only attack.
883 // (it can also be retrieved via 'hf 14a list', but hey...
884 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
885 uint8_t ar_nr_collected = 0;
886
81cd0474 887 uint8_t sak;
32719adf 888
889 // PACK response to PWD AUTH for EV1/NTAG
e98572a1 890 uint8_t response8[4] = {0,0,0,0};
32719adf 891
81cd0474 892 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
e98572a1 893 uint8_t response1[2] = {0,0};
81cd0474 894
895 switch (tagType) {
896 case 1: { // MIFARE Classic
897 // Says: I am Mifare 1k - original line
898 response1[0] = 0x04;
899 response1[1] = 0x00;
900 sak = 0x08;
901 } break;
902 case 2: { // MIFARE Ultralight
903 // Says: I am a stupid memory tag, no crypto
32719adf 904 response1[0] = 0x44;
81cd0474 905 response1[1] = 0x00;
906 sak = 0x00;
907 } break;
908 case 3: { // MIFARE DESFire
909 // Says: I am a DESFire tag, ph33r me
910 response1[0] = 0x04;
911 response1[1] = 0x03;
912 sak = 0x20;
913 } break;
914 case 4: { // ISO/IEC 14443-4
915 // Says: I am a javacard (JCOP)
916 response1[0] = 0x04;
917 response1[1] = 0x00;
918 sak = 0x28;
919 } break;
3fe4ff4f 920 case 5: { // MIFARE TNP3XXX
921 // Says: I am a toy
922 response1[0] = 0x01;
923 response1[1] = 0x0f;
924 sak = 0x01;
d26849d4 925 } break;
926 case 6: { // MIFARE Mini
927 // Says: I am a Mifare Mini, 320b
928 response1[0] = 0x44;
929 response1[1] = 0x00;
930 sak = 0x09;
931 } break;
32719adf 932 case 7: { // NTAG?
933 // Says: I am a NTAG,
934 response1[0] = 0x44;
935 response1[1] = 0x00;
936 sak = 0x00;
937 // PACK
938 response8[0] = 0x80;
939 response8[1] = 0x80;
940 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
2b1f4228 941 // uid not supplied then get from emulator memory
942 if (data[0]==0) {
943 uint16_t start = 4 * (0+12);
944 uint8_t emdata[8];
945 emlGetMemBt( emdata, start, sizeof(emdata));
946 memcpy(data, emdata, 3); //uid bytes 0-2
947 memcpy(data+3, emdata+4, 4); //uid bytes 3-7
948 flags |= FLAG_7B_UID_IN_DATA;
949 }
32719adf 950 } break;
81cd0474 951 default: {
952 Dbprintf("Error: unkown tagtype (%d)",tagType);
953 return;
954 } break;
955 }
956
957 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 958 uint8_t response2[5] = {0x00};
81cd0474 959
960 // Check if the uid uses the (optional) part
c8b6da22 961 uint8_t response2a[5] = {0x00};
962
d26849d4 963 if (flags & FLAG_7B_UID_IN_DATA) {
81cd0474 964 response2[0] = 0x88;
d26849d4 965 response2[1] = data[0];
966 response2[2] = data[1];
967 response2[3] = data[2];
968
969 response2a[0] = data[3];
970 response2a[1] = data[4];
971 response2a[2] = data[5];
c3c241f3 972 response2a[3] = data[6]; //??
81cd0474 973 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
974
975 // Configure the ATQA and SAK accordingly
976 response1[0] |= 0x40;
977 sak |= 0x04;
978 } else {
d26849d4 979 memcpy(response2, data, 4);
980 //num_to_bytes(uid_1st,4,response2);
81cd0474 981 // Configure the ATQA and SAK accordingly
982 response1[0] &= 0xBF;
983 sak &= 0xFB;
984 }
985
986 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
987 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
988
989 // Prepare the mandatory SAK (for 4 and 7 byte UID)
c8b6da22 990 uint8_t response3[3] = {0x00};
81cd0474 991 response3[0] = sak;
992 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
993
994 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 995 uint8_t response3a[3] = {0x00};
81cd0474 996 response3a[0] = sak & 0xFB;
997 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
998
0de8e387 999 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
6a1f2d82 1000 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1001 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1002 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1003 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1004 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 1005 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1006
2b1f4228 1007 // Prepare GET_VERSION (different for UL EV-1 / NTAG)
32719adf 1008 //uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
2b1f4228 1009 //uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
32719adf 1010
c9216a92 1011 // Prepare CHK_TEARING
2b1f4228 1012 //uint8_t response9[] = {0xBD,0x90,0x3f};
c9216a92 1013
1014 #define TAG_RESPONSE_COUNT 10
7bc95e2e 1015 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1016 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1017 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1018 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1019 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1020 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1021 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1022 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
4c0cf2d2 1023
495d7f13 1024 { .response = response8, .response_n = sizeof(response8) } // EV1/NTAG PACK response
4c0cf2d2 1025 };
1026 //{ .response = response7_NTAG, .response_n = sizeof(response7_NTAG)}, // EV1/NTAG GET_VERSION response
2b1f4228 1027 //{ .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
4c0cf2d2 1028
7bc95e2e 1029
1030 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1031 // Such a response is less time critical, so we can prepare them on the fly
1032 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1033 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1034 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1035 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1036 tag_response_info_t dynamic_response_info = {
1037 .response = dynamic_response_buffer,
1038 .response_n = 0,
1039 .modulation = dynamic_modulation_buffer,
1040 .modulation_n = 0
1041 };
ce02f6f9 1042
99cf19d9 1043 // We need to listen to the high-frequency, peak-detected path.
1044 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1045
f71f4deb 1046 BigBuf_free_keep_EM();
1047
1048 // allocate buffers:
1049 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1050 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1051 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1052
1053 // clear trace
3000dc4e
MHS
1054 clear_trace();
1055 set_tracing(TRUE);
f71f4deb 1056
7bc95e2e 1057 // Prepare the responses of the anticollision phase
ce02f6f9 1058 // there will be not enough time to do this at the moment the reader sends it REQA
495d7f13 1059 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++)
7bc95e2e 1060 prepare_allocated_tag_modulation(&responses[i]);
15c4dc5a 1061
7bc95e2e 1062 int len = 0;
15c4dc5a 1063
1064 // To control where we are in the protocol
1065 int order = 0;
1066 int lastorder;
1067
1068 // Just to allow some checks
1069 int happened = 0;
1070 int happened2 = 0;
81cd0474 1071 int cmdsRecvd = 0;
15c4dc5a 1072
254b70a4 1073 cmdsRecvd = 0;
7bc95e2e 1074 tag_response_info_t* p_response;
15c4dc5a 1075
254b70a4 1076 LED_A_ON();
1077 for(;;) {
4c0cf2d2 1078
1079 WDT_HIT();
1080
7bc95e2e 1081 // Clean receive command buffer
6a1f2d82 1082 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1083 DbpString("Button press");
254b70a4 1084 break;
1085 }
7bc95e2e 1086
1087 p_response = NULL;
1088
254b70a4 1089 // Okay, look at the command now.
1090 lastorder = order;
1091 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1092 p_response = &responses[0]; order = 1;
254b70a4 1093 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1094 p_response = &responses[0]; order = 6;
254b70a4 1095 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1096 p_response = &responses[1]; order = 2;
6a1f2d82 1097 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1098 p_response = &responses[2]; order = 20;
254b70a4 1099 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1100 p_response = &responses[3]; order = 3;
254b70a4 1101 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1102 p_response = &responses[4]; order = 30;
254b70a4 1103 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
32719adf 1104 uint8_t block = receivedCmd[1];
2b1f4228 1105 // if Ultralight or NTAG (4 byte blocks)
1106 if ( tagType == 7 || tagType == 2 ) {
1107 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1108 uint16_t start = 4 * (block+12);
5e428463 1109 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1110 emlGetMemBt( emdata, start, 16);
1111 AppendCrc14443a(emdata, 16);
1112 EmSendCmdEx(emdata, sizeof(emdata), false);
2b1f4228 1113 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
32719adf 1114 p_response = NULL;
2b1f4228 1115 } else { // all other tags (16 byte block tags)
1116 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
32719adf 1117 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1118 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1119 p_response = NULL;
1120 }
91c7a7cc 1121 } else if(receivedCmd[0] == 0x3A) { // Received a FAST READ (ranged read)
1122 uint8_t emdata[MAX_FRAME_SIZE];
1123 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1124 int start = (receivedCmd[1]+12) * 4;
1125 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
1126 emlGetMemBt( emdata, start, len);
1127 AppendCrc14443a(emdata, len);
1128 EmSendCmdEx(emdata, len+2, false);
1129 p_response = NULL;
839a53ae 1130 } else if(receivedCmd[0] == 0x3C && tagType == 7) { // Received a READ SIGNATURE --
91c7a7cc 1131 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1132 uint16_t start = 4 * 4;
1133 uint8_t emdata[34];
1134 emlGetMemBt( emdata, start, 32);
1135 AppendCrc14443a(emdata, 32);
1136 EmSendCmdEx(emdata, sizeof(emdata), false);
1137 p_response = NULL;
a126332a 1138 } else if (receivedCmd[0] == 0x39 && tagType == 7) { // Received a READ COUNTER --
e9a92fe2 1139 uint8_t index = receivedCmd[1];
a126332a 1140 uint8_t data[] = {0x00,0x00,0x00,0x14,0xa5};
e9a92fe2 1141 if ( counters[index] > 0) {
1142 num_to_bytes(counters[index], 3, data);
1143 AppendCrc14443a(data, sizeof(data)-2);
1144 }
a126332a 1145 EmSendCmdEx(data,sizeof(data),false);
1146 p_response = NULL;
1147 } else if (receivedCmd[0] == 0xA5 && tagType == 7) { // Received a INC COUNTER --
ce3d6bd2 1148 // number of counter
a126332a 1149 uint8_t counter = receivedCmd[1];
1150 uint32_t val = bytes_to_num(receivedCmd+2,4);
1151 counters[counter] = val;
1152
ce3d6bd2 1153 // send ACK
1154 uint8_t ack[] = {0x0a};
1155 EmSendCmdEx(ack,sizeof(ack),false);
91c7a7cc 1156 p_response = NULL;
c9216a92 1157 } else if(receivedCmd[0] == 0x3E && tagType == 7) { // Received a CHECK_TEARING_EVENT --
2b1f4228 1158 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1159 uint8_t emdata[3];
1160 uint8_t counter=0;
1161 if (receivedCmd[1]<3) counter = receivedCmd[1];
1162 emlGetMemBt( emdata, 10+counter, 1);
1163 AppendCrc14443a(emdata, sizeof(emdata)-2);
1164 EmSendCmdEx(emdata, sizeof(emdata), false);
b0300679 1165 p_response = NULL;
254b70a4 1166 } else if(receivedCmd[0] == 0x50) { // Received a HALT
810f5379 1167 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1168 p_response = NULL;
254b70a4 1169 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
32719adf 1170
1171 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
2b1f4228 1172 uint8_t emdata[10];
1173 emlGetMemBt( emdata, 0, 8 );
1174 AppendCrc14443a(emdata, sizeof(emdata)-2);
1175 EmSendCmdEx(emdata, sizeof(emdata), false);
1176 p_response = NULL;
32719adf 1177 } else {
1178 p_response = &responses[5]; order = 7;
1179 }
254b70a4 1180 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
7bc95e2e 1181 if (tagType == 1 || tagType == 2) { // RATS not supported
1182 EmSend4bit(CARD_NACK_NA);
1183 p_response = NULL;
1184 } else {
1185 p_response = &responses[6]; order = 70;
1186 }
6a1f2d82 1187 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
810f5379 1188 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d26849d4 1189 uint32_t nonce = bytes_to_num(response5,4);
7bc95e2e 1190 uint32_t nr = bytes_to_num(receivedCmd,4);
1191 uint32_t ar = bytes_to_num(receivedCmd+4,4);
d26849d4 1192
91c7a7cc 1193 if(flags & FLAG_NR_AR_ATTACK ) {
d26849d4 1194 if(ar_nr_collected < 2){
1195 // Avoid duplicates... probably not necessary, nr should vary.
1196 //if(ar_nr_responses[3] != nr){
1197 ar_nr_responses[ar_nr_collected*5] = 0;
1198 ar_nr_responses[ar_nr_collected*5+1] = 0;
1199 ar_nr_responses[ar_nr_collected*5+2] = nonce;
1200 ar_nr_responses[ar_nr_collected*5+3] = nr;
1201 ar_nr_responses[ar_nr_collected*5+4] = ar;
1202 ar_nr_collected++;
1203 //}
1204 }
1205
1206 if(ar_nr_collected > 1 ) {
1207
1208 if (MF_DBGLEVEL >= 2) {
1209 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
1210 Dbprintf("../tools/mfkey/mfkey32 %07x%08x %08x %08x %08x %08x %08x",
1211 ar_nr_responses[0], // UID1
1212 ar_nr_responses[1], // UID2
1213 ar_nr_responses[2], // NT
1214 ar_nr_responses[3], // AR1
1215 ar_nr_responses[4], // NR1
1216 ar_nr_responses[8], // AR2
1217 ar_nr_responses[9] // NR2
1218 );
7838f4be 1219 Dbprintf("../tools/mfkey/mfkey32v2 %06x%08x %08x %08x %08x %08x %08x %08x",
1220 ar_nr_responses[0], // UID1
1221 ar_nr_responses[1], // UID2
1222 ar_nr_responses[2], // NT1
1223 ar_nr_responses[3], // AR1
1224 ar_nr_responses[4], // NR1
1225 ar_nr_responses[7], // NT2
1226 ar_nr_responses[8], // AR2
1227 ar_nr_responses[9] // NR2
1228 );
d26849d4 1229 }
1230 uint8_t len = ar_nr_collected*5*4;
1231 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,len,0,&ar_nr_responses,len);
1232 ar_nr_collected = 0;
1233 memset(ar_nr_responses, 0x00, len);
d26849d4 1234 }
1235 }
91c7a7cc 1236 } else if (receivedCmd[0] == 0x1a ) { // ULC authentication
32719adf 1237 }
91c7a7cc 1238 else if (receivedCmd[0] == 0x1b) { // NTAG / EV-1 authentication
32719adf 1239 if ( tagType == 7 ) {
2b1f4228 1240 uint16_t start = 13; //first 4 blocks of emu are [getversion answer - check tearing - pack - 0x00]
1241 uint8_t emdata[4];
1242 emlGetMemBt( emdata, start, 2);
1243 AppendCrc14443a(emdata, 2);
1244 EmSendCmdEx(emdata, sizeof(emdata), false);
1245 p_response = NULL;
ce3d6bd2 1246 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
e98572a1 1247
91c7a7cc 1248 if ( MF_DBGLEVEL >= 3) Dbprintf("Auth attempt: %08x", pwd);
32719adf 1249 }
2b1f4228 1250 } else {
7bc95e2e 1251 // Check for ISO 14443A-4 compliant commands, look at left nibble
1252 switch (receivedCmd[0]) {
7838f4be 1253 case 0x02:
1254 case 0x03: { // IBlock (command no CID)
1255 dynamic_response_info.response[0] = receivedCmd[0];
1256 dynamic_response_info.response[1] = 0x90;
1257 dynamic_response_info.response[2] = 0x00;
1258 dynamic_response_info.response_n = 3;
1259 } break;
7bc95e2e 1260 case 0x0B:
7838f4be 1261 case 0x0A: { // IBlock (command CID)
7bc95e2e 1262 dynamic_response_info.response[0] = receivedCmd[0];
1263 dynamic_response_info.response[1] = 0x00;
1264 dynamic_response_info.response[2] = 0x90;
1265 dynamic_response_info.response[3] = 0x00;
1266 dynamic_response_info.response_n = 4;
1267 } break;
1268
1269 case 0x1A:
1270 case 0x1B: { // Chaining command
1271 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1272 dynamic_response_info.response_n = 2;
1273 } break;
1274
1275 case 0xaa:
1276 case 0xbb: {
1277 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1278 dynamic_response_info.response_n = 2;
1279 } break;
1280
7838f4be 1281 case 0xBA: { // ping / pong
1282 dynamic_response_info.response[0] = 0xAB;
1283 dynamic_response_info.response[1] = 0x00;
1284 dynamic_response_info.response_n = 2;
7bc95e2e 1285 } break;
1286
1287 case 0xCA:
1288 case 0xC2: { // Readers sends deselect command
7838f4be 1289 dynamic_response_info.response[0] = 0xCA;
1290 dynamic_response_info.response[1] = 0x00;
1291 dynamic_response_info.response_n = 2;
7bc95e2e 1292 } break;
1293
1294 default: {
1295 // Never seen this command before
810f5379 1296 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1297 Dbprintf("Received unknown command (len=%d):",len);
1298 Dbhexdump(len,receivedCmd,false);
1299 // Do not respond
1300 dynamic_response_info.response_n = 0;
1301 } break;
1302 }
ce02f6f9 1303
7bc95e2e 1304 if (dynamic_response_info.response_n > 0) {
1305 // Copy the CID from the reader query
1306 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1307
7bc95e2e 1308 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1309 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1310 dynamic_response_info.response_n += 2;
ce02f6f9 1311
7bc95e2e 1312 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1313 Dbprintf("Error preparing tag response");
810f5379 1314 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1315 break;
1316 }
1317 p_response = &dynamic_response_info;
1318 }
81cd0474 1319 }
15c4dc5a 1320
1321 // Count number of wakeups received after a halt
1322 if(order == 6 && lastorder == 5) { happened++; }
1323
1324 // Count number of other messages after a halt
1325 if(order != 6 && lastorder == 5) { happened2++; }
1326
91c7a7cc 1327 // comment this limit if you want to simulation longer
15c4dc5a 1328 if(cmdsRecvd > 999) {
1329 DbpString("1000 commands later...");
254b70a4 1330 break;
15c4dc5a 1331 }
ce02f6f9 1332 cmdsRecvd++;
1333
1334 if (p_response != NULL) {
7bc95e2e 1335 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1336 // do the tracing for the previous reader request and this tag answer:
810f5379 1337 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1338 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1339
7bc95e2e 1340 EmLogTrace(Uart.output,
1341 Uart.len,
1342 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1343 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1344 Uart.parity,
7bc95e2e 1345 p_response->response,
1346 p_response->response_n,
1347 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1348 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1349 par);
7bc95e2e 1350 }
91c7a7cc 1351
1352 // comment this limit if you want to simulation longer
7bc95e2e 1353 if (!tracing) {
1354 Dbprintf("Trace Full. Simulation stopped.");
1355 break;
1356 }
1357 }
15c4dc5a 1358
d26849d4 1359 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 1360 set_tracing(FALSE);
f71f4deb 1361 BigBuf_free_keep_EM();
c9216a92 1362 LED_A_OFF();
1363
0de8e387 1364 if (MF_DBGLEVEL >= 4){
5ee53a0e 1365 Dbprintf("-[ Wake ups after halt [%d]", happened);
1366 Dbprintf("-[ Messages after halt [%d]", happened2);
1367 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
0de8e387 1368 }
15c4dc5a 1369}
1370
9492e0b0 1371
1372// prepare a delayed transfer. This simply shifts ToSend[] by a number
1373// of bits specified in the delay parameter.
1374void PrepareDelayedTransfer(uint16_t delay)
1375{
7504dc50 1376 delay &= 0x07;
1377 if (!delay) return;
1378
9492e0b0 1379 uint8_t bitmask = 0;
1380 uint8_t bits_to_shift = 0;
1381 uint8_t bits_shifted = 0;
7504dc50 1382 uint16_t i = 0;
1383
1384 for (i = 0; i < delay; ++i)
1385 bitmask |= (0x01 << i);
2285d9dd 1386
6fc68747 1387 ToSend[++ToSendMax] = 0x00;
7504dc50 1388
1389 for (i = 0; i < ToSendMax; ++i) {
9492e0b0 1390 bits_to_shift = ToSend[i] & bitmask;
1391 ToSend[i] = ToSend[i] >> delay;
1392 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1393 bits_shifted = bits_to_shift;
1394 }
1395 }
9492e0b0 1396
7bc95e2e 1397
1398//-------------------------------------------------------------------------------------
15c4dc5a 1399// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1400// Parameter timing:
7bc95e2e 1401// if NULL: transfer at next possible time, taking into account
1402// request guard time and frame delay time
1403// if == 0: transfer immediately and return time of transfer
9492e0b0 1404// if != 0: delay transfer until time specified
7bc95e2e 1405//-------------------------------------------------------------------------------------
6a1f2d82 1406static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1407{
9492e0b0 1408 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1409
7bc95e2e 1410 uint32_t ThisTransferTime = 0;
e30c654b 1411
9492e0b0 1412 if (timing) {
ca5bad3d 1413 if(*timing == 0) { // Measure time
7bc95e2e 1414 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
ca5bad3d 1415 } else {
1416 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1417 }
1418 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1419 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
7bc95e2e 1420 LastTimeProxToAirStart = *timing;
1421 } else {
1422 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
7504dc50 1423
7bc95e2e 1424 while(GetCountSspClk() < ThisTransferTime);
7504dc50 1425
7bc95e2e 1426 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1427 }
1428
7bc95e2e 1429 // clear TXRDY
1430 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1431
7bc95e2e 1432 uint16_t c = 0;
9492e0b0 1433 for(;;) {
1434 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1435 AT91C_BASE_SSC->SSC_THR = cmd[c];
4c0cf2d2 1436 ++c;
5ebcb867 1437 if(c >= len)
9492e0b0 1438 break;
9492e0b0 1439 }
1440 }
7bc95e2e 1441
1442 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1443}
1444
7bc95e2e 1445
15c4dc5a 1446//-----------------------------------------------------------------------------
195af472 1447// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1448//-----------------------------------------------------------------------------
6a1f2d82 1449void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1450{
7bc95e2e 1451 int i, j;
5ebcb867 1452 int last = 0;
7bc95e2e 1453 uint8_t b;
e30c654b 1454
7bc95e2e 1455 ToSendReset();
e30c654b 1456
7bc95e2e 1457 // Start of Communication (Seq. Z)
1458 ToSend[++ToSendMax] = SEC_Z;
1459 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
7bc95e2e 1460
1461 size_t bytecount = nbytes(bits);
1462 // Generate send structure for the data bits
1463 for (i = 0; i < bytecount; i++) {
1464 // Get the current byte to send
1465 b = cmd[i];
1466 size_t bitsleft = MIN((bits-(i*8)),8);
1467
1468 for (j = 0; j < bitsleft; j++) {
1469 if (b & 1) {
1470 // Sequence X
1471 ToSend[++ToSendMax] = SEC_X;
1472 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1473 last = 1;
1474 } else {
1475 if (last == 0) {
1476 // Sequence Z
1477 ToSend[++ToSendMax] = SEC_Z;
1478 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1479 } else {
1480 // Sequence Y
1481 ToSend[++ToSendMax] = SEC_Y;
1482 last = 0;
1483 }
1484 }
1485 b >>= 1;
1486 }
1487
6a1f2d82 1488 // Only transmit parity bit if we transmitted a complete byte
0ec548dc 1489 if (j == 8 && parity != NULL) {
7bc95e2e 1490 // Get the parity bit
6a1f2d82 1491 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1492 // Sequence X
1493 ToSend[++ToSendMax] = SEC_X;
1494 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1495 last = 1;
1496 } else {
1497 if (last == 0) {
1498 // Sequence Z
1499 ToSend[++ToSendMax] = SEC_Z;
1500 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1501 } else {
1502 // Sequence Y
1503 ToSend[++ToSendMax] = SEC_Y;
1504 last = 0;
1505 }
1506 }
1507 }
1508 }
e30c654b 1509
7bc95e2e 1510 // End of Communication: Logic 0 followed by Sequence Y
1511 if (last == 0) {
1512 // Sequence Z
1513 ToSend[++ToSendMax] = SEC_Z;
1514 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1515 } else {
1516 // Sequence Y
1517 ToSend[++ToSendMax] = SEC_Y;
1518 last = 0;
1519 }
1520 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1521
7bc95e2e 1522 // Convert to length of command:
4b78d6b3 1523 ++ToSendMax;
15c4dc5a 1524}
1525
195af472 1526//-----------------------------------------------------------------------------
1527// Prepare reader command to send to FPGA
1528//-----------------------------------------------------------------------------
6a1f2d82 1529void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
195af472 1530{
ca5bad3d 1531 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1532}
1533
0c8d25eb 1534
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1535//-----------------------------------------------------------------------------
1536// Wait for commands from reader
1537// Stop when button is pressed (return 1) or field was gone (return 2)
1538// Or return 0 when command is captured
1539//-----------------------------------------------------------------------------
6a1f2d82 1540static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
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1541{
1542 *len = 0;
1543
1544 uint32_t timer = 0, vtime = 0;
1545 int analogCnt = 0;
1546 int analogAVG = 0;
1547
1548 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1549 // only, since we are receiving, not transmitting).
1550 // Signal field is off with the appropriate LED
1551 LED_D_OFF();
1552 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1553
1554 // Set ADC to read field strength
1555 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1556 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1557 ADC_MODE_PRESCALE(63) |
1558 ADC_MODE_STARTUP_TIME(1) |
1559 ADC_MODE_SAMPLE_HOLD_TIME(15);
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1560 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1561 // start ADC
1562 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1563
1564 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1565 UartInit(received, parity);
7bc95e2e 1566
1567 // Clear RXRDY:
1568 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1569
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1570 for(;;) {
1571 WDT_HIT();
1572
1573 if (BUTTON_PRESS()) return 1;
1574
1575 // test if the field exists
1576 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1577 analogCnt++;
1578 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1579 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1580 if (analogCnt >= 32) {
0c8d25eb 1581 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
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1582 vtime = GetTickCount();
1583 if (!timer) timer = vtime;
1584 // 50ms no field --> card to idle state
1585 if (vtime - timer > 50) return 2;
1586 } else
1587 if (timer) timer = 0;
1588 analogCnt = 0;
1589 analogAVG = 0;
1590 }
1591 }
7bc95e2e 1592
9ca155ba 1593 // receive and test the miller decoding
7bc95e2e 1594 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1595 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1596 if(MillerDecoding(b, 0)) {
1597 *len = Uart.len;
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1598 return 0;
1599 }
7bc95e2e 1600 }
1601
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1602 }
1603}
1604
9ca155ba 1605
6a1f2d82 1606static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
7bc95e2e 1607{
1608 uint8_t b;
1609 uint16_t i = 0;
1610 uint32_t ThisTransferTime;
1611
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1612 // Modulate Manchester
1613 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1614
1615 // include correction bit if necessary
1616 if (Uart.parityBits & 0x01) {
1617 correctionNeeded = TRUE;
1618 }
1619 if(correctionNeeded) {
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1620 // 1236, so correction bit needed
1621 i = 0;
7bc95e2e 1622 } else {
1623 i = 1;
9ca155ba 1624 }
7bc95e2e 1625
d714d3ef 1626 // clear receiving shift register and holding register
7bc95e2e 1627 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1628 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1629 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1630 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1631
7bc95e2e 1632 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1633 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1634 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1635 if (AT91C_BASE_SSC->SSC_RHR) break;
1636 }
1637
1638 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1639
1640 // Clear TXRDY:
1641 AT91C_BASE_SSC->SSC_THR = SEC_F;
1642
9ca155ba 1643 // send cycle
bb42a03e 1644 for(; i < respLen; ) {
9ca155ba 1645 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1646 AT91C_BASE_SSC->SSC_THR = resp[i++];
1647 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1648 }
7bc95e2e 1649
17ad0e09 1650 if(BUTTON_PRESS()) break;
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1651 }
1652
7bc95e2e 1653 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
4b78d6b3 1654 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3; // twich /8 ?? >>3,
0c8d25eb 1655 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
7bc95e2e 1656 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1657 AT91C_BASE_SSC->SSC_THR = SEC_F;
1658 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1659 i++;
1660 }
1661 }
0c8d25eb 1662
7bc95e2e 1663 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1664
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1665 return 0;
1666}
1667
7bc95e2e 1668int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1669 Code4bitAnswerAsTag(resp);
0a39986e 1670 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1671 // do the tracing for the previous reader request and this tag answer:
5ebcb867 1672 uint8_t par[1] = {0x00};
6a1f2d82 1673 GetParity(&resp, 1, par);
7bc95e2e 1674 EmLogTrace(Uart.output,
1675 Uart.len,
1676 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1677 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1678 Uart.parity,
7bc95e2e 1679 &resp,
1680 1,
1681 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1682 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1683 par);
0a39986e 1684 return res;
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1685}
1686
8f51ddb0 1687int EmSend4bit(uint8_t resp){
7bc95e2e 1688 return EmSend4bitEx(resp, false);
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1689}
1690
6a1f2d82 1691int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1692 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1693 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1694 // do the tracing for the previous reader request and this tag answer:
1695 EmLogTrace(Uart.output,
1696 Uart.len,
1697 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1698 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1699 Uart.parity,
7bc95e2e 1700 resp,
1701 respLen,
1702 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1703 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1704 par);
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1705 return res;
1706}
1707
6a1f2d82 1708int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
5ebcb867 1709 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1710 GetParity(resp, respLen, par);
1711 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
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1712}
1713
6a1f2d82 1714int EmSendCmd(uint8_t *resp, uint16_t respLen){
5ebcb867 1715 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1716 GetParity(resp, respLen, par);
1717 return EmSendCmdExPar(resp, respLen, false, par);
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1718}
1719
6a1f2d82 1720int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1721 return EmSendCmdExPar(resp, respLen, false, par);
1722}
1723
6a1f2d82 1724bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1725 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1726{
810f5379 1727 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1728 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1729 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1730 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1731 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1732 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1733 reader_EndTime = tag_StartTime - exact_fdt;
1734 reader_StartTime = reader_EndTime - reader_modlen;
5ebcb867 1735
810f5379 1736 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE))
1737 return FALSE;
1738 else
1739 return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1740
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1741}
1742
15c4dc5a 1743//-----------------------------------------------------------------------------
1744// Wait a certain time for tag response
1745// If a response is captured return TRUE
e691fc45 1746// If it takes too long return FALSE
15c4dc5a 1747//-----------------------------------------------------------------------------
6a1f2d82 1748static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1749{
46c65fed 1750 uint32_t c = 0x00;
e691fc45 1751
15c4dc5a 1752 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1753 // only, since we are receiving, not transmitting).
1754 // Signal field is on with the appropriate LED
1755 LED_D_ON();
1756 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1757
534983d7 1758 // Now get the answer from the card
6a1f2d82 1759 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1760
7bc95e2e 1761 // clear RXRDY:
1762 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1763
15c4dc5a 1764 for(;;) {
534983d7 1765 WDT_HIT();
15c4dc5a 1766
534983d7 1767 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1768 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1769 if(ManchesterDecoding(b, offset, 0)) {
1770 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1771 return TRUE;
19a700a8 1772 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
7bc95e2e 1773 return FALSE;
15c4dc5a 1774 }
534983d7 1775 }
1776 }
15c4dc5a 1777}
1778
6a1f2d82 1779void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1780{
6a1f2d82 1781 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1782
7bc95e2e 1783 // Send command to tag
1784 TransmitFor14443a(ToSend, ToSendMax, timing);
1785 if(trigger)
1786 LED_A_ON();
dfc3c505 1787
7bc95e2e 1788 // Log reader command in trace buffer
4b78d6b3 1789 //LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1790 LogTrace(frame, nbytes(bits), (LastTimeProxToAirStart<<4) + DELAY_ARM2AIR_AS_READER, ((LastTimeProxToAirStart + LastProxToAirDuration)<<4) + DELAY_ARM2AIR_AS_READER, par, TRUE);
15c4dc5a 1791}
1792
6a1f2d82 1793void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1794{
ca5bad3d 1795 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1796}
15c4dc5a 1797
6a1f2d82 1798void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1799{
1800 // Generate parity and redirect
5ebcb867 1801 uint8_t par[MAX_PARITY_SIZE] = {0x00};
ca5bad3d 1802 GetParity(frame, len/8, par);
6a1f2d82 1803 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1804}
1805
6a1f2d82 1806void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1807{
1808 // Generate parity and redirect
5ebcb867 1809 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1810 GetParity(frame, len, par);
ca5bad3d 1811 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1812}
1813
6a1f2d82 1814int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1815{
ca5bad3d 1816 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
1817 //if (tracing) {
1818 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1819 //}
e691fc45 1820 return Demod.len;
1821}
1822
91c7a7cc 1823int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity) {
ca5bad3d 1824 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
1825 //if (tracing) {
91c7a7cc 1826 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
ca5bad3d 1827 //}
e691fc45 1828 return Demod.len;
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1829}
1830
c188b1b9 1831// performs iso14443a anticollision (optional) and card select procedure
1832// fills the uid and cuid pointer unless NULL
1833// fills the card info record unless NULL
1834// if anticollision is false, then the UID must be provided in uid_ptr[]
1835// and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1836int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades) {
6a1f2d82 1837 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1838 uint8_t sel_all[] = { 0x93,0x20 };
1839 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1840 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
4c0cf2d2 1841 uint8_t resp[MAX_FRAME_SIZE] = {0}; // theoretically. A usual RATS will be much smaller
1842 uint8_t resp_par[MAX_PARITY_SIZE] = {0};
1843 byte_t uid_resp[4] = {0};
1844 size_t uid_resp_len = 0;
6a1f2d82 1845
1846 uint8_t sak = 0x04; // cascade uid
1847 int cascade_level = 0;
1848 int len;
1849
1850 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
c188b1b9 1851 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
7bc95e2e 1852
6a1f2d82 1853 // Receive the ATQA
1854 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1855
1856 if(p_hi14a_card) {
1857 memcpy(p_hi14a_card->atqa, resp, 2);
1858 p_hi14a_card->uidlen = 0;
1859 memset(p_hi14a_card->uid,0,10);
1860 }
5f6d6c90 1861
c188b1b9 1862 if (anticollision) {
4c0cf2d2 1863 // clear uid
1864 if (uid_ptr)
1865 memset(uid_ptr,0,10);
c188b1b9 1866 }
79a73ab2 1867
0ec548dc 1868 // check for proprietary anticollision:
4c0cf2d2 1869 if ((resp[0] & 0x1F) == 0) return 3;
0ec548dc 1870
6a1f2d82 1871 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1872 // which case we need to make a cascade 2 request and select - this is a long UID
1873 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1874 for(; sak & 0x04; cascade_level++) {
1875 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1876 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1877
c188b1b9 1878 if (anticollision) {
6a1f2d82 1879 // SELECT_ALL
4c0cf2d2 1880 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1881 if (!ReaderReceive(resp, resp_par)) return 0;
1882
1883 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1884 memset(uid_resp, 0, 4);
1885 uint16_t uid_resp_bits = 0;
1886 uint16_t collision_answer_offset = 0;
1887 // anti-collision-loop:
1888 while (Demod.collisionPos) {
1889 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1890 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1891 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1892 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1893 }
1894 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1895 uid_resp_bits++;
1896 // construct anticollosion command:
1897 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1898 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1899 sel_uid[2+i] = uid_resp[i];
1900 }
1901 collision_answer_offset = uid_resp_bits%8;
1902 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1903 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
6a1f2d82 1904 }
4c0cf2d2 1905 // finally, add the last bits and BCC of the UID
1906 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1907 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1908 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1909 }
e691fc45 1910
4c0cf2d2 1911 } else { // no collision, use the response to SELECT_ALL as current uid
1912 memcpy(uid_resp, resp, 4);
1913 }
1914
c188b1b9 1915 } else {
1916 if (cascade_level < num_cascades - 1) {
1917 uid_resp[0] = 0x88;
1918 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1919 } else {
1920 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1921 }
1922 }
6a1f2d82 1923 uid_resp_len = 4;
5f6d6c90 1924
6a1f2d82 1925 // calculate crypto UID. Always use last 4 Bytes.
4c0cf2d2 1926 if(cuid_ptr)
6a1f2d82 1927 *cuid_ptr = bytes_to_num(uid_resp, 4);
e30c654b 1928
6a1f2d82 1929 // Construct SELECT UID command
1930 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
c188b1b9 1931 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
6a1f2d82 1932 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1933 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1934 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1935
1936 // Receive the SAK
1937 if (!ReaderReceive(resp, resp_par)) return 0;
4c0cf2d2 1938
6a1f2d82 1939 sak = resp[0];
1940
810f5379 1941 // Test if more parts of the uid are coming
6a1f2d82 1942 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1943 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1944 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1945 uid_resp[0] = uid_resp[1];
1946 uid_resp[1] = uid_resp[2];
1947 uid_resp[2] = uid_resp[3];
6a1f2d82 1948 uid_resp_len = 3;
1949 }
5f6d6c90 1950
4c0cf2d2 1951 if(uid_ptr && anticollision)
6a1f2d82 1952 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
5f6d6c90 1953
6a1f2d82 1954 if(p_hi14a_card) {
1955 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1956 p_hi14a_card->uidlen += uid_resp_len;
1957 }
1958 }
79a73ab2 1959
6a1f2d82 1960 if(p_hi14a_card) {
1961 p_hi14a_card->sak = sak;
1962 p_hi14a_card->ats_len = 0;
1963 }
534983d7 1964
3fe4ff4f 1965 // non iso14443a compliant tag
1966 if( (sak & 0x20) == 0) return 2;
534983d7 1967
6a1f2d82 1968 // Request for answer to select
1969 AppendCrc14443a(rats, 2);
1970 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1971
6a1f2d82 1972 if (!(len = ReaderReceive(resp, resp_par))) return 0;
3fe4ff4f 1973
6a1f2d82 1974 if(p_hi14a_card) {
1975 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1976 p_hi14a_card->ats_len = len;
1977 }
5f6d6c90 1978
6a1f2d82 1979 // reset the PCB block number
1980 iso14_pcb_blocknum = 0;
19a700a8 1981
1982 // set default timeout based on ATS
1983 iso14a_set_ATS_timeout(resp);
1984
6a1f2d82 1985 return 1;
7e758047 1986}
15c4dc5a 1987
7bc95e2e 1988void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1989 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1990 // Set up the synchronous serial port
1991 FpgaSetupSsc();
7bc95e2e 1992 // connect Demodulated Signal to ADC:
7e758047 1993 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
91c7a7cc 1994
1995 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
ca5bad3d 1996
1997 LED_D_OFF();
7e758047 1998 // Signal field is on with the appropriate LED
ca5bad3d 1999 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD ||
2000 fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN)
7bc95e2e 2001 LED_D_ON();
6fc68747 2002
91c7a7cc 2003 // Prepare the demodulation functions
7bc95e2e 2004 DemodReset();
2005 UartReset();
6fc68747 2006
46c65fed 2007 iso14a_set_timeout(10*106); // 10ms default
91c7a7cc 2008
2009 //NextTransferTime = 2 * DELAY_ARM2AIR_AS_READER;
2010 NextTransferTime = DELAY_ARM2AIR_AS_READER << 1;
6fc68747 2011
2012 // Start the timer
2013 StartCountSspClk();
7e758047 2014}
15c4dc5a 2015
6a1f2d82 2016int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
810f5379 2017 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
534983d7 2018 uint8_t real_cmd[cmd_len+4];
2019 real_cmd[0] = 0x0a; //I-Block
b0127e65 2020 // put block number into the PCB
2021 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 2022 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
2023 memcpy(real_cmd+2, cmd, cmd_len);
2024 AppendCrc14443a(real_cmd,cmd_len+2);
2025
9492e0b0 2026 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 2027 size_t len = ReaderReceive(data, parity);
ca5bad3d 2028 //DATA LINK ERROR
2029 if (!len) return 0;
2030
6a1f2d82 2031 uint8_t *data_bytes = (uint8_t *) data;
ca5bad3d 2032
b0127e65 2033 // if we received an I- or R(ACK)-Block with a block number equal to the
2034 // current block number, toggle the current block number
ca5bad3d 2035 if (len >= 4 // PCB+CID+CRC = 4 bytes
b0127e65 2036 && ((data_bytes[0] & 0xC0) == 0 // I-Block
2037 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2038 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
2039 {
2040 iso14_pcb_blocknum ^= 1;
2041 }
2042
534983d7 2043 return len;
2044}
2045
7e758047 2046//-----------------------------------------------------------------------------
2047// Read an ISO 14443a tag. Send out commands and store answers.
2048//
2049//-----------------------------------------------------------------------------
91c7a7cc 2050void ReaderIso14443a(UsbCommand *c) {
534983d7 2051 iso14a_command_t param = c->arg[0];
04bc1c66 2052 size_t len = c->arg[1] & 0xffff;
2053 size_t lenbits = c->arg[1] >> 16;
2054 uint32_t timeout = c->arg[2];
91c7a7cc 2055 uint8_t *cmd = c->d.asBytes;
9492e0b0 2056 uint32_t arg0 = 0;
810f5379 2057 byte_t buf[USB_CMD_DATA_SIZE] = {0x00};
2058 uint8_t par[MAX_PARITY_SIZE] = {0x00};
902cb3c0 2059
810f5379 2060 if (param & ISO14A_CONNECT)
3000dc4e 2061 clear_trace();
e691fc45 2062
3000dc4e 2063 set_tracing(TRUE);
e30c654b 2064
810f5379 2065 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 2066 iso14a_set_trigger(TRUE);
15c4dc5a 2067
810f5379 2068 if (param & ISO14A_CONNECT) {
7bc95e2e 2069 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 2070 if(!(param & ISO14A_NO_SELECT)) {
2071 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
c188b1b9 2072 arg0 = iso14443a_select_card(NULL,card,NULL, true, 0);
91c7a7cc 2073 cmd_send(CMD_ACK, arg0, card->uidlen, 0, buf, sizeof(iso14a_card_select_t));
6fc68747 2074 // if it fails, the cmdhf14a.c client quites.. however this one still executes.
2075 if ( arg0 == 0 ) return;
5f6d6c90 2076 }
534983d7 2077 }
e30c654b 2078
810f5379 2079 if (param & ISO14A_SET_TIMEOUT)
04bc1c66 2080 iso14a_set_timeout(timeout);
e30c654b 2081
810f5379 2082 if (param & ISO14A_APDU) {
902cb3c0 2083 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 2084 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2085 }
e30c654b 2086
810f5379 2087 if (param & ISO14A_RAW) {
534983d7 2088 if(param & ISO14A_APPEND_CRC) {
0ec548dc 2089 if(param & ISO14A_TOPAZMODE) {
2090 AppendCrc14443b(cmd,len);
2091 } else {
d26849d4 2092 AppendCrc14443a(cmd,len);
0ec548dc 2093 }
534983d7 2094 len += 2;
c7324bef 2095 if (lenbits) lenbits += 16;
15c4dc5a 2096 }
0ec548dc 2097 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2098 if(param & ISO14A_TOPAZMODE) {
2099 int bits_to_send = lenbits;
2100 uint16_t i = 0;
2101 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2102 bits_to_send -= 7;
2103 while (bits_to_send > 0) {
2104 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2105 bits_to_send -= 8;
2106 }
2107 } else {
6a1f2d82 2108 GetParity(cmd, lenbits/8, par);
0ec548dc 2109 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2110 }
2111 } else { // want to send complete bytes only
2112 if(param & ISO14A_TOPAZMODE) {
2113 uint16_t i = 0;
2114 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2115 while (i < len) {
2116 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2117 }
5f6d6c90 2118 } else {
0ec548dc 2119 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2120 }
5f6d6c90 2121 }
6a1f2d82 2122 arg0 = ReaderReceive(buf, par);
9492e0b0 2123 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2124 }
15c4dc5a 2125
810f5379 2126 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 2127 iso14a_set_trigger(FALSE);
15c4dc5a 2128
810f5379 2129 if (param & ISO14A_NO_DISCONNECT)
534983d7 2130 return;
15c4dc5a 2131
15c4dc5a 2132 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 2133 set_tracing(FALSE);
15c4dc5a 2134 LEDsoff();
15c4dc5a 2135}
b0127e65 2136
1c611bbd 2137
1c611bbd 2138// Determine the distance between two nonces.
2139// Assume that the difference is small, but we don't know which is first.
2140// Therefore try in alternating directions.
2141int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2142
ca5bad3d 2143 if (nt1 == nt2) return 0;
ca5bad3d 2144
91c7a7cc 2145 uint16_t i;
2146 uint32_t nttmp1 = nt1;
2147 uint32_t nttmp2 = nt2;
2148
2149 for (i = 1; i < 32768; ++i) {
ca5bad3d 2150 nttmp1 = prng_successor(nttmp1, 1);
2151 if (nttmp1 == nt2) return i;
2152 nttmp2 = prng_successor(nttmp2, 1);
2153 if (nttmp2 == nt1) return -i;
91c7a7cc 2154 }
2155 // either nt1 or nt2 are invalid nonces
2156 return(-99999);
e772353f 2157}
2158
e772353f 2159
1c611bbd 2160//-----------------------------------------------------------------------------
2161// Recover several bits of the cypher stream. This implements (first stages of)
2162// the algorithm described in "The Dark Side of Security by Obscurity and
2163// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2164// (article by Nicolas T. Courtois, 2009)
2165//-----------------------------------------------------------------------------
91c7a7cc 2166void ReaderMifare(bool first_try, uint8_t block ) {
c830303d 2167 // Mifare AUTH
810f5379 2168 //uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2169 //uint8_t mf_auth[] = { 0x60,0x05, 0x58, 0x2c };
91c7a7cc 2170 uint8_t mf_auth[] = { MIFARE_AUTH_KEYA, block, 0x00, 0x00 };
b0300679 2171 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2172 uint8_t uid[10] = {0,0,0,0,0,0,0,0,0,0};
2173 uint8_t par_list[8] = {0,0,0,0,0,0,0,0};
2174 uint8_t ks_list[8] = {0,0,0,0,0,0,0,0};
495d7f13 2175 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = {0x00};
2176 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b0300679 2177 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2178 byte_t nt_diff = 0;
6a1f2d82 2179 uint32_t nt = 0;
b0300679 2180 uint32_t previous_nt = 0;
b0300679 2181 uint32_t cuid = 0;
2182
91c7a7cc 2183 int32_t catch_up_cycles = 0;
2184 int32_t last_catch_up = 0;
2185 int32_t isOK = 0;
2186 int32_t nt_distance = 0;
b0300679 2187
4c0cf2d2 2188 uint16_t elapsed_prng_sequences = 1;
1c611bbd 2189 uint16_t consecutive_resyncs = 0;
0de8e387 2190 uint16_t unexpected_random = 0;
2191 uint16_t sync_tries = 0;
b0300679 2192
91c7a7cc 2193 // static variables here, is re-used in the next call?
b0300679 2194 static uint32_t nt_attacked = 0;
2195 static uint32_t sync_time = 0;
91c7a7cc 2196 static uint32_t sync_cycles = 0;
b0300679 2197 static uint8_t par_low = 0;
2198 static uint8_t mf_nr_ar3 = 0;
91c7a7cc 2199
b0300679 2200 #define PRNG_SEQUENCE_LENGTH (1 << 16)
2201 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2202 #define MAX_SYNC_TRIES 32
2203 #define MAX_STRATEGY 3
4c0cf2d2 2204
91c7a7cc 2205 BigBuf_free(); BigBuf_Clear_ext(false);
4b78d6b3 2206 clear_trace();
91c7a7cc 2207 set_tracing(TRUE);
2208 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
4c0cf2d2 2209
91c7a7cc 2210 AppendCrc14443a(mf_auth, 2);
2211
4c0cf2d2 2212 if (first_try) {
2213 sync_time = GetCountSspClk() & 0xfffffff8;
91c7a7cc 2214 sync_cycles = PRNG_SEQUENCE_LENGTH + 1130; //65536; //0x10000 // Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
4c0cf2d2 2215 mf_nr_ar3 = 0;
2216 nt_attacked = 0;
91c7a7cc 2217 par_low = 0;
b0300679 2218
91c7a7cc 2219 Dbprintf("FIRST: sync_time - %08X", sync_time);
4c0cf2d2 2220 } else {
b0300679 2221 // we were unsuccessful on a previous call.
2222 // Try another READER nonce (first 3 parity bits remain the same)
2223 ++mf_nr_ar3;
4c0cf2d2 2224 mf_nr_ar[3] = mf_nr_ar3;
2225 par[0] = par_low;
2226 }
91c7a7cc 2227
2228 bool have_uid = FALSE;
2229 uint8_t cascade_levels = 0;
2230
4c0cf2d2 2231 LED_C_ON();
91c7a7cc 2232 uint16_t i;
2233 for(i = 0; TRUE; ++i) {
4c0cf2d2 2234
1c611bbd 2235 WDT_HIT();
e30c654b 2236
1c611bbd 2237 // Test if the action was cancelled
c830303d 2238 if(BUTTON_PRESS()) {
2239 isOK = -1;
1c611bbd 2240 break;
2241 }
2242
91c7a7cc 2243 // this part is from Piwi's faster nonce collecting part in Hardnested.
2244 if (!have_uid) { // need a full select cycle to get the uid first
2245 iso14a_card_select_t card_info;
2246 if(!iso14443a_select_card(uid, &card_info, &cuid, true, 0)) {
2247 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (ALL)");
2248 break;
2249 }
2250 switch (card_info.uidlen) {
2251 case 4 : cascade_levels = 1; break;
2252 case 7 : cascade_levels = 2; break;
2253 case 10: cascade_levels = 3; break;
2254 default: break;
2255 }
2256 have_uid = TRUE;
2257 } else { // no need for anticollision. We can directly select the card
2258 if(!iso14443a_select_card(uid, NULL, &cuid, false, cascade_levels)) {
2259 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (UID)");
2260 continue;
2261 }
1c611bbd 2262 }
4c0cf2d2 2263
91c7a7cc 2264 // Sending timeslot of ISO14443a frame
2265 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles + catch_up_cycles;
4b78d6b3 2266 catch_up_cycles = 0;
2267
2268 // if we missed the sync time already, advance to the next nonce repeat
91c7a7cc 2269 while( GetCountSspClk() > sync_time) {
4b78d6b3 2270 ++elapsed_prng_sequences;
91c7a7cc 2271 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles;
2272 }
2273
2274 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2275 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2276
91c7a7cc 2277 // Receive the (4 Byte) "random" nonce from TAG
4c0cf2d2 2278 if (!ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2279 continue;
1c611bbd 2280
4b78d6b3 2281 previous_nt = nt;
2282 nt = bytes_to_num(receivedAnswer, 4);
2283
91c7a7cc 2284 // Transmit reader nonce with fake par
2285 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2286
2287 WDT_HIT();
2288 LED_B_ON();
1c611bbd 2289 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
91c7a7cc 2290
2291 nt_distance = dist_nt(previous_nt, nt);
2292
2293 // if no distance between, then we are in sync.
1c611bbd 2294 if (nt_distance == 0) {
2295 nt_attacked = nt;
0de8e387 2296 } else {
c830303d 2297 if (nt_distance == -99999) { // invalid nonce received
91c7a7cc 2298 ++unexpected_random;
3bc7b13d 2299 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
c830303d 2300 isOK = -3; // Card has an unpredictable PRNG. Give up
2301 break;
91c7a7cc 2302 } else {
2303 if (sync_cycles <= 0) sync_cycles += PRNG_SEQUENCE_LENGTH;
2304 LED_B_OFF();
c830303d 2305 continue; // continue trying...
2306 }
1c611bbd 2307 }
4c0cf2d2 2308
0de8e387 2309 if (++sync_tries > MAX_SYNC_TRIES) {
91c7a7cc 2310 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2311 break;
0de8e387 2312 }
4c0cf2d2 2313
4b78d6b3 2314 sync_cycles = (sync_cycles - nt_distance)/elapsed_prng_sequences;
91c7a7cc 2315
4c0cf2d2 2316 if (sync_cycles <= 0)
0de8e387 2317 sync_cycles += PRNG_SEQUENCE_LENGTH;
4c0cf2d2 2318
91c7a7cc 2319 if (MF_DBGLEVEL >= 4)
3bc7b13d 2320 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
4c0cf2d2 2321
91c7a7cc 2322 LED_B_OFF();
1c611bbd 2323 continue;
2324 }
2325 }
91c7a7cc 2326 LED_B_OFF();
1c611bbd 2327
2328 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
4c0cf2d2 2329
91c7a7cc 2330 catch_up_cycles = ABS(dist_nt(nt_attacked, nt));
c830303d 2331 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
1c611bbd 2332 catch_up_cycles = 0;
2333 continue;
91c7a7cc 2334 }
4c0cf2d2 2335 // average?
3bc7b13d 2336 catch_up_cycles /= elapsed_prng_sequences;
4c0cf2d2 2337
1c611bbd 2338 if (catch_up_cycles == last_catch_up) {
4a71da5a 2339 ++consecutive_resyncs;
4c0cf2d2 2340 } else {
1c611bbd 2341 last_catch_up = catch_up_cycles;
2342 consecutive_resyncs = 0;
4b78d6b3 2343 }
4c0cf2d2 2344
1c611bbd 2345 if (consecutive_resyncs < 3) {
91c7a7cc 2346 if (MF_DBGLEVEL >= 4)
2347 Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, catch_up_cycles, consecutive_resyncs);
4c0cf2d2 2348 } else {
2349 sync_cycles += catch_up_cycles;
2350
91c7a7cc 2351 if (MF_DBGLEVEL >= 4)
2352 Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, catch_up_cycles, sync_cycles);
4c0cf2d2 2353
3bc7b13d 2354 last_catch_up = 0;
2355 catch_up_cycles = 0;
2356 consecutive_resyncs = 0;
1c611bbd 2357 }
2358 continue;
2359 }
2360
1c611bbd 2361 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
91c7a7cc 2362 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2363 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2364
495d7f13 2365 if (nt_diff == 0)
6a1f2d82 2366 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2367
6a1f2d82 2368 par_list[nt_diff] = SwapBits(par[0], 8);
91c7a7cc 2369 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; // xor with NACK value to get keystream
1c611bbd 2370
2371 // Test if the information is complete
2372 if (nt_diff == 0x07) {
2373 isOK = 1;
2374 break;
2375 }
2376
2377 nt_diff = (nt_diff + 1) & 0x07;
2378 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2379 par[0] = par_low;
4b78d6b3 2380
1c611bbd 2381 } else {
b0300679 2382 // No NACK.
495d7f13 2383 if (nt_diff == 0 && first_try) {
6a1f2d82 2384 par[0]++;
5ebcb867 2385 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
c830303d 2386 isOK = -2;
2387 break;
2388 }
1c611bbd 2389 } else {
b0300679 2390 // Why this?
6a1f2d82 2391 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2392 }
2393 }
4b78d6b3 2394
91c7a7cc 2395 // reset the resyncs since we got a complete transaction on right time.
4b78d6b3 2396 consecutive_resyncs = 0;
91c7a7cc 2397 } // end for loop
1c611bbd 2398
1c611bbd 2399 mf_nr_ar[3] &= 0x1F;
5ebcb867 2400
91c7a7cc 2401 if (MF_DBGLEVEL >= 1) Dbprintf("\nNumber of sent auth requestes: %u", i);
d26849d4 2402
b0300679 2403 uint8_t buf[28] = {0x00};
91c7a7cc 2404 memset(buf, 0x00, sizeof(buf));
b0300679 2405 num_to_bytes(cuid, 4, buf);
1c611bbd 2406 num_to_bytes(nt, 4, buf + 4);
2407 memcpy(buf + 8, par_list, 8);
2408 memcpy(buf + 16, ks_list, 8);
2409 memcpy(buf + 24, mf_nr_ar, 4);
2410
91c7a7cc 2411 cmd_send(CMD_ACK, isOK, 0, 0, buf, sizeof(buf) );
1c611bbd 2412
1c611bbd 2413 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2414 LEDsoff();
99cf19d9 2415 set_tracing(FALSE);
20f9a2a1 2416}
1c611bbd 2417
0de8e387 2418/**
d2f487af 2419 *MIFARE 1K simulate.
2420 *
2421 *@param flags :
2422 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2423 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2424 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2425 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2426 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2427 */
91c7a7cc 2428void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain) {
50193c1e 2429 int cardSTATE = MFEMUL_NOFIELD;
8556b852 2430 int _7BUID = 0;
9ca155ba 2431 int vHf = 0; // in mV
8f51ddb0 2432 int res;
0a39986e
M
2433 uint32_t selTimer = 0;
2434 uint32_t authTimer = 0;
6a1f2d82 2435 uint16_t len = 0;
8f51ddb0 2436 uint8_t cardWRBL = 0;
9ca155ba
M
2437 uint8_t cardAUTHSC = 0;
2438 uint8_t cardAUTHKEY = 0xff; // no authentication
c3c241f3 2439// uint32_t cardRr = 0;
9ca155ba 2440 uint32_t cuid = 0;
d2f487af 2441 //uint32_t rn_enc = 0;
51969283 2442 uint32_t ans = 0;
0014cb46
M
2443 uint32_t cardINTREG = 0;
2444 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2445 struct Crypto1State mpcs = {0, 0};
2446 struct Crypto1State *pcs;
2447 pcs = &mpcs;
d2f487af 2448 uint32_t numReads = 0;//Counts numer of times reader read a block
5ebcb867 2449 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2450 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2451 uint8_t response[MAX_MIFARE_FRAME_SIZE] = {0x00};
2452 uint8_t response_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
9ca155ba 2453
d2f487af 2454 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2455 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2456 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
94422fa2 2457 uint8_t rSAK[] = {0x08, 0xb6, 0xdd}; // Mifare Classic
2458 //uint8_t rSAK[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
d2f487af 2459 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
9ca155ba 2460
02a40596 2461 //uint8_t rAUTH_NT[] = {0x01, 0x01, 0x01, 0x01};
2462 uint8_t rAUTH_NT[] = {0x55, 0x41, 0x49, 0x92};
d2f487af 2463 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
7bc95e2e 2464
2b1f4228 2465 //Here, we collect UID1,UID2,NT,AR,NR,0,0,NT2,AR2,NR2
d2f487af 2466 // This can be used in a reader-only attack.
2467 // (it can also be retrieved via 'hf 14a list', but hey...
c3c241f3 2468 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
d2f487af 2469 uint8_t ar_nr_collected = 0;
0014cb46 2470
7bc95e2e 2471 // Authenticate response - nonce
51969283 2472 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
7bc95e2e 2473
d2f487af 2474 //-- Determine the UID
2475 // Can be set from emulator memory, incoming data
2476 // and can be 7 or 4 bytes long
7bc95e2e 2477 if (flags & FLAG_4B_UID_IN_DATA)
d2f487af 2478 {
2479 // 4B uid comes from data-portion of packet
2480 memcpy(rUIDBCC1,datain,4);
8556b852 2481 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
8556b852 2482
7bc95e2e 2483 } else if (flags & FLAG_7B_UID_IN_DATA) {
d2f487af 2484 // 7B uid comes from data-portion of packet
2485 memcpy(&rUIDBCC1[1],datain,3);
2486 memcpy(rUIDBCC2, datain+3, 4);
2487 _7BUID = true;
7bc95e2e 2488 } else {
d2f487af 2489 // get UID from emul memory
2490 emlGetMemBt(receivedCmd, 7, 1);
2491 _7BUID = !(receivedCmd[0] == 0x00);
2492 if (!_7BUID) { // ---------- 4BUID
2493 emlGetMemBt(rUIDBCC1, 0, 4);
2494 } else { // ---------- 7BUID
2495 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2496 emlGetMemBt(rUIDBCC2, 3, 4);
2497 }
2498 }
7bc95e2e 2499
c3c241f3 2500 // save uid.
2501 ar_nr_responses[0*5] = bytes_to_num(rUIDBCC1+1, 3);
2502 if ( _7BUID )
2503 ar_nr_responses[0*5+1] = bytes_to_num(rUIDBCC2, 4);
2504
d2f487af 2505 /*
2506 * Regardless of what method was used to set the UID, set fifth byte and modify
2507 * the ATQA for 4 or 7-byte UID
2508 */
d2f487af 2509 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
7bc95e2e 2510 if (_7BUID) {
d2f487af 2511 rATQA[0] = 0x44;
8556b852 2512 rUIDBCC1[0] = 0x88;
d26849d4 2513 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
8556b852
M
2514 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2515 }
2516
d2f487af 2517 if (MF_DBGLEVEL >= 1) {
2518 if (!_7BUID) {
b03c0f2d 2519 Dbprintf("4B UID: %02x%02x%02x%02x",
2520 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
7bc95e2e 2521 } else {
b03c0f2d 2522 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2523 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2524 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
d2f487af 2525 }
2526 }
7bc95e2e 2527
99cf19d9 2528 // We need to listen to the high-frequency, peak-detected path.
2529 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2530
2531 // free eventually allocated BigBuf memory but keep Emulator Memory
2532 BigBuf_free_keep_EM();
2533
2534 // clear trace
2535 clear_trace();
2536 set_tracing(TRUE);
2537
2538
7bc95e2e 2539 bool finished = FALSE;
2b1f4228 2540 while (!BUTTON_PRESS() && !finished && !usb_poll_validate_length()) {
9ca155ba 2541 WDT_HIT();
9ca155ba
M
2542
2543 // find reader field
9ca155ba 2544 if (cardSTATE == MFEMUL_NOFIELD) {
0c8d25eb 2545 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
9ca155ba 2546 if (vHf > MF_MINFIELDV) {
0014cb46 2547 cardSTATE_TO_IDLE();
9ca155ba
M
2548 LED_A_ON();
2549 }
2550 }
d2f487af 2551 if(cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2552
d2f487af 2553 //Now, get data
6a1f2d82 2554 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2555 if (res == 2) { //Field is off!
2556 cardSTATE = MFEMUL_NOFIELD;
2557 LEDsoff();
2558 continue;
7bc95e2e 2559 } else if (res == 1) {
2560 break; //return value 1 means button press
2561 }
2562
d2f487af 2563 // REQ or WUP request in ANY state and WUP in HALTED state
2564 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2565 selTimer = GetTickCount();
2566 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2567 cardSTATE = MFEMUL_SELECT1;
2568
2569 // init crypto block
2570 LED_B_OFF();
2571 LED_C_OFF();
2572 crypto1_destroy(pcs);
2573 cardAUTHKEY = 0xff;
2574 continue;
0a39986e 2575 }
7bc95e2e 2576
50193c1e 2577 switch (cardSTATE) {
d2f487af 2578 case MFEMUL_NOFIELD:
2579 case MFEMUL_HALTED:
50193c1e 2580 case MFEMUL_IDLE:{
6a1f2d82 2581 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2582 break;
2583 }
2584 case MFEMUL_SELECT1:{
9ca155ba
M
2585 // select all
2586 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
d2f487af 2587 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2588 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2589 break;
9ca155ba
M
2590 }
2591
d2f487af 2592 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2593 {
2594 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2595 }
9ca155ba 2596 // select card
0a39986e
M
2597 if (len == 9 &&
2598 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
bfb6a143 2599 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
9ca155ba 2600 cuid = bytes_to_num(rUIDBCC1, 4);
8556b852
M
2601 if (!_7BUID) {
2602 cardSTATE = MFEMUL_WORK;
0014cb46
M
2603 LED_B_ON();
2604 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2605 break;
8556b852
M
2606 } else {
2607 cardSTATE = MFEMUL_SELECT2;
8556b852 2608 }
9ca155ba 2609 }
50193c1e
M
2610 break;
2611 }
d2f487af 2612 case MFEMUL_AUTH1:{
495d7f13 2613 if( len != 8) {
d2f487af 2614 cardSTATE_TO_IDLE();
6a1f2d82 2615 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2616 break;
2617 }
0c8d25eb 2618
d2f487af 2619 uint32_t ar = bytes_to_num(receivedCmd, 4);
6a1f2d82 2620 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2621
2622 //Collect AR/NR
46cd801c 2623 //if(ar_nr_collected < 2 && cardAUTHSC == 2){
495d7f13 2624 if(ar_nr_collected < 2) {
2625 if(ar_nr_responses[2] != ar) {
2626 // Avoid duplicates... probably not necessary, ar should vary.
c3c241f3 2627 //ar_nr_responses[ar_nr_collected*5] = 0;
2628 //ar_nr_responses[ar_nr_collected*5+1] = 0;
2629 ar_nr_responses[ar_nr_collected*5+2] = nonce;
2630 ar_nr_responses[ar_nr_collected*5+3] = nr;
2631 ar_nr_responses[ar_nr_collected*5+4] = ar;
273b57a7 2632 ar_nr_collected++;
12d708fe 2633 }
2634 // Interactive mode flag, means we need to send ACK
2635 if(flags & FLAG_INTERACTIVE && ar_nr_collected == 2)
12d708fe 2636 finished = true;
d2f487af 2637 }
2638
2639 // --- crypto
c3c241f3 2640 //crypto1_word(pcs, ar , 1);
2641 //cardRr = nr ^ crypto1_word(pcs, 0, 0);
2642
2643 //test if auth OK
2644 //if (cardRr != prng_successor(nonce, 64)){
2645
2646 //if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2647 // cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2648 // cardRr, prng_successor(nonce, 64));
7bc95e2e 2649 // Shouldn't we respond anything here?
d2f487af 2650 // Right now, we don't nack or anything, which causes the
2651 // reader to do a WUPA after a while. /Martin
b03c0f2d 2652 // -- which is the correct response. /piwi
c3c241f3 2653 //cardSTATE_TO_IDLE();
2654 //LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2655 //break;
2656 //}
d2f487af 2657
2658 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2659
2660 num_to_bytes(ans, 4, rAUTH_AT);
2661 // --- crypto
2662 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2663 LED_C_ON();
2664 cardSTATE = MFEMUL_WORK;
495d7f13 2665 if (MF_DBGLEVEL >= 4) {
2666 Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2667 cardAUTHSC,
2668 cardAUTHKEY == 0 ? 'A' : 'B',
2669 GetTickCount() - authTimer
2670 );
2671 }
d2f487af 2672 break;
2673 }
50193c1e 2674 case MFEMUL_SELECT2:{
7bc95e2e 2675 if (!len) {
6a1f2d82 2676 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2677 break;
2678 }
8556b852 2679 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
9ca155ba 2680 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
8556b852
M
2681 break;
2682 }
9ca155ba 2683
8556b852
M
2684 // select 2 card
2685 if (len == 9 &&
495d7f13 2686 (receivedCmd[0] == 0x95 &&
2687 receivedCmd[1] == 0x70 &&
2688 memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0) ) {
8556b852 2689 EmSendCmd(rSAK, sizeof(rSAK));
8556b852
M
2690 cuid = bytes_to_num(rUIDBCC2, 4);
2691 cardSTATE = MFEMUL_WORK;
2692 LED_B_ON();
0014cb46 2693 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
8556b852
M
2694 break;
2695 }
0014cb46
M
2696
2697 // i guess there is a command). go into the work state.
7bc95e2e 2698 if (len != 4) {
6a1f2d82 2699 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2700 break;
2701 }
0014cb46 2702 cardSTATE = MFEMUL_WORK;
d2f487af 2703 //goto lbWORK;
2704 //intentional fall-through to the next case-stmt
50193c1e 2705 }
51969283 2706
7bc95e2e 2707 case MFEMUL_WORK:{
2708 if (len == 0) {
6a1f2d82 2709 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2710 break;
2711 }
2712
d2f487af 2713 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2714
495d7f13 2715 // decrypt seqence
2716 if(encrypted_data)
51969283 2717 mf_crypto1_decrypt(pcs, receivedCmd, len);
7bc95e2e 2718
d2f487af 2719 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2720 authTimer = GetTickCount();
2721 cardAUTHSC = receivedCmd[1] / 4; // received block num
2722 cardAUTHKEY = receivedCmd[0] - 0x60;
2723 crypto1_destroy(pcs);//Added by martin
2724 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2725
d2f487af 2726 if (!encrypted_data) { // first authentication
b03c0f2d 2727 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
51969283 2728
d2f487af 2729 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2730 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
7bc95e2e 2731 } else { // nested authentication
b03c0f2d 2732 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
7bc95e2e 2733 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2734 num_to_bytes(ans, 4, rAUTH_AT);
2735 }
0c8d25eb 2736
d2f487af 2737 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2738 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2739 cardSTATE = MFEMUL_AUTH1;
2740 break;
51969283 2741 }
7bc95e2e 2742
8f51ddb0
M
2743 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2744 // BUT... ACK --> NACK
2745 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2746 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2747 break;
2748 }
2749
2750 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2751 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2752 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2753 break;
0a39986e
M
2754 }
2755
7bc95e2e 2756 if(len != 4) {
6a1f2d82 2757 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2758 break;
2759 }
d2f487af 2760
2761 if(receivedCmd[0] == 0x30 // read block
2762 || receivedCmd[0] == 0xA0 // write block
b03c0f2d 2763 || receivedCmd[0] == 0xC0 // inc
2764 || receivedCmd[0] == 0xC1 // dec
2765 || receivedCmd[0] == 0xC2 // restore
7bc95e2e 2766 || receivedCmd[0] == 0xB0) { // transfer
2767 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2768 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2769 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2770 break;
2771 }
2772
7bc95e2e 2773 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2774 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2775 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2776 break;
2777 }
d2f487af 2778 }
2779 // read block
2780 if (receivedCmd[0] == 0x30) {
495d7f13 2781 if (MF_DBGLEVEL >= 4) Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2782
8f51ddb0
M
2783 emlGetMem(response, receivedCmd[1], 1);
2784 AppendCrc14443a(response, 16);
6a1f2d82 2785 mf_crypto1_encrypt(pcs, response, 18, response_par);
2786 EmSendCmdPar(response, 18, response_par);
d2f487af 2787 numReads++;
12d708fe 2788 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
d2f487af 2789 Dbprintf("%d reads done, exiting", numReads);
2790 finished = true;
2791 }
0a39986e
M
2792 break;
2793 }
0a39986e 2794 // write block
d2f487af 2795 if (receivedCmd[0] == 0xA0) {
b03c0f2d 2796 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
8f51ddb0 2797 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2798 cardSTATE = MFEMUL_WRITEBL2;
2799 cardWRBL = receivedCmd[1];
0a39986e 2800 break;
7bc95e2e 2801 }
0014cb46 2802 // increment, decrement, restore
d2f487af 2803 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
b03c0f2d 2804 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2805 if (emlCheckValBl(receivedCmd[1])) {
c3c241f3 2806 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2807 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2808 break;
2809 }
2810 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2811 if (receivedCmd[0] == 0xC1)
2812 cardSTATE = MFEMUL_INTREG_INC;
2813 if (receivedCmd[0] == 0xC0)
2814 cardSTATE = MFEMUL_INTREG_DEC;
2815 if (receivedCmd[0] == 0xC2)
2816 cardSTATE = MFEMUL_INTREG_REST;
2817 cardWRBL = receivedCmd[1];
0014cb46
M
2818 break;
2819 }
0014cb46 2820 // transfer
d2f487af 2821 if (receivedCmd[0] == 0xB0) {
b03c0f2d 2822 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
0014cb46
M
2823 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2824 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2825 else
2826 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2827 break;
2828 }
9ca155ba 2829 // halt
d2f487af 2830 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
9ca155ba 2831 LED_B_OFF();
0a39986e 2832 LED_C_OFF();
0014cb46
M
2833 cardSTATE = MFEMUL_HALTED;
2834 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2835 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2836 break;
9ca155ba 2837 }
d2f487af 2838 // RATS
2839 if (receivedCmd[0] == 0xe0) {//RATS
8f51ddb0
M
2840 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2841 break;
2842 }
d2f487af 2843 // command not allowed
2844 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2845 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2846 break;
8f51ddb0
M
2847 }
2848 case MFEMUL_WRITEBL2:{
495d7f13 2849 if (len == 18) {
8f51ddb0
M
2850 mf_crypto1_decrypt(pcs, receivedCmd, len);
2851 emlSetMem(receivedCmd, cardWRBL, 1);
2852 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2853 cardSTATE = MFEMUL_WORK;
51969283 2854 } else {
0014cb46 2855 cardSTATE_TO_IDLE();
6a1f2d82 2856 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2857 }
8f51ddb0 2858 break;
50193c1e 2859 }
0014cb46
M
2860
2861 case MFEMUL_INTREG_INC:{
2862 mf_crypto1_decrypt(pcs, receivedCmd, len);
2863 memcpy(&ans, receivedCmd, 4);
2864 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2865 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2866 cardSTATE_TO_IDLE();
2867 break;
7bc95e2e 2868 }
6a1f2d82 2869 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2870 cardINTREG = cardINTREG + ans;
2871 cardSTATE = MFEMUL_WORK;
2872 break;
2873 }
2874 case MFEMUL_INTREG_DEC:{
2875 mf_crypto1_decrypt(pcs, receivedCmd, len);
2876 memcpy(&ans, receivedCmd, 4);
2877 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2878 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2879 cardSTATE_TO_IDLE();
2880 break;
2881 }
6a1f2d82 2882 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2883 cardINTREG = cardINTREG - ans;
2884 cardSTATE = MFEMUL_WORK;
2885 break;
2886 }
2887 case MFEMUL_INTREG_REST:{
2888 mf_crypto1_decrypt(pcs, receivedCmd, len);
2889 memcpy(&ans, receivedCmd, 4);
2890 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2891 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2892 cardSTATE_TO_IDLE();
2893 break;
2894 }
6a1f2d82 2895 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2896 cardSTATE = MFEMUL_WORK;
2897 break;
2898 }
50193c1e 2899 }
50193c1e
M
2900 }
2901
810f5379 2902 // Interactive mode flag, means we need to send ACK
2903 if(flags & FLAG_INTERACTIVE) {
d2f487af 2904 //May just aswell send the collected ar_nr in the response aswell
c3c241f3 2905 uint8_t len = ar_nr_collected*5*4;
2906 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
d2f487af 2907 }
d714d3ef 2908
810f5379 2909 if(flags & FLAG_NR_AR_ATTACK && MF_DBGLEVEL >= 1 ) {
12d708fe 2910 if(ar_nr_collected > 1 ) {
d2f487af 2911 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
c3c241f3 2912 Dbprintf("../tools/mfkey/mfkey32 %06x%08x %08x %08x %08x %08x %08x",
2913 ar_nr_responses[0], // UID1
2914 ar_nr_responses[1], // UID2
2915 ar_nr_responses[2], // NT
2916 ar_nr_responses[3], // AR1
2917 ar_nr_responses[4], // NR1
2918 ar_nr_responses[8], // AR2
2919 ar_nr_responses[9] // NR2
d2f487af 2920 );
7838f4be 2921 Dbprintf("../tools/mfkey/mfkey32v2 %06x%08x %08x %08x %08x %08x %08x %08x",
2922 ar_nr_responses[0], // UID1
2923 ar_nr_responses[1], // UID2
2924 ar_nr_responses[2], // NT1
2925 ar_nr_responses[3], // AR1
2926 ar_nr_responses[4], // NR1
2927 ar_nr_responses[7], // NT2
2928 ar_nr_responses[8], // AR2
2929 ar_nr_responses[9] // NR2
2930 );
7bc95e2e 2931 } else {
d2f487af 2932 Dbprintf("Failed to obtain two AR/NR pairs!");
12d708fe 2933 if(ar_nr_collected > 0 ) {
2b1f4228 2934 Dbprintf("Only got these: UID=%06x%08x, nonce=%08x, AR1=%08x, NR1=%08x",
c3c241f3 2935 ar_nr_responses[0], // UID1
2936 ar_nr_responses[1], // UID2
2937 ar_nr_responses[2], // NT
2938 ar_nr_responses[3], // AR1
2939 ar_nr_responses[4] // NR1
d2f487af 2940 );
2941 }
2942 }
2943 }
c3c241f3 2944 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
5ee53a0e 2945
91c7a7cc 2946 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2947 LEDsoff();
5ee53a0e 2948 set_tracing(FALSE);
15c4dc5a 2949}
b62a5a84 2950
d2f487af 2951
b62a5a84
M
2952//-----------------------------------------------------------------------------
2953// MIFARE sniffer.
2954//
2955//-----------------------------------------------------------------------------
5cd9ec01
M
2956void RAMFUNC SniffMifare(uint8_t param) {
2957 // param:
2958 // bit 0 - trigger from first card answer
2959 // bit 1 - trigger from first reader 7-bit request
b62a5a84 2960 LEDsoff();
810f5379 2961
aaa1a9a2 2962 // free eventually allocated BigBuf memory
2963 BigBuf_free(); BigBuf_Clear_ext(false);
3000dc4e
MHS
2964 clear_trace();
2965 set_tracing(TRUE);
b62a5a84 2966
b62a5a84 2967 // The command (reader -> tag) that we're receiving.
810f5379 2968 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
495d7f13 2969 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
810f5379 2970
b62a5a84 2971 // The response (tag -> reader) that we're receiving.
495d7f13 2972 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE] = {0x00};
2973 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b62a5a84 2974
99cf19d9 2975 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2976
f71f4deb 2977 // allocate the DMA buffer, used to stream samples from the FPGA
2978 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 2979 uint8_t *data = dmaBuf;
2980 uint8_t previous_data = 0;
5cd9ec01
M
2981 int maxDataLen = 0;
2982 int dataLen = 0;
7bc95e2e 2983 bool ReaderIsActive = FALSE;
2984 bool TagIsActive = FALSE;
2985
b62a5a84 2986 // Set up the demodulator for tag -> reader responses.
6a1f2d82 2987 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
2988
2989 // Set up the demodulator for the reader -> tag commands
6a1f2d82 2990 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
2991
2992 // Setup for the DMA.
7bc95e2e 2993 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 2994
b62a5a84 2995 LED_D_OFF();
39864b0b
M
2996
2997 // init sniffer
2998 MfSniffInit();
b62a5a84 2999
b62a5a84 3000 // And now we loop, receiving samples.
7bc95e2e 3001 for(uint32_t sniffCounter = 0; TRUE; ) {
91c7a7cc 3002
3003 LED_A_ON();
3004 WDT_HIT();
7bc95e2e 3005
5cd9ec01
M
3006 if(BUTTON_PRESS()) {
3007 DbpString("cancelled by button");
7bc95e2e 3008 break;
5cd9ec01 3009 }
91c7a7cc 3010
7bc95e2e 3011 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3012 // check if a transaction is completed (timeout after 2000ms).
3013 // if yes, stop the DMA transfer and send what we have so far to the client
3014 if (MfSniffSend(2000)) {
3015 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3016 sniffCounter = 0;
3017 data = dmaBuf;
3018 maxDataLen = 0;
3019 ReaderIsActive = FALSE;
3020 TagIsActive = FALSE;
3021 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 3022 }
39864b0b 3023 }
7bc95e2e 3024
3025 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3026 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
495d7f13 3027
3028 if (readBufDataP <= dmaBufDataP) // we are processing the same block of data which is currently being transferred
7bc95e2e 3029 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
495d7f13 3030 else
7bc95e2e 3031 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
495d7f13 3032
5cd9ec01 3033 // test for length of buffer
7bc95e2e 3034 if(dataLen > maxDataLen) { // we are more behind than ever...
3035 maxDataLen = dataLen;
f71f4deb 3036 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 3037 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 3038 break;
b62a5a84
M
3039 }
3040 }
5cd9ec01 3041 if(dataLen < 1) continue;
b62a5a84 3042
7bc95e2e 3043 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
3044 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3045 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3046 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
91c7a7cc 3047 Dbprintf("RxEmpty ERROR, data length:%d", dataLen); // temporary
5cd9ec01
M
3048 }
3049 // secondary buffer sets as primary, secondary buffer was stopped
3050 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3051 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
3052 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3053 }
5cd9ec01
M
3054
3055 LED_A_OFF();
b62a5a84 3056
7bc95e2e 3057 if (sniffCounter & 0x01) {
b62a5a84 3058
495d7f13 3059 // no need to try decoding tag data if the reader is sending
3060 if(!TagIsActive) {
7bc95e2e 3061 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3062 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3063 LED_C_INV();
495d7f13 3064
6a1f2d82 3065 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 3066
f8ada309 3067 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3068 DemodReset();
3069 }
3070 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3071 }
3072
495d7f13 3073 // no need to try decoding tag data if the reader is sending
3074 if(!ReaderIsActive) {
7bc95e2e 3075 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3076 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3077 LED_C_INV();
b62a5a84 3078
6a1f2d82 3079 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 3080
7bc95e2e 3081 DemodReset();
0ec548dc 3082 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3083 }
3084 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3085 }
b62a5a84
M
3086 }
3087
7bc95e2e 3088 previous_data = *data;
3089 sniffCounter++;
5cd9ec01 3090 data++;
495d7f13 3091
3092 if(data == dmaBuf + DMA_BUFFER_SIZE)
5cd9ec01 3093 data = dmaBuf;
7bc95e2e 3094
b62a5a84
M
3095 } // main cycle
3096
55acbb2a 3097 FpgaDisableSscDma();
39864b0b 3098 MfSniffEnd();
7838f4be 3099 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
91c7a7cc 3100 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3101 LEDsoff();
5ee53a0e 3102 set_tracing(FALSE);
3803d529 3103}
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