]> git.zerfleddert.de Git - proxmark3-svn/blame - armsrc/iso14443a.c
CHG: "hf 14a sim" command , correct use of FLAGS
[proxmark3-svn] / armsrc / iso14443a.c
CommitLineData
a126332a 1 //-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
e30c654b 13#include "proxmark3.h"
15c4dc5a 14#include "apps.h"
f7e3ed82 15#include "util.h"
9ab7a6c7 16#include "string.h"
902cb3c0 17#include "cmd.h"
15c4dc5a 18#include "iso14443crc.h"
534983d7 19#include "iso14443a.h"
6fc68747 20#include "iso14443b.h"
20f9a2a1
M
21#include "crapto1.h"
22#include "mifareutil.h"
3000dc4e 23#include "BigBuf.h"
f8ada309 24#include "parity.h"
25
534983d7 26static uint32_t iso14a_timeout;
1e262141 27int rsamples = 0;
1e262141 28uint8_t trigger = 0;
b0127e65 29// the block number for the ISO14443-4 PCB
30static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 31
0194ce8f 32static uint8_t* free_buffer_pointer;
33
7bc95e2e 34//
35// ISO14443 timing:
36//
37// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
38#define REQUEST_GUARD_TIME (7000/16 + 1)
39// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
40#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
41// bool LastCommandWasRequest = FALSE;
42
43//
44// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
45//
d714d3ef 46// When the PM acts as reader and is receiving tag data, it takes
47// 3 ticks delay in the AD converter
48// 16 ticks until the modulation detector completes and sets curbit
49// 8 ticks until bit_to_arm is assigned from curbit
50// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 51// 4*16 ticks until we measure the time
52// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 53#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 54
55// When the PM acts as a reader and is sending, it takes
56// 4*16 ticks until we can write data to the sending hold register
57// 8*16 ticks until the SHR is transferred to the Sending Shift Register
58// 8 ticks until the first transfer starts
59// 8 ticks later the FPGA samples the data
60// 1 tick to assign mod_sig_coil
61#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
62
63// When the PM acts as tag and is receiving it takes
d714d3ef 64// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 65// 3 ticks for the A/D conversion,
66// 8 ticks on average until the start of the SSC transfer,
67// 8 ticks until the SSC samples the first data
68// 7*16 ticks to complete the transfer from FPGA to ARM
69// 8 ticks until the next ssp_clk rising edge
d714d3ef 70// 4*16 ticks until we measure the time
7bc95e2e 71// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 72#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 73
74// The FPGA will report its internal sending delay in
75uint16_t FpgaSendQueueDelay;
76// the 5 first bits are the number of bits buffered in mod_sig_buf
77// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
78#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
79
80// When the PM acts as tag and is sending, it takes
d714d3ef 81// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 82// 8*16 ticks until the SHR is transferred to the Sending Shift Register
83// 8 ticks until the first transfer starts
84// 8 ticks later the FPGA samples the data
85// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
86// + 1 tick to assign mod_sig_coil
d714d3ef 87#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 88
89// When the PM acts as sniffer and is receiving tag data, it takes
90// 3 ticks A/D conversion
d714d3ef 91// 14 ticks to complete the modulation detection
92// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 93// + the delays in transferring data - which is the same for
94// sniffing reader and tag data and therefore not relevant
d714d3ef 95#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 96
d714d3ef 97// When the PM acts as sniffer and is receiving reader data, it takes
98// 2 ticks delay in analogue RF receiver (for the falling edge of the
99// start bit, which marks the start of the communication)
7bc95e2e 100// 3 ticks A/D conversion
d714d3ef 101// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 102// + the delays in transferring data - which is the same for
103// sniffing reader and tag data and therefore not relevant
d714d3ef 104#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 105
106//variables used for timing purposes:
107//these are in ssp_clk cycles:
6a1f2d82 108static uint32_t NextTransferTime;
109static uint32_t LastTimeProxToAirStart;
110static uint32_t LastProxToAirDuration;
7bc95e2e 111
8f51ddb0 112// CARD TO READER - manchester
72934aa3 113// Sequence D: 11110000 modulation with subcarrier during first half
114// Sequence E: 00001111 modulation with subcarrier during second half
115// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 116// READER TO CARD - miller
72934aa3 117// Sequence X: 00001100 drop after half a period
118// Sequence Y: 00000000 no drop
119// Sequence Z: 11000000 drop at start
120#define SEC_D 0xf0
121#define SEC_E 0x0f
122#define SEC_F 0x00
123#define SEC_X 0x0c
124#define SEC_Y 0x00
125#define SEC_Z 0xc0
15c4dc5a 126
902cb3c0 127void iso14a_set_trigger(bool enable) {
534983d7 128 trigger = enable;
129}
130
b0127e65 131void iso14a_set_timeout(uint32_t timeout) {
132 iso14a_timeout = timeout;
19a700a8 133 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
b0127e65 134}
8556b852 135
19a700a8 136void iso14a_set_ATS_timeout(uint8_t *ats) {
19a700a8 137 uint8_t tb1;
138 uint8_t fwi;
139 uint32_t fwt;
140
141 if (ats[0] > 1) { // there is a format byte T0
142 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
4c0cf2d2 143
144 if ((ats[1] & 0x10) == 0x10) // there is an interface byte TA(1) preceding TB(1)
19a700a8 145 tb1 = ats[3];
4c0cf2d2 146 else
19a700a8 147 tb1 = ats[2];
4c0cf2d2 148
19a700a8 149 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
ca5bad3d 150 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
151 //fwt = 4096 * (1 << fwi);
19a700a8 152
ca5bad3d 153 iso14a_set_timeout(fwt/(8*16));
154 //iso14a_set_timeout(fwt/128);
19a700a8 155 }
156 }
157}
158
15c4dc5a 159//-----------------------------------------------------------------------------
160// Generate the parity value for a byte sequence
e30c654b 161//
15c4dc5a 162//-----------------------------------------------------------------------------
91c7a7cc 163void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par) {
6a1f2d82 164 uint16_t paritybit_cnt = 0;
165 uint16_t paritybyte_cnt = 0;
166 uint8_t parityBits = 0;
167
168 for (uint16_t i = 0; i < iLen; i++) {
169 // Generate the parity bits
f8ada309 170 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
6a1f2d82 171 if (paritybit_cnt == 7) {
172 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
173 parityBits = 0; // and advance to next Parity Byte
174 paritybyte_cnt++;
175 paritybit_cnt = 0;
176 } else {
177 paritybit_cnt++;
178 }
5f6d6c90 179 }
6a1f2d82 180
181 // save remaining parity bits
91c7a7cc 182 par[paritybyte_cnt] = parityBits;
15c4dc5a 183}
184
91c7a7cc 185void AppendCrc14443a(uint8_t* data, int len) {
5f6d6c90 186 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 187}
188
7bc95e2e 189//=============================================================================
190// ISO 14443 Type A - Miller decoder
191//=============================================================================
192// Basics:
193// This decoder is used when the PM3 acts as a tag.
194// The reader will generate "pauses" by temporarily switching of the field.
195// At the PM3 antenna we will therefore measure a modulated antenna voltage.
196// The FPGA does a comparison with a threshold and would deliver e.g.:
197// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
198// The Miller decoder needs to identify the following sequences:
199// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
200// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
201// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
202// Note 1: the bitstream may start at any time. We therefore need to sync.
203// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 204//-----------------------------------------------------------------------------
b62a5a84 205static tUart Uart;
15c4dc5a 206
d7aa3739 207// Lookup-Table to decide if 4 raw bits are a modulation.
0ec548dc 208// We accept the following:
209// 0001 - a 3 tick wide pause
210// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
211// 0111 - a 2 tick wide pause shifted left
212// 1001 - a 2 tick wide pause shifted right
d7aa3739 213const bool Mod_Miller_LUT[] = {
0ec548dc 214 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
215 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
d7aa3739 216};
0ec548dc 217#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
218#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 219
91c7a7cc 220void UartReset() {
7bc95e2e 221 Uart.state = STATE_UNSYNCD;
222 Uart.bitCount = 0;
223 Uart.len = 0; // number of decoded data bytes
6a1f2d82 224 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 225 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 226 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 227 Uart.startTime = 0;
228 Uart.endTime = 0;
46c65fed 229
230 Uart.byteCntMax = 0;
231 Uart.posCnt = 0;
232 Uart.syncBit = 9999;
7bc95e2e 233}
15c4dc5a 234
91c7a7cc 235void UartInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 236 Uart.output = data;
237 Uart.parity = parity;
0ec548dc 238 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
6a1f2d82 239 UartReset();
240}
d714d3ef 241
7bc95e2e 242// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 243static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time) {
0ec548dc 244 Uart.fourBits = (Uart.fourBits << 8) | bit;
7bc95e2e 245
0c8d25eb 246 if (Uart.state == STATE_UNSYNCD) { // not yet synced
91c7a7cc 247 Uart.syncBit = 9999; // not set
46c65fed 248
249 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
250 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
251 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
252
0ec548dc 253 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
46c65fed 254 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
255 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
0ec548dc 256 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
46c65fed 257 //
258#define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
259#define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
260
0ec548dc 261 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
262 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
263 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
264 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
265 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
266 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
267 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
268 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
269
270 if (Uart.syncBit != 9999) { // found a sync bit
91c7a7cc 271 Uart.startTime = non_real_time ? non_real_time : (GetCountSspClk() & 0xfffffff8);
272 Uart.startTime -= Uart.syncBit;
273 Uart.endTime = Uart.startTime;
274 Uart.state = STATE_START_OF_COMMUNICATION;
275 }
7bc95e2e 276 } else {
15c4dc5a 277
0ec548dc 278 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
279 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
d7aa3739 280 UartReset();
d7aa3739 281 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 282 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
283 UartReset();
7bc95e2e 284 } else {
285 Uart.bitCount++;
286 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
287 Uart.state = STATE_MILLER_Z;
288 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
289 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
290 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
291 Uart.parityBits <<= 1; // make room for the parity bit
292 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
293 Uart.bitCount = 0;
294 Uart.shiftReg = 0;
6a1f2d82 295 if((Uart.len&0x0007) == 0) { // every 8 data bytes
296 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
297 Uart.parityBits = 0;
298 }
15c4dc5a 299 }
7bc95e2e 300 }
d7aa3739 301 }
302 } else {
0ec548dc 303 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 304 Uart.bitCount++;
305 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
306 Uart.state = STATE_MILLER_X;
307 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
308 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
309 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
310 Uart.parityBits <<= 1; // make room for the new parity bit
311 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
312 Uart.bitCount = 0;
313 Uart.shiftReg = 0;
6a1f2d82 314 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
315 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
316 Uart.parityBits = 0;
317 }
7bc95e2e 318 }
d7aa3739 319 } else { // no modulation in both halves - Sequence Y
7bc95e2e 320 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 321 Uart.state = STATE_UNSYNCD;
6a1f2d82 322 Uart.bitCount--; // last "0" was part of EOC sequence
323 Uart.shiftReg <<= 1; // drop it
324 if(Uart.bitCount > 0) { // if we decoded some bits
325 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
326 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
327 Uart.parityBits <<= 1; // add a (void) parity bit
328 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
329 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
330 return TRUE;
331 } else if (Uart.len & 0x0007) { // there are some parity bits to store
332 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
333 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 334 }
335 if (Uart.len) {
6a1f2d82 336 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 337 } else {
0c8d25eb 338 UartReset(); // Nothing received - start over
7bc95e2e 339 }
15c4dc5a 340 }
7bc95e2e 341 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
342 UartReset();
7bc95e2e 343 } else { // a logic "0"
344 Uart.bitCount++;
345 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
346 Uart.state = STATE_MILLER_Y;
347 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
348 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
349 Uart.parityBits <<= 1; // make room for the parity bit
350 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
351 Uart.bitCount = 0;
352 Uart.shiftReg = 0;
6a1f2d82 353 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
354 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
355 Uart.parityBits = 0;
356 }
15c4dc5a 357 }
358 }
d7aa3739 359 }
15c4dc5a 360 }
7bc95e2e 361 }
7bc95e2e 362 return FALSE; // not finished yet, need more data
15c4dc5a 363}
364
365//=============================================================================
e691fc45 366// ISO 14443 Type A - Manchester decoder
15c4dc5a 367//=============================================================================
e691fc45 368// Basics:
7bc95e2e 369// This decoder is used when the PM3 acts as a reader.
e691fc45 370// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
371// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
372// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
373// The Manchester decoder needs to identify the following sequences:
374// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
375// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
376// 8 ticks unmodulated: Sequence F = end of communication
377// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 378// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 379// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 380static tDemod Demod;
15c4dc5a 381
d7aa3739 382// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 383// We accept three or four "1" in any position
7bc95e2e 384const bool Mod_Manchester_LUT[] = {
d7aa3739 385 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 386 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 387};
388
389#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
390#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 391
91c7a7cc 392void DemodReset() {
7bc95e2e 393 Demod.state = DEMOD_UNSYNCD;
394 Demod.len = 0; // number of decoded data bytes
6a1f2d82 395 Demod.parityLen = 0;
7bc95e2e 396 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
397 Demod.parityBits = 0; //
398 Demod.collisionPos = 0; // Position of collision bit
399 Demod.twoBits = 0xffff; // buffer for 2 Bits
400 Demod.highCnt = 0;
401 Demod.startTime = 0;
91c7a7cc 402 Demod.endTime = 0;
46c65fed 403 Demod.bitCount = 0;
404 Demod.syncBit = 0xFFFF;
405 Demod.samples = 0;
e691fc45 406}
15c4dc5a 407
91c7a7cc 408void DemodInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 409 Demod.output = data;
410 Demod.parity = parity;
411 DemodReset();
412}
413
7bc95e2e 414// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 415static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time) {
7bc95e2e 416 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 417
7bc95e2e 418 if (Demod.state == DEMOD_UNSYNCD) {
419
420 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
421 if (Demod.twoBits == 0x0000) {
422 Demod.highCnt++;
423 } else {
424 Demod.highCnt = 0;
425 }
426 } else {
427 Demod.syncBit = 0xFFFF; // not set
428 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
429 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
430 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
431 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
432 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
433 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
434 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
435 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 436 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 437 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
438 Demod.startTime -= Demod.syncBit;
439 Demod.bitCount = offset; // number of decoded data bits
e691fc45 440 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 441 }
7bc95e2e 442 }
7bc95e2e 443 } else {
15c4dc5a 444
7bc95e2e 445 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
446 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 447 if (!Demod.collisionPos) {
448 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
449 }
450 } // modulation in first half only - Sequence D = 1
7bc95e2e 451 Demod.bitCount++;
452 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
453 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 454 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 455 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 456 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
457 Demod.bitCount = 0;
458 Demod.shiftReg = 0;
6a1f2d82 459 if((Demod.len&0x0007) == 0) { // every 8 data bytes
460 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
461 Demod.parityBits = 0;
462 }
15c4dc5a 463 }
7bc95e2e 464 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
465 } else { // no modulation in first half
466 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 467 Demod.bitCount++;
7bc95e2e 468 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 469 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 470 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 471 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 472 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
473 Demod.bitCount = 0;
474 Demod.shiftReg = 0;
6a1f2d82 475 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
476 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
477 Demod.parityBits = 0;
478 }
15c4dc5a 479 }
7bc95e2e 480 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 481 } else { // no modulation in both halves - End of communication
6a1f2d82 482 if(Demod.bitCount > 0) { // there are some remaining data bits
483 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
484 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
485 Demod.parityBits <<= 1; // add a (void) parity bit
486 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
487 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
488 return TRUE;
489 } else if (Demod.len & 0x0007) { // there are some parity bits to store
490 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
491 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 492 }
493 if (Demod.len) {
d7aa3739 494 return TRUE; // we are finished with decoding the raw data sequence
495 } else { // nothing received. Start over
496 DemodReset();
e691fc45 497 }
15c4dc5a 498 }
7bc95e2e 499 }
e691fc45 500 }
e691fc45 501 return FALSE; // not finished yet, need more data
15c4dc5a 502}
503
504//=============================================================================
505// Finally, a `sniffer' for ISO 14443 Type A
506// Both sides of communication!
507//=============================================================================
508
509//-----------------------------------------------------------------------------
510// Record the sequence of commands sent by the reader to the tag, with
511// triggering so that we start recording at the point that the tag is moved
512// near the reader.
bc939371 513// "hf 14a sniff"
15c4dc5a 514//-----------------------------------------------------------------------------
d26849d4 515void RAMFUNC SniffIso14443a(uint8_t param) {
5cd9ec01
M
516 // param:
517 // bit 0 - trigger from first card answer
518 // bit 1 - trigger from first reader 7-bit request
5cd9ec01 519 LEDsoff();
5cd9ec01 520
99cf19d9 521 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
7bc95e2e 522
f71f4deb 523 // Allocate memory from BigBuf for some buffers
524 // free all previous allocations first
aaa1a9a2 525 BigBuf_free(); BigBuf_Clear_ext(false);
7838f4be 526 clear_trace();
527 set_tracing(TRUE);
528
5cd9ec01 529 // The command (reader -> tag) that we're receiving.
f71f4deb 530 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
531 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 532
5cd9ec01 533 // The response (tag -> reader) that we're receiving.
f71f4deb 534 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
535 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
536
537 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 538 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
539
7bc95e2e 540 uint8_t *data = dmaBuf;
541 uint8_t previous_data = 0;
5cd9ec01
M
542 int maxDataLen = 0;
543 int dataLen = 0;
7bc95e2e 544 bool TagIsActive = FALSE;
545 bool ReaderIsActive = FALSE;
546
5cd9ec01 547 // Set up the demodulator for tag -> reader responses.
6a1f2d82 548 DemodInit(receivedResponse, receivedResponsePar);
549
5cd9ec01 550 // Set up the demodulator for the reader -> tag commands
6a1f2d82 551 UartInit(receivedCmd, receivedCmdPar);
552
7bc95e2e 553 // Setup and start DMA.
5cd9ec01 554 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 555
99cf19d9 556 // We won't start recording the frames that we acquire until we trigger;
557 // a good trigger condition to get started is probably when we see a
558 // response from the tag.
559 // triggered == FALSE -- to wait first for card
560 bool triggered = !(param & 0x03);
561
5cd9ec01 562 // And now we loop, receiving samples.
7bc95e2e 563 for(uint32_t rsamples = 0; TRUE; ) {
564
5cd9ec01
M
565 if(BUTTON_PRESS()) {
566 DbpString("cancelled by button");
7bc95e2e 567 break;
5cd9ec01 568 }
15c4dc5a 569
5cd9ec01
M
570 LED_A_ON();
571 WDT_HIT();
15c4dc5a 572
5cd9ec01
M
573 int register readBufDataP = data - dmaBuf;
574 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
575 if (readBufDataP <= dmaBufDataP){
576 dataLen = dmaBufDataP - readBufDataP;
577 } else {
7bc95e2e 578 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
579 }
580 // test for length of buffer
581 if(dataLen > maxDataLen) {
582 maxDataLen = dataLen;
f71f4deb 583 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 584 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
585 break;
5cd9ec01
M
586 }
587 }
588 if(dataLen < 1) continue;
589
590 // primary buffer was stopped( <-- we lost data!
591 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
592 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
593 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 594 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
595 }
596 // secondary buffer sets as primary, secondary buffer was stopped
597 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
598 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
599 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
600 }
601
602 LED_A_OFF();
7bc95e2e 603
604 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 605
7bc95e2e 606 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
607 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
608 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
609 LED_C_ON();
5cd9ec01 610
7bc95e2e 611 // check - if there is a short 7bit request from reader
612 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 613
7bc95e2e 614 if(triggered) {
6a1f2d82 615 if (!LogTrace(receivedCmd,
616 Uart.len,
617 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
618 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
619 Uart.parity,
620 TRUE)) break;
7bc95e2e 621 }
622 /* And ready to receive another command. */
623 UartReset();
624 /* And also reset the demod code, which might have been */
625 /* false-triggered by the commands from the reader. */
626 DemodReset();
627 LED_B_OFF();
628 }
629 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 630 }
3be2a5ae 631
7bc95e2e 632 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
633 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
634 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
635 LED_B_ON();
5cd9ec01 636
6a1f2d82 637 if (!LogTrace(receivedResponse,
638 Demod.len,
639 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
640 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
641 Demod.parity,
642 FALSE)) break;
5cd9ec01 643
7bc95e2e 644 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 645
7bc95e2e 646 // And ready to receive another response.
647 DemodReset();
0ec548dc 648 // And reset the Miller decoder including itS (now outdated) input buffer
649 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 650 LED_C_OFF();
651 }
652 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
653 }
5cd9ec01
M
654 }
655
7bc95e2e 656 previous_data = *data;
657 rsamples++;
5cd9ec01 658 data++;
d714d3ef 659 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
660 data = dmaBuf;
661 }
662 } // main cycle
663
bc939371 664 if (MF_DBGLEVEL >= 1) {
665 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
666 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
667 }
7bc95e2e 668 FpgaDisableSscDma();
91c7a7cc 669 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
bc939371 670 LEDsoff();
5ee53a0e 671 set_tracing(FALSE);
15c4dc5a 672}
673
15c4dc5a 674//-----------------------------------------------------------------------------
675// Prepare tag messages
676//-----------------------------------------------------------------------------
91c7a7cc 677static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity) {
8f51ddb0 678 ToSendReset();
15c4dc5a 679
680 // Correction bit, might be removed when not needed
681 ToSendStuffBit(0);
682 ToSendStuffBit(0);
683 ToSendStuffBit(0);
684 ToSendStuffBit(0);
685 ToSendStuffBit(1); // 1
686 ToSendStuffBit(0);
687 ToSendStuffBit(0);
688 ToSendStuffBit(0);
8f51ddb0 689
15c4dc5a 690 // Send startbit
72934aa3 691 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 692 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 693
6a1f2d82 694 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 695 uint8_t b = cmd[i];
15c4dc5a 696
697 // Data bits
6a1f2d82 698 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 699 if(b & 1) {
72934aa3 700 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 701 } else {
72934aa3 702 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
703 }
704 b >>= 1;
705 }
15c4dc5a 706
0014cb46 707 // Get the parity bit
6a1f2d82 708 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 709 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 710 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 711 } else {
72934aa3 712 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 713 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 714 }
8f51ddb0 715 }
15c4dc5a 716
8f51ddb0
M
717 // Send stopbit
718 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 719
8f51ddb0 720 // Convert from last byte pos to length
6fc68747 721 ++ToSendMax;
8f51ddb0
M
722}
723
91c7a7cc 724static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len) {
7504dc50 725 uint8_t par[MAX_PARITY_SIZE] = {0};
6a1f2d82 726 GetParity(cmd, len, par);
727 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 728}
729
91c7a7cc 730static void Code4bitAnswerAsTag(uint8_t cmd) {
91c7a7cc 731 uint8_t b = cmd;
8f51ddb0 732
5f6d6c90 733 ToSendReset();
8f51ddb0
M
734
735 // Correction bit, might be removed when not needed
736 ToSendStuffBit(0);
737 ToSendStuffBit(0);
738 ToSendStuffBit(0);
739 ToSendStuffBit(0);
740 ToSendStuffBit(1); // 1
741 ToSendStuffBit(0);
742 ToSendStuffBit(0);
743 ToSendStuffBit(0);
744
745 // Send startbit
746 ToSend[++ToSendMax] = SEC_D;
747
0194ce8f 748 for(uint8_t i = 0; i < 4; i++) {
8f51ddb0
M
749 if(b & 1) {
750 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 751 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
752 } else {
753 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 754 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
755 }
756 b >>= 1;
757 }
758
759 // Send stopbit
760 ToSend[++ToSendMax] = SEC_F;
761
5f6d6c90 762 // Convert from last byte pos to length
763 ToSendMax++;
15c4dc5a 764}
765
766//-----------------------------------------------------------------------------
767// Wait for commands from reader
768// Stop when button is pressed
769// Or return TRUE when command is captured
770//-----------------------------------------------------------------------------
91c7a7cc 771static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len) {
15c4dc5a 772 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
773 // only, since we are receiving, not transmitting).
774 // Signal field is off with the appropriate LED
775 LED_D_OFF();
776 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
777
ca5bad3d 778 // Now run a `software UART` on the stream of incoming samples.
6a1f2d82 779 UartInit(received, parity);
7bc95e2e 780
781 // clear RXRDY:
782 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 783
784 for(;;) {
785 WDT_HIT();
786
787 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 788
15c4dc5a 789 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 790 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
791 if(MillerDecoding(b, 0)) {
792 *len = Uart.len;
15c4dc5a 793 return TRUE;
794 }
7bc95e2e 795 }
15c4dc5a 796 }
797}
28afbd2b 798
ce02f6f9 799bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 800 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 801 // This will need the following byte array for a modulation sequence
802 // 144 data bits (18 * 8)
803 // 18 parity bits
804 // 2 Start and stop
805 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
806 // 1 just for the case
807 // ----------- +
808 // 166 bytes, since every bit that needs to be send costs us a byte
809 //
91c7a7cc 810 // Prepare the tag modulation bits from the message
811 CodeIso14443aAsTag(response_info->response,response_info->response_n);
812
813 // Make sure we do not exceed the free buffer space
814 if (ToSendMax > max_buffer_size) {
815 Dbprintf("Out of memory, when modulating bits for tag answer:");
816 Dbhexdump(response_info->response_n,response_info->response,false);
817 return FALSE;
818 }
819
820 // Copy the byte array, used for this modulation to the buffer position
821 memcpy(response_info->modulation,ToSend,ToSendMax);
822
823 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
824 response_info->modulation_n = ToSendMax;
825 response_info->ProxToAirDuration = LastProxToAirDuration;
826 return TRUE;
ce02f6f9 827}
828
f71f4deb 829// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
830// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
831// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
832// -> need 273 bytes buffer
c9216a92 833// 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
834// 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
835#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
f71f4deb 836
ce02f6f9 837bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
ca5bad3d 838 // Retrieve and store the current buffer index
839 response_info->modulation = free_buffer_pointer;
840
841 // Determine the maximum size we can use from our buffer
842 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
843
844 // Forward the prepare tag modulation function to the inner function
845 if (prepare_tag_modulation(response_info, max_buffer_size)) {
846 // Update the free buffer offset
847 free_buffer_pointer += ToSendMax;
848 return true;
849 } else {
850 return false;
851 }
ce02f6f9 852}
853
15c4dc5a 854//-----------------------------------------------------------------------------
855// Main loop of simulated tag: receive commands from reader, decide what
856// response to send, and send it.
857//-----------------------------------------------------------------------------
91c7a7cc 858void SimulateIso14443aTag(int tagType, int flags, byte_t* data) {
0194ce8f 859
bc939371 860 //Here, we collect CUID, NT, NR, AR, CUID, NT2, NR2, AR2
d26849d4 861 // This can be used in a reader-only attack.
d26849d4 862 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0,0};
863 uint8_t ar_nr_collected = 0;
0194ce8f 864 uint8_t sak = 0;
bc939371 865 uint32_t cuid = 0;
866 uint32_t nonce = 0;
867
32719adf 868 // PACK response to PWD AUTH for EV1/NTAG
0194ce8f 869 uint8_t response8[4] = {0,0,0,0};
870 // Counter for EV1/NTAG
871 uint32_t counters[] = {0,0,0};
32719adf 872
81cd0474 873 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
0194ce8f 874 uint8_t response1[] = {0,0};
81cd0474 875
876 switch (tagType) {
0194ce8f 877 case 1: { // MIFARE Classic 1k
81cd0474 878 response1[0] = 0x04;
81cd0474 879 sak = 0x08;
880 } break;
881 case 2: { // MIFARE Ultralight
32719adf 882 response1[0] = 0x44;
81cd0474 883 sak = 0x00;
884 } break;
885 case 3: { // MIFARE DESFire
81cd0474 886 response1[0] = 0x04;
887 response1[1] = 0x03;
888 sak = 0x20;
889 } break;
0194ce8f 890 case 4: { // ISO/IEC 14443-4 - javacard (JCOP)
81cd0474 891 response1[0] = 0x04;
81cd0474 892 sak = 0x28;
893 } break;
3fe4ff4f 894 case 5: { // MIFARE TNP3XXX
3fe4ff4f 895 response1[0] = 0x01;
896 response1[1] = 0x0f;
897 sak = 0x01;
d26849d4 898 } break;
0194ce8f 899 case 6: { // MIFARE Mini 320b
d26849d4 900 response1[0] = 0x44;
d26849d4 901 sak = 0x09;
902 } break;
0194ce8f 903 case 7: { // NTAG
32719adf 904 response1[0] = 0x44;
32719adf 905 sak = 0x00;
906 // PACK
907 response8[0] = 0x80;
908 response8[1] = 0x80;
909 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
2b1f4228 910 // uid not supplied then get from emulator memory
911 if (data[0]==0) {
912 uint16_t start = 4 * (0+12);
913 uint8_t emdata[8];
914 emlGetMemBt( emdata, start, sizeof(emdata));
915 memcpy(data, emdata, 3); //uid bytes 0-2
916 memcpy(data+3, emdata+4, 4); //uid bytes 3-7
917 flags |= FLAG_7B_UID_IN_DATA;
918 }
32719adf 919 } break;
81cd0474 920 default: {
921 Dbprintf("Error: unkown tagtype (%d)",tagType);
922 return;
923 } break;
924 }
925
926 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 927 uint8_t response2[5] = {0x00};
81cd0474 928
0194ce8f 929 // For UID size 7,
c8b6da22 930 uint8_t response2a[5] = {0x00};
931
bc939371 932 if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA ) {
0194ce8f 933 response2[0] = 0x88; // Cascade Tag marker
d26849d4 934 response2[1] = data[0];
935 response2[2] = data[1];
936 response2[3] = data[2];
937
938 response2a[0] = data[3];
939 response2a[1] = data[4];
940 response2a[2] = data[5];
c3c241f3 941 response2a[3] = data[6]; //??
81cd0474 942 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
943
944 // Configure the ATQA and SAK accordingly
945 response1[0] |= 0x40;
946 sak |= 0x04;
bc939371 947
948 cuid = bytes_to_num(data+3, 4);
81cd0474 949 } else {
d26849d4 950 memcpy(response2, data, 4);
81cd0474 951 // Configure the ATQA and SAK accordingly
952 response1[0] &= 0xBF;
953 sak &= 0xFB;
bc939371 954 cuid = bytes_to_num(data, 4);
81cd0474 955 }
956
957 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
958 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
959
960 // Prepare the mandatory SAK (for 4 and 7 byte UID)
0194ce8f 961 uint8_t response3[3] = {sak, 0x00, 0x00};
81cd0474 962 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
963
964 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 965 uint8_t response3a[3] = {0x00};
81cd0474 966 response3a[0] = sak & 0xFB;
967 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
968
0194ce8f 969 uint8_t response5[] = { 0x01, 0x01, 0x01, 0x01 }; // Very random tag nonce
970 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
6a1f2d82 971 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
972 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
973 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
974 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 975 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
976
bc939371 977 // the randon nonce
978 nonce = bytes_to_num(response5, 4);
979
2b1f4228 980 // Prepare GET_VERSION (different for UL EV-1 / NTAG)
32719adf 981 //uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
0194ce8f 982 //uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
c9216a92 983 // Prepare CHK_TEARING
2b1f4228 984 //uint8_t response9[] = {0xBD,0x90,0x3f};
c9216a92 985
986 #define TAG_RESPONSE_COUNT 10
7bc95e2e 987 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
988 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
989 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
990 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
991 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
992 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
993 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
994 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
4c0cf2d2 995
495d7f13 996 { .response = response8, .response_n = sizeof(response8) } // EV1/NTAG PACK response
4c0cf2d2 997 };
998 //{ .response = response7_NTAG, .response_n = sizeof(response7_NTAG)}, // EV1/NTAG GET_VERSION response
2b1f4228 999 //{ .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
4c0cf2d2 1000
7bc95e2e 1001
1002 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1003 // Such a response is less time critical, so we can prepare them on the fly
1004 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1005 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1006 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1007 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1008 tag_response_info_t dynamic_response_info = {
1009 .response = dynamic_response_buffer,
1010 .response_n = 0,
1011 .modulation = dynamic_modulation_buffer,
1012 .modulation_n = 0
1013 };
ce02f6f9 1014
99cf19d9 1015 // We need to listen to the high-frequency, peak-detected path.
1016 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1017
f71f4deb 1018 BigBuf_free_keep_EM();
0194ce8f 1019 clear_trace();
1020 set_tracing(TRUE);
f71f4deb 1021
1022 // allocate buffers:
1023 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1024 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1025 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1026
7bc95e2e 1027 // Prepare the responses of the anticollision phase
ce02f6f9 1028 // there will be not enough time to do this at the moment the reader sends it REQA
495d7f13 1029 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++)
7bc95e2e 1030 prepare_allocated_tag_modulation(&responses[i]);
15c4dc5a 1031
7bc95e2e 1032 int len = 0;
15c4dc5a 1033
1034 // To control where we are in the protocol
1035 int order = 0;
1036 int lastorder;
1037
1038 // Just to allow some checks
1039 int happened = 0;
1040 int happened2 = 0;
81cd0474 1041 int cmdsRecvd = 0;
7bc95e2e 1042 tag_response_info_t* p_response;
15c4dc5a 1043
254b70a4 1044 LED_A_ON();
0194ce8f 1045 for(;;) {
4c0cf2d2 1046 WDT_HIT();
1047
7bc95e2e 1048 // Clean receive command buffer
6a1f2d82 1049 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1050 DbpString("Button press");
254b70a4 1051 break;
1052 }
bc939371 1053
1054 // incease nonce at every command recieved
1055 nonce++;
1056 num_to_bytes(nonce, 4, response5);
1057
7bc95e2e 1058 p_response = NULL;
1059
254b70a4 1060 // Okay, look at the command now.
1061 lastorder = order;
0194ce8f 1062 if(receivedCmd[0] == ISO14443A_CMD_REQA) { // Received a REQUEST
ce02f6f9 1063 p_response = &responses[0]; order = 1;
0194ce8f 1064 } else if(receivedCmd[0] == ISO14443A_CMD_WUPA) { // Received a WAKEUP
ce02f6f9 1065 p_response = &responses[0]; order = 6;
0194ce8f 1066 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received request for UID (cascade 1)
ce02f6f9 1067 p_response = &responses[1]; order = 2;
0194ce8f 1068 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received request for UID (cascade 2)
ce02f6f9 1069 p_response = &responses[2]; order = 20;
0194ce8f 1070 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received a SELECT (cascade 1)
ce02f6f9 1071 p_response = &responses[3]; order = 3;
0194ce8f 1072 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received a SELECT (cascade 2)
1073 p_response = &responses[4]; order = 30;
1074 } else if(receivedCmd[0] == ISO14443A_CMD_READBLOCK) { // Received a (plain) READ
32719adf 1075 uint8_t block = receivedCmd[1];
2b1f4228 1076 // if Ultralight or NTAG (4 byte blocks)
1077 if ( tagType == 7 || tagType == 2 ) {
1078 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1079 uint16_t start = 4 * (block+12);
5e428463 1080 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1081 emlGetMemBt( emdata, start, 16);
1082 AppendCrc14443a(emdata, 16);
1083 EmSendCmdEx(emdata, sizeof(emdata), false);
2b1f4228 1084 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
32719adf 1085 p_response = NULL;
2b1f4228 1086 } else { // all other tags (16 byte block tags)
1087 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
32719adf 1088 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1089 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1090 p_response = NULL;
1091 }
0194ce8f 1092 } else if(receivedCmd[0] == MIFARE_ULEV1_FASTREAD) { // Received a FAST READ (ranged read)
91c7a7cc 1093 uint8_t emdata[MAX_FRAME_SIZE];
1094 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1095 int start = (receivedCmd[1]+12) * 4;
1096 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
1097 emlGetMemBt( emdata, start, len);
1098 AppendCrc14443a(emdata, len);
1099 EmSendCmdEx(emdata, len+2, false);
1100 p_response = NULL;
0194ce8f 1101 } else if(receivedCmd[0] == MIFARE_ULEV1_READSIG && tagType == 7) { // Received a READ SIGNATURE --
91c7a7cc 1102 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1103 uint16_t start = 4 * 4;
1104 uint8_t emdata[34];
1105 emlGetMemBt( emdata, start, 32);
1106 AppendCrc14443a(emdata, 32);
1107 EmSendCmdEx(emdata, sizeof(emdata), false);
1108 p_response = NULL;
0194ce8f 1109 } else if (receivedCmd[0] == MIFARE_ULEV1_READ_CNT && tagType == 7) { // Received a READ COUNTER --
e9a92fe2 1110 uint8_t index = receivedCmd[1];
a126332a 1111 uint8_t data[] = {0x00,0x00,0x00,0x14,0xa5};
e9a92fe2 1112 if ( counters[index] > 0) {
1113 num_to_bytes(counters[index], 3, data);
1114 AppendCrc14443a(data, sizeof(data)-2);
1115 }
a126332a 1116 EmSendCmdEx(data,sizeof(data),false);
1117 p_response = NULL;
0194ce8f 1118 } else if (receivedCmd[0] == MIFARE_ULEV1_INCR_CNT && tagType == 7) { // Received a INC COUNTER --
ce3d6bd2 1119 // number of counter
a126332a 1120 uint8_t counter = receivedCmd[1];
1121 uint32_t val = bytes_to_num(receivedCmd+2,4);
1122 counters[counter] = val;
1123
ce3d6bd2 1124 // send ACK
1125 uint8_t ack[] = {0x0a};
1126 EmSendCmdEx(ack,sizeof(ack),false);
91c7a7cc 1127 p_response = NULL;
0194ce8f 1128 } else if(receivedCmd[0] == MIFARE_ULEV1_CHECKTEAR && tagType == 7) { // Received a CHECK_TEARING_EVENT --
2b1f4228 1129 //first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1130 uint8_t emdata[3];
1131 uint8_t counter=0;
1132 if (receivedCmd[1]<3) counter = receivedCmd[1];
1133 emlGetMemBt( emdata, 10+counter, 1);
1134 AppendCrc14443a(emdata, sizeof(emdata)-2);
1135 EmSendCmdEx(emdata, sizeof(emdata), false);
b0300679 1136 p_response = NULL;
0194ce8f 1137 } else if(receivedCmd[0] == ISO14443A_CMD_HALT) { // Received a HALT
810f5379 1138 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1139 p_response = NULL;
0194ce8f 1140 } else if(receivedCmd[0] == MIFARE_AUTH_KEYA || receivedCmd[0] == MIFARE_AUTH_KEYB) { // Received an authentication request
32719adf 1141
1142 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
2b1f4228 1143 uint8_t emdata[10];
1144 emlGetMemBt( emdata, 0, 8 );
1145 AppendCrc14443a(emdata, sizeof(emdata)-2);
1146 EmSendCmdEx(emdata, sizeof(emdata), false);
1147 p_response = NULL;
32719adf 1148 } else {
1149 p_response = &responses[5]; order = 7;
1150 }
0194ce8f 1151 } else if(receivedCmd[0] == ISO14443A_CMD_RATS) { // Received a RATS request
7bc95e2e 1152 if (tagType == 1 || tagType == 2) { // RATS not supported
1153 EmSend4bit(CARD_NACK_NA);
1154 p_response = NULL;
1155 } else {
1156 p_response = &responses[6]; order = 70;
1157 }
6a1f2d82 1158 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
810f5379 1159 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1160 uint32_t nr = bytes_to_num(receivedCmd,4);
1161 uint32_t ar = bytes_to_num(receivedCmd+4,4);
d26849d4 1162
bc939371 1163 if ( (flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) {
d26849d4 1164 if(ar_nr_collected < 2){
1165 // Avoid duplicates... probably not necessary, nr should vary.
bc939371 1166 // nr doesn't change in pm3's reading etc. its fixed.
d26849d4 1167 //if(ar_nr_responses[3] != nr){
bc939371 1168 ar_nr_responses[ar_nr_collected*4] = cuid;
0194ce8f 1169 ar_nr_responses[ar_nr_collected*4+1] = nonce;
1170 ar_nr_responses[ar_nr_collected*4+2] = nr;
1171 ar_nr_responses[ar_nr_collected*4+3] = ar;
d26849d4 1172 ar_nr_collected++;
1173 //}
1174 }
1175
0194ce8f 1176 if(ar_nr_collected > 1 ) {
bc939371 1177 if (MF_DBGLEVEL >= 2 && !(flags & FLAG_INTERACTIVE)) {
d26849d4 1178 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
0194ce8f 1179 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
1180 ar_nr_responses[0], // CUID
1181 ar_nr_responses[1], // NT
1182 ar_nr_responses[2], // AR1
1183 ar_nr_responses[3], // NR1
1184 ar_nr_responses[6], // AR2
1185 ar_nr_responses[7] // NR2
d26849d4 1186 );
1187 }
bc939371 1188 uint8_t len = ar_nr_collected*4*4;
1189 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
d26849d4 1190 ar_nr_collected = 0;
1191 memset(ar_nr_responses, 0x00, len);
d26849d4 1192 }
1193 }
0194ce8f 1194 } else if (receivedCmd[0] == MIFARE_ULC_AUTH_1 ) { // ULC authentication, or Desfire Authentication
1195 } else if (receivedCmd[0] == MIFARE_ULEV1_AUTH) { // NTAG / EV-1 authentication
32719adf 1196 if ( tagType == 7 ) {
2b1f4228 1197 uint16_t start = 13; //first 4 blocks of emu are [getversion answer - check tearing - pack - 0x00]
1198 uint8_t emdata[4];
1199 emlGetMemBt( emdata, start, 2);
1200 AppendCrc14443a(emdata, 2);
1201 EmSendCmdEx(emdata, sizeof(emdata), false);
1202 p_response = NULL;
ce3d6bd2 1203 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
e98572a1 1204
91c7a7cc 1205 if ( MF_DBGLEVEL >= 3) Dbprintf("Auth attempt: %08x", pwd);
32719adf 1206 }
2b1f4228 1207 } else {
7bc95e2e 1208 // Check for ISO 14443A-4 compliant commands, look at left nibble
1209 switch (receivedCmd[0]) {
7838f4be 1210 case 0x02:
1211 case 0x03: { // IBlock (command no CID)
1212 dynamic_response_info.response[0] = receivedCmd[0];
1213 dynamic_response_info.response[1] = 0x90;
1214 dynamic_response_info.response[2] = 0x00;
1215 dynamic_response_info.response_n = 3;
1216 } break;
7bc95e2e 1217 case 0x0B:
7838f4be 1218 case 0x0A: { // IBlock (command CID)
7bc95e2e 1219 dynamic_response_info.response[0] = receivedCmd[0];
1220 dynamic_response_info.response[1] = 0x00;
1221 dynamic_response_info.response[2] = 0x90;
1222 dynamic_response_info.response[3] = 0x00;
1223 dynamic_response_info.response_n = 4;
1224 } break;
1225
1226 case 0x1A:
1227 case 0x1B: { // Chaining command
1228 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1229 dynamic_response_info.response_n = 2;
1230 } break;
1231
1232 case 0xaa:
1233 case 0xbb: {
1234 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1235 dynamic_response_info.response_n = 2;
1236 } break;
1237
7838f4be 1238 case 0xBA: { // ping / pong
1239 dynamic_response_info.response[0] = 0xAB;
1240 dynamic_response_info.response[1] = 0x00;
1241 dynamic_response_info.response_n = 2;
7bc95e2e 1242 } break;
1243
1244 case 0xCA:
1245 case 0xC2: { // Readers sends deselect command
7838f4be 1246 dynamic_response_info.response[0] = 0xCA;
1247 dynamic_response_info.response[1] = 0x00;
1248 dynamic_response_info.response_n = 2;
7bc95e2e 1249 } break;
1250
1251 default: {
1252 // Never seen this command before
810f5379 1253 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1254 Dbprintf("Received unknown command (len=%d):",len);
1255 Dbhexdump(len,receivedCmd,false);
1256 // Do not respond
1257 dynamic_response_info.response_n = 0;
1258 } break;
1259 }
ce02f6f9 1260
7bc95e2e 1261 if (dynamic_response_info.response_n > 0) {
1262 // Copy the CID from the reader query
1263 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1264
7bc95e2e 1265 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1266 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1267 dynamic_response_info.response_n += 2;
ce02f6f9 1268
7bc95e2e 1269 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1270 Dbprintf("Error preparing tag response");
810f5379 1271 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1272 break;
1273 }
1274 p_response = &dynamic_response_info;
1275 }
81cd0474 1276 }
15c4dc5a 1277
1278 // Count number of wakeups received after a halt
1279 if(order == 6 && lastorder == 5) { happened++; }
1280
1281 // Count number of other messages after a halt
1282 if(order != 6 && lastorder == 5) { happened2++; }
1283
bc939371 1284 // comment this limit if you want to simulation longer
1285 if (!tracing) {
1286 Dbprintf("Trace Full. Simulation stopped.");
1287 break;
1288 }
91c7a7cc 1289 // comment this limit if you want to simulation longer
15c4dc5a 1290 if(cmdsRecvd > 999) {
1291 DbpString("1000 commands later...");
254b70a4 1292 break;
15c4dc5a 1293 }
ce02f6f9 1294 cmdsRecvd++;
1295
1296 if (p_response != NULL) {
7bc95e2e 1297 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1298 // do the tracing for the previous reader request and this tag answer:
810f5379 1299 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1300 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1301
7bc95e2e 1302 EmLogTrace(Uart.output,
1303 Uart.len,
1304 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1305 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1306 Uart.parity,
7bc95e2e 1307 p_response->response,
1308 p_response->response_n,
1309 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1310 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1311 par);
7bc95e2e 1312 }
7bc95e2e 1313 }
15c4dc5a 1314
d26849d4 1315 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 1316 set_tracing(FALSE);
f71f4deb 1317 BigBuf_free_keep_EM();
c9216a92 1318 LED_A_OFF();
1319
0de8e387 1320 if (MF_DBGLEVEL >= 4){
5ee53a0e 1321 Dbprintf("-[ Wake ups after halt [%d]", happened);
1322 Dbprintf("-[ Messages after halt [%d]", happened2);
1323 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
0de8e387 1324 }
15c4dc5a 1325}
1326
9492e0b0 1327// prepare a delayed transfer. This simply shifts ToSend[] by a number
1328// of bits specified in the delay parameter.
0194ce8f 1329void PrepareDelayedTransfer(uint16_t delay) {
7504dc50 1330 delay &= 0x07;
1331 if (!delay) return;
1332
9492e0b0 1333 uint8_t bitmask = 0;
1334 uint8_t bits_to_shift = 0;
1335 uint8_t bits_shifted = 0;
7504dc50 1336 uint16_t i = 0;
1337
1338 for (i = 0; i < delay; ++i)
1339 bitmask |= (0x01 << i);
2285d9dd 1340
6fc68747 1341 ToSend[++ToSendMax] = 0x00;
7504dc50 1342
1343 for (i = 0; i < ToSendMax; ++i) {
9492e0b0 1344 bits_to_shift = ToSend[i] & bitmask;
1345 ToSend[i] = ToSend[i] >> delay;
1346 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1347 bits_shifted = bits_to_shift;
1348 }
1349 }
9492e0b0 1350
7bc95e2e 1351
1352//-------------------------------------------------------------------------------------
15c4dc5a 1353// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1354// Parameter timing:
7bc95e2e 1355// if NULL: transfer at next possible time, taking into account
1356// request guard time and frame delay time
1357// if == 0: transfer immediately and return time of transfer
9492e0b0 1358// if != 0: delay transfer until time specified
7bc95e2e 1359//-------------------------------------------------------------------------------------
0194ce8f 1360static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing) {
9492e0b0 1361 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1362
7bc95e2e 1363 uint32_t ThisTransferTime = 0;
e30c654b 1364
9492e0b0 1365 if (timing) {
ca5bad3d 1366 if(*timing == 0) { // Measure time
7bc95e2e 1367 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
ca5bad3d 1368 } else {
1369 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1370 }
1371 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1372 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
7bc95e2e 1373 LastTimeProxToAirStart = *timing;
1374 } else {
1375 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
7504dc50 1376
7bc95e2e 1377 while(GetCountSspClk() < ThisTransferTime);
7504dc50 1378
7bc95e2e 1379 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1380 }
1381
7bc95e2e 1382 // clear TXRDY
1383 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1384
7bc95e2e 1385 uint16_t c = 0;
9492e0b0 1386 for(;;) {
1387 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1388 AT91C_BASE_SSC->SSC_THR = cmd[c];
4c0cf2d2 1389 ++c;
5ebcb867 1390 if(c >= len)
9492e0b0 1391 break;
9492e0b0 1392 }
1393 }
7bc95e2e 1394
1395 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1396}
1397
15c4dc5a 1398//-----------------------------------------------------------------------------
195af472 1399// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1400//-----------------------------------------------------------------------------
6a1f2d82 1401void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1402{
7bc95e2e 1403 int i, j;
5ebcb867 1404 int last = 0;
7bc95e2e 1405 uint8_t b;
e30c654b 1406
7bc95e2e 1407 ToSendReset();
e30c654b 1408
7bc95e2e 1409 // Start of Communication (Seq. Z)
1410 ToSend[++ToSendMax] = SEC_Z;
1411 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
7bc95e2e 1412
1413 size_t bytecount = nbytes(bits);
1414 // Generate send structure for the data bits
1415 for (i = 0; i < bytecount; i++) {
1416 // Get the current byte to send
1417 b = cmd[i];
1418 size_t bitsleft = MIN((bits-(i*8)),8);
1419
1420 for (j = 0; j < bitsleft; j++) {
1421 if (b & 1) {
1422 // Sequence X
1423 ToSend[++ToSendMax] = SEC_X;
1424 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1425 last = 1;
1426 } else {
1427 if (last == 0) {
1428 // Sequence Z
1429 ToSend[++ToSendMax] = SEC_Z;
1430 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1431 } else {
1432 // Sequence Y
1433 ToSend[++ToSendMax] = SEC_Y;
1434 last = 0;
1435 }
1436 }
1437 b >>= 1;
1438 }
1439
6a1f2d82 1440 // Only transmit parity bit if we transmitted a complete byte
0ec548dc 1441 if (j == 8 && parity != NULL) {
7bc95e2e 1442 // Get the parity bit
6a1f2d82 1443 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1444 // Sequence X
1445 ToSend[++ToSendMax] = SEC_X;
1446 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1447 last = 1;
1448 } else {
1449 if (last == 0) {
1450 // Sequence Z
1451 ToSend[++ToSendMax] = SEC_Z;
1452 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1453 } else {
1454 // Sequence Y
1455 ToSend[++ToSendMax] = SEC_Y;
1456 last = 0;
1457 }
1458 }
1459 }
1460 }
e30c654b 1461
7bc95e2e 1462 // End of Communication: Logic 0 followed by Sequence Y
1463 if (last == 0) {
1464 // Sequence Z
1465 ToSend[++ToSendMax] = SEC_Z;
1466 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1467 } else {
1468 // Sequence Y
1469 ToSend[++ToSendMax] = SEC_Y;
1470 last = 0;
1471 }
1472 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1473
7bc95e2e 1474 // Convert to length of command:
4b78d6b3 1475 ++ToSendMax;
15c4dc5a 1476}
1477
195af472 1478//-----------------------------------------------------------------------------
1479// Prepare reader command to send to FPGA
1480//-----------------------------------------------------------------------------
0194ce8f 1481void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity) {
ca5bad3d 1482 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1483}
1484
9ca155ba
M
1485//-----------------------------------------------------------------------------
1486// Wait for commands from reader
1487// Stop when button is pressed (return 1) or field was gone (return 2)
1488// Or return 0 when command is captured
1489//-----------------------------------------------------------------------------
0194ce8f 1490static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity) {
9ca155ba
M
1491 *len = 0;
1492
1493 uint32_t timer = 0, vtime = 0;
1494 int analogCnt = 0;
1495 int analogAVG = 0;
1496
1497 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1498 // only, since we are receiving, not transmitting).
1499 // Signal field is off with the appropriate LED
1500 LED_D_OFF();
1501 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1502
1503 // Set ADC to read field strength
1504 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1505 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1506 ADC_MODE_PRESCALE(63) |
1507 ADC_MODE_STARTUP_TIME(1) |
1508 ADC_MODE_SAMPLE_HOLD_TIME(15);
9ca155ba
M
1509 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1510 // start ADC
1511 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1512
1513 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1514 UartInit(received, parity);
7bc95e2e 1515
1516 // Clear RXRDY:
1517 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1518
9ca155ba
M
1519 for(;;) {
1520 WDT_HIT();
1521
1522 if (BUTTON_PRESS()) return 1;
1523
1524 // test if the field exists
1525 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1526 analogCnt++;
1527 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1528 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1529 if (analogCnt >= 32) {
0c8d25eb 1530 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
9ca155ba
M
1531 vtime = GetTickCount();
1532 if (!timer) timer = vtime;
1533 // 50ms no field --> card to idle state
1534 if (vtime - timer > 50) return 2;
1535 } else
1536 if (timer) timer = 0;
1537 analogCnt = 0;
1538 analogAVG = 0;
1539 }
1540 }
7bc95e2e 1541
9ca155ba 1542 // receive and test the miller decoding
7bc95e2e 1543 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1544 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1545 if(MillerDecoding(b, 0)) {
1546 *len = Uart.len;
9ca155ba
M
1547 return 0;
1548 }
7bc95e2e 1549 }
9ca155ba
M
1550 }
1551}
1552
0194ce8f 1553int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded) {
7bc95e2e 1554 uint8_t b;
1555 uint16_t i = 0;
1556 uint32_t ThisTransferTime;
1557
9ca155ba
M
1558 // Modulate Manchester
1559 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1560
1561 // include correction bit if necessary
1562 if (Uart.parityBits & 0x01) {
1563 correctionNeeded = TRUE;
1564 }
0194ce8f 1565 // 1236, so correction bit needed
1566 i = (correctionNeeded) ? 0 : 1;
7bc95e2e 1567
d714d3ef 1568 // clear receiving shift register and holding register
7bc95e2e 1569 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1570 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1571 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1572 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1573
7bc95e2e 1574 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1575 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1576 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1577 if (AT91C_BASE_SSC->SSC_RHR) break;
1578 }
1579
1580 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1581
1582 // Clear TXRDY:
1583 AT91C_BASE_SSC->SSC_THR = SEC_F;
1584
9ca155ba 1585 // send cycle
bb42a03e 1586 for(; i < respLen; ) {
9ca155ba 1587 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1588 AT91C_BASE_SSC->SSC_THR = resp[i++];
1589 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1590 }
7bc95e2e 1591
17ad0e09 1592 if(BUTTON_PRESS()) break;
9ca155ba
M
1593 }
1594
7bc95e2e 1595 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
4b78d6b3 1596 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3; // twich /8 ?? >>3,
0c8d25eb 1597 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
7bc95e2e 1598 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1599 AT91C_BASE_SSC->SSC_THR = SEC_F;
1600 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1601 i++;
1602 }
1603 }
7bc95e2e 1604 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
9ca155ba
M
1605 return 0;
1606}
1607
7bc95e2e 1608int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1609 Code4bitAnswerAsTag(resp);
0a39986e 1610 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1611 // do the tracing for the previous reader request and this tag answer:
5ebcb867 1612 uint8_t par[1] = {0x00};
6a1f2d82 1613 GetParity(&resp, 1, par);
7bc95e2e 1614 EmLogTrace(Uart.output,
1615 Uart.len,
1616 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1617 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1618 Uart.parity,
7bc95e2e 1619 &resp,
1620 1,
1621 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1622 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1623 par);
0a39986e 1624 return res;
9ca155ba
M
1625}
1626
8f51ddb0 1627int EmSend4bit(uint8_t resp){
7bc95e2e 1628 return EmSend4bitEx(resp, false);
8f51ddb0
M
1629}
1630
6a1f2d82 1631int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1632 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1633 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1634 // do the tracing for the previous reader request and this tag answer:
1635 EmLogTrace(Uart.output,
1636 Uart.len,
1637 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1638 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1639 Uart.parity,
7bc95e2e 1640 resp,
1641 respLen,
1642 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1643 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1644 par);
8f51ddb0
M
1645 return res;
1646}
1647
6a1f2d82 1648int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
5ebcb867 1649 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1650 GetParity(resp, respLen, par);
1651 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
8f51ddb0
M
1652}
1653
6a1f2d82 1654int EmSendCmd(uint8_t *resp, uint16_t respLen){
5ebcb867 1655 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1656 GetParity(resp, respLen, par);
1657 return EmSendCmdExPar(resp, respLen, false, par);
8f51ddb0
M
1658}
1659
6a1f2d82 1660int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1661 return EmSendCmdExPar(resp, respLen, false, par);
1662}
1663
6a1f2d82 1664bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1665 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1666{
810f5379 1667 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1668 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1669 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1670 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1671 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1672 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1673 reader_EndTime = tag_StartTime - exact_fdt;
1674 reader_StartTime = reader_EndTime - reader_modlen;
5ebcb867 1675
810f5379 1676 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE))
1677 return FALSE;
1678 else
1679 return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1680
9ca155ba
M
1681}
1682
15c4dc5a 1683//-----------------------------------------------------------------------------
1684// Wait a certain time for tag response
1685// If a response is captured return TRUE
e691fc45 1686// If it takes too long return FALSE
15c4dc5a 1687//-----------------------------------------------------------------------------
0194ce8f 1688static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset) {
46c65fed 1689 uint32_t c = 0x00;
e691fc45 1690
15c4dc5a 1691 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1692 // only, since we are receiving, not transmitting).
1693 // Signal field is on with the appropriate LED
1694 LED_D_ON();
1695 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1696
534983d7 1697 // Now get the answer from the card
6a1f2d82 1698 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1699
7bc95e2e 1700 // clear RXRDY:
1701 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1702
15c4dc5a 1703 for(;;) {
534983d7 1704 WDT_HIT();
15c4dc5a 1705
534983d7 1706 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1707 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1708 if(ManchesterDecoding(b, offset, 0)) {
1709 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1710 return TRUE;
19a700a8 1711 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
7bc95e2e 1712 return FALSE;
15c4dc5a 1713 }
534983d7 1714 }
1715 }
15c4dc5a 1716}
1717
0194ce8f 1718void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing) {
6a1f2d82 1719 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1720
7bc95e2e 1721 // Send command to tag
1722 TransmitFor14443a(ToSend, ToSendMax, timing);
0194ce8f 1723 if(trigger) LED_A_ON();
dfc3c505 1724
7bc95e2e 1725 // Log reader command in trace buffer
4b78d6b3 1726 //LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
1727 LogTrace(frame, nbytes(bits), (LastTimeProxToAirStart<<4) + DELAY_ARM2AIR_AS_READER, ((LastTimeProxToAirStart + LastProxToAirDuration)<<4) + DELAY_ARM2AIR_AS_READER, par, TRUE);
15c4dc5a 1728}
1729
0194ce8f 1730void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing) {
ca5bad3d 1731 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1732}
15c4dc5a 1733
0194ce8f 1734void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing) {
e691fc45 1735 // Generate parity and redirect
5ebcb867 1736 uint8_t par[MAX_PARITY_SIZE] = {0x00};
ca5bad3d 1737 GetParity(frame, len/8, par);
6a1f2d82 1738 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1739}
1740
0194ce8f 1741void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing) {
15c4dc5a 1742 // Generate parity and redirect
5ebcb867 1743 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1744 GetParity(frame, len, par);
ca5bad3d 1745 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1746}
1747
0194ce8f 1748int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity) {
1749 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset))
1750 return FALSE;
1751 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
e691fc45 1752 return Demod.len;
1753}
1754
91c7a7cc 1755int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity) {
0194ce8f 1756 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0))
1757 return FALSE;
91c7a7cc 1758 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
e691fc45 1759 return Demod.len;
f89c7050
M
1760}
1761
c188b1b9 1762// performs iso14443a anticollision (optional) and card select procedure
1763// fills the uid and cuid pointer unless NULL
1764// fills the card info record unless NULL
1765// if anticollision is false, then the UID must be provided in uid_ptr[]
1766// and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1767int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades) {
6a1f2d82 1768 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1769 uint8_t sel_all[] = { 0x93,0x20 };
1770 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1771 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
4c0cf2d2 1772 uint8_t resp[MAX_FRAME_SIZE] = {0}; // theoretically. A usual RATS will be much smaller
1773 uint8_t resp_par[MAX_PARITY_SIZE] = {0};
1774 byte_t uid_resp[4] = {0};
1775 size_t uid_resp_len = 0;
6a1f2d82 1776
1777 uint8_t sak = 0x04; // cascade uid
1778 int cascade_level = 0;
1779 int len;
1780
1781 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
c188b1b9 1782 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
7bc95e2e 1783
6a1f2d82 1784 // Receive the ATQA
1785 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1786
1787 if(p_hi14a_card) {
1788 memcpy(p_hi14a_card->atqa, resp, 2);
1789 p_hi14a_card->uidlen = 0;
1790 memset(p_hi14a_card->uid,0,10);
1791 }
5f6d6c90 1792
c188b1b9 1793 if (anticollision) {
4c0cf2d2 1794 // clear uid
1795 if (uid_ptr)
1796 memset(uid_ptr,0,10);
c188b1b9 1797 }
79a73ab2 1798
0ec548dc 1799 // check for proprietary anticollision:
4c0cf2d2 1800 if ((resp[0] & 0x1F) == 0) return 3;
0ec548dc 1801
6a1f2d82 1802 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1803 // which case we need to make a cascade 2 request and select - this is a long UID
1804 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1805 for(; sak & 0x04; cascade_level++) {
1806 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1807 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1808
c188b1b9 1809 if (anticollision) {
6a1f2d82 1810 // SELECT_ALL
4c0cf2d2 1811 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1812 if (!ReaderReceive(resp, resp_par)) return 0;
1813
1814 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1815 memset(uid_resp, 0, 4);
1816 uint16_t uid_resp_bits = 0;
1817 uint16_t collision_answer_offset = 0;
1818 // anti-collision-loop:
1819 while (Demod.collisionPos) {
1820 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1821 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1822 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1823 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1824 }
1825 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1826 uid_resp_bits++;
1827 // construct anticollosion command:
1828 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1829 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1830 sel_uid[2+i] = uid_resp[i];
1831 }
1832 collision_answer_offset = uid_resp_bits%8;
1833 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1834 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
6a1f2d82 1835 }
4c0cf2d2 1836 // finally, add the last bits and BCC of the UID
1837 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1838 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1839 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1840 }
e691fc45 1841
4c0cf2d2 1842 } else { // no collision, use the response to SELECT_ALL as current uid
1843 memcpy(uid_resp, resp, 4);
1844 }
1845
c188b1b9 1846 } else {
1847 if (cascade_level < num_cascades - 1) {
1848 uid_resp[0] = 0x88;
1849 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1850 } else {
1851 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1852 }
1853 }
6a1f2d82 1854 uid_resp_len = 4;
5f6d6c90 1855
6a1f2d82 1856 // calculate crypto UID. Always use last 4 Bytes.
4c0cf2d2 1857 if(cuid_ptr)
6a1f2d82 1858 *cuid_ptr = bytes_to_num(uid_resp, 4);
e30c654b 1859
6a1f2d82 1860 // Construct SELECT UID command
1861 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
c188b1b9 1862 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
6a1f2d82 1863 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1864 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1865 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1866
1867 // Receive the SAK
1868 if (!ReaderReceive(resp, resp_par)) return 0;
4c0cf2d2 1869
6a1f2d82 1870 sak = resp[0];
1871
810f5379 1872 // Test if more parts of the uid are coming
6a1f2d82 1873 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1874 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1875 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1876 uid_resp[0] = uid_resp[1];
1877 uid_resp[1] = uid_resp[2];
1878 uid_resp[2] = uid_resp[3];
6a1f2d82 1879 uid_resp_len = 3;
1880 }
5f6d6c90 1881
4c0cf2d2 1882 if(uid_ptr && anticollision)
6a1f2d82 1883 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
5f6d6c90 1884
6a1f2d82 1885 if(p_hi14a_card) {
1886 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1887 p_hi14a_card->uidlen += uid_resp_len;
1888 }
1889 }
79a73ab2 1890
6a1f2d82 1891 if(p_hi14a_card) {
1892 p_hi14a_card->sak = sak;
1893 p_hi14a_card->ats_len = 0;
1894 }
534983d7 1895
3fe4ff4f 1896 // non iso14443a compliant tag
1897 if( (sak & 0x20) == 0) return 2;
534983d7 1898
6a1f2d82 1899 // Request for answer to select
1900 AppendCrc14443a(rats, 2);
1901 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1902
6a1f2d82 1903 if (!(len = ReaderReceive(resp, resp_par))) return 0;
3fe4ff4f 1904
6a1f2d82 1905 if(p_hi14a_card) {
1906 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1907 p_hi14a_card->ats_len = len;
1908 }
5f6d6c90 1909
6a1f2d82 1910 // reset the PCB block number
1911 iso14_pcb_blocknum = 0;
19a700a8 1912
1913 // set default timeout based on ATS
1914 iso14a_set_ATS_timeout(resp);
1915
6a1f2d82 1916 return 1;
7e758047 1917}
15c4dc5a 1918
7bc95e2e 1919void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1920 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1921 // Set up the synchronous serial port
1922 FpgaSetupSsc();
7bc95e2e 1923 // connect Demodulated Signal to ADC:
7e758047 1924 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
91c7a7cc 1925
1926 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
ca5bad3d 1927
1928 LED_D_OFF();
7e758047 1929 // Signal field is on with the appropriate LED
ca5bad3d 1930 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD ||
1931 fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN)
7bc95e2e 1932 LED_D_ON();
6fc68747 1933
91c7a7cc 1934 // Prepare the demodulation functions
7bc95e2e 1935 DemodReset();
1936 UartReset();
6fc68747 1937
46c65fed 1938 iso14a_set_timeout(10*106); // 10ms default
91c7a7cc 1939
1940 //NextTransferTime = 2 * DELAY_ARM2AIR_AS_READER;
1941 NextTransferTime = DELAY_ARM2AIR_AS_READER << 1;
6fc68747 1942
1943 // Start the timer
1944 StartCountSspClk();
7e758047 1945}
15c4dc5a 1946
6a1f2d82 1947int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
810f5379 1948 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
534983d7 1949 uint8_t real_cmd[cmd_len+4];
1950 real_cmd[0] = 0x0a; //I-Block
b0127e65 1951 // put block number into the PCB
1952 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 1953 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1954 memcpy(real_cmd+2, cmd, cmd_len);
1955 AppendCrc14443a(real_cmd,cmd_len+2);
1956
9492e0b0 1957 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 1958 size_t len = ReaderReceive(data, parity);
ca5bad3d 1959 //DATA LINK ERROR
1960 if (!len) return 0;
1961
6a1f2d82 1962 uint8_t *data_bytes = (uint8_t *) data;
ca5bad3d 1963
b0127e65 1964 // if we received an I- or R(ACK)-Block with a block number equal to the
1965 // current block number, toggle the current block number
ca5bad3d 1966 if (len >= 4 // PCB+CID+CRC = 4 bytes
b0127e65 1967 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1968 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1969 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1970 {
1971 iso14_pcb_blocknum ^= 1;
1972 }
1973
534983d7 1974 return len;
1975}
1976
7e758047 1977//-----------------------------------------------------------------------------
1978// Read an ISO 14443a tag. Send out commands and store answers.
1979//
1980//-----------------------------------------------------------------------------
91c7a7cc 1981void ReaderIso14443a(UsbCommand *c) {
534983d7 1982 iso14a_command_t param = c->arg[0];
04bc1c66 1983 size_t len = c->arg[1] & 0xffff;
1984 size_t lenbits = c->arg[1] >> 16;
1985 uint32_t timeout = c->arg[2];
91c7a7cc 1986 uint8_t *cmd = c->d.asBytes;
9492e0b0 1987 uint32_t arg0 = 0;
810f5379 1988 byte_t buf[USB_CMD_DATA_SIZE] = {0x00};
1989 uint8_t par[MAX_PARITY_SIZE] = {0x00};
902cb3c0 1990
810f5379 1991 if (param & ISO14A_CONNECT)
3000dc4e 1992 clear_trace();
e691fc45 1993
3000dc4e 1994 set_tracing(TRUE);
e30c654b 1995
810f5379 1996 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 1997 iso14a_set_trigger(TRUE);
15c4dc5a 1998
810f5379 1999 if (param & ISO14A_CONNECT) {
7bc95e2e 2000 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 2001 if(!(param & ISO14A_NO_SELECT)) {
2002 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
c188b1b9 2003 arg0 = iso14443a_select_card(NULL,card,NULL, true, 0);
91c7a7cc 2004 cmd_send(CMD_ACK, arg0, card->uidlen, 0, buf, sizeof(iso14a_card_select_t));
6fc68747 2005 // if it fails, the cmdhf14a.c client quites.. however this one still executes.
2006 if ( arg0 == 0 ) return;
5f6d6c90 2007 }
534983d7 2008 }
e30c654b 2009
810f5379 2010 if (param & ISO14A_SET_TIMEOUT)
04bc1c66 2011 iso14a_set_timeout(timeout);
e30c654b 2012
810f5379 2013 if (param & ISO14A_APDU) {
902cb3c0 2014 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 2015 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2016 }
e30c654b 2017
810f5379 2018 if (param & ISO14A_RAW) {
534983d7 2019 if(param & ISO14A_APPEND_CRC) {
0ec548dc 2020 if(param & ISO14A_TOPAZMODE) {
2021 AppendCrc14443b(cmd,len);
2022 } else {
d26849d4 2023 AppendCrc14443a(cmd,len);
0ec548dc 2024 }
534983d7 2025 len += 2;
c7324bef 2026 if (lenbits) lenbits += 16;
15c4dc5a 2027 }
0ec548dc 2028 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2029 if(param & ISO14A_TOPAZMODE) {
2030 int bits_to_send = lenbits;
2031 uint16_t i = 0;
2032 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2033 bits_to_send -= 7;
2034 while (bits_to_send > 0) {
2035 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2036 bits_to_send -= 8;
2037 }
2038 } else {
6a1f2d82 2039 GetParity(cmd, lenbits/8, par);
0ec548dc 2040 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2041 }
2042 } else { // want to send complete bytes only
2043 if(param & ISO14A_TOPAZMODE) {
2044 uint16_t i = 0;
2045 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2046 while (i < len) {
2047 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2048 }
5f6d6c90 2049 } else {
0ec548dc 2050 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2051 }
5f6d6c90 2052 }
6a1f2d82 2053 arg0 = ReaderReceive(buf, par);
9492e0b0 2054 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2055 }
15c4dc5a 2056
810f5379 2057 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 2058 iso14a_set_trigger(FALSE);
15c4dc5a 2059
810f5379 2060 if (param & ISO14A_NO_DISCONNECT)
534983d7 2061 return;
15c4dc5a 2062
15c4dc5a 2063 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 2064 set_tracing(FALSE);
15c4dc5a 2065 LEDsoff();
15c4dc5a 2066}
b0127e65 2067
1c611bbd 2068// Determine the distance between two nonces.
2069// Assume that the difference is small, but we don't know which is first.
2070// Therefore try in alternating directions.
2071int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2072
ca5bad3d 2073 if (nt1 == nt2) return 0;
ca5bad3d 2074
91c7a7cc 2075 uint16_t i;
2076 uint32_t nttmp1 = nt1;
2077 uint32_t nttmp2 = nt2;
2078
0194ce8f 2079 for (i = 1; i < (32768/8); ++i) {
bc939371 2080 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i;
2081 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -i;
0194ce8f 2082
2083 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+1;
2084 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+1);
2085 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+2;
2086 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+2);
2087 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+3;
2088 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+3);
2089 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+4;
2090 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+4);
2091 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+5;
2092 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+5);
2093 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+6;
2094 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+6);
2095 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+7;
2096 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+7);
91c7a7cc 2097 }
2098 // either nt1 or nt2 are invalid nonces
2099 return(-99999);
e772353f 2100}
2101
1c611bbd 2102//-----------------------------------------------------------------------------
2103// Recover several bits of the cypher stream. This implements (first stages of)
2104// the algorithm described in "The Dark Side of Security by Obscurity and
2105// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2106// (article by Nicolas T. Courtois, 2009)
2107//-----------------------------------------------------------------------------
91c7a7cc 2108void ReaderMifare(bool first_try, uint8_t block ) {
91c7a7cc 2109 uint8_t mf_auth[] = { MIFARE_AUTH_KEYA, block, 0x00, 0x00 };
b0300679 2110 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2111 uint8_t uid[10] = {0,0,0,0,0,0,0,0,0,0};
2112 uint8_t par_list[8] = {0,0,0,0,0,0,0,0};
2113 uint8_t ks_list[8] = {0,0,0,0,0,0,0,0};
495d7f13 2114 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = {0x00};
2115 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b0300679 2116 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2117 byte_t nt_diff = 0;
6a1f2d82 2118 uint32_t nt = 0;
b0300679 2119 uint32_t previous_nt = 0;
b0300679 2120 uint32_t cuid = 0;
2121
91c7a7cc 2122 int32_t catch_up_cycles = 0;
2123 int32_t last_catch_up = 0;
2124 int32_t isOK = 0;
2125 int32_t nt_distance = 0;
b0300679 2126
4c0cf2d2 2127 uint16_t elapsed_prng_sequences = 1;
1c611bbd 2128 uint16_t consecutive_resyncs = 0;
0de8e387 2129 uint16_t unexpected_random = 0;
2130 uint16_t sync_tries = 0;
b0300679 2131
bc939371 2132 // static variables here, is re-used in the next call
b0300679 2133 static uint32_t nt_attacked = 0;
2134 static uint32_t sync_time = 0;
91c7a7cc 2135 static uint32_t sync_cycles = 0;
b0300679 2136 static uint8_t par_low = 0;
2137 static uint8_t mf_nr_ar3 = 0;
91c7a7cc 2138
b0300679 2139 #define PRNG_SEQUENCE_LENGTH (1 << 16)
2140 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2141 #define MAX_SYNC_TRIES 32
4c0cf2d2 2142
91c7a7cc 2143 BigBuf_free(); BigBuf_Clear_ext(false);
4b78d6b3 2144 clear_trace();
91c7a7cc 2145 set_tracing(TRUE);
2146 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
4c0cf2d2 2147
91c7a7cc 2148 AppendCrc14443a(mf_auth, 2);
2149
4c0cf2d2 2150 if (first_try) {
2151 sync_time = GetCountSspClk() & 0xfffffff8;
91c7a7cc 2152 sync_cycles = PRNG_SEQUENCE_LENGTH + 1130; //65536; //0x10000 // Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
4c0cf2d2 2153 mf_nr_ar3 = 0;
2154 nt_attacked = 0;
91c7a7cc 2155 par_low = 0;
4c0cf2d2 2156 } else {
b0300679 2157 // we were unsuccessful on a previous call.
2158 // Try another READER nonce (first 3 parity bits remain the same)
2159 ++mf_nr_ar3;
4c0cf2d2 2160 mf_nr_ar[3] = mf_nr_ar3;
2161 par[0] = par_low;
2162 }
91c7a7cc 2163
2164 bool have_uid = FALSE;
2165 uint8_t cascade_levels = 0;
2166
4c0cf2d2 2167 LED_C_ON();
91c7a7cc 2168 uint16_t i;
2169 for(i = 0; TRUE; ++i) {
4c0cf2d2 2170
1c611bbd 2171 WDT_HIT();
e30c654b 2172
1c611bbd 2173 // Test if the action was cancelled
c830303d 2174 if(BUTTON_PRESS()) {
2175 isOK = -1;
1c611bbd 2176 break;
2177 }
2178
91c7a7cc 2179 // this part is from Piwi's faster nonce collecting part in Hardnested.
2180 if (!have_uid) { // need a full select cycle to get the uid first
2181 iso14a_card_select_t card_info;
2182 if(!iso14443a_select_card(uid, &card_info, &cuid, true, 0)) {
2183 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (ALL)");
2184 break;
2185 }
2186 switch (card_info.uidlen) {
2187 case 4 : cascade_levels = 1; break;
2188 case 7 : cascade_levels = 2; break;
2189 case 10: cascade_levels = 3; break;
2190 default: break;
2191 }
2192 have_uid = TRUE;
2193 } else { // no need for anticollision. We can directly select the card
2194 if(!iso14443a_select_card(uid, NULL, &cuid, false, cascade_levels)) {
2195 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (UID)");
2196 continue;
2197 }
1c611bbd 2198 }
4c0cf2d2 2199
91c7a7cc 2200 // Sending timeslot of ISO14443a frame
2201 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles + catch_up_cycles;
4b78d6b3 2202 catch_up_cycles = 0;
2203
2204 // if we missed the sync time already, advance to the next nonce repeat
91c7a7cc 2205 while( GetCountSspClk() > sync_time) {
4b78d6b3 2206 ++elapsed_prng_sequences;
91c7a7cc 2207 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles;
2208 }
2209
2210 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2211 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2212
91c7a7cc 2213 // Receive the (4 Byte) "random" nonce from TAG
4c0cf2d2 2214 if (!ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2215 continue;
1c611bbd 2216
4b78d6b3 2217 previous_nt = nt;
2218 nt = bytes_to_num(receivedAnswer, 4);
2219
91c7a7cc 2220 // Transmit reader nonce with fake par
2221 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2222
2223 WDT_HIT();
2224 LED_B_ON();
1c611bbd 2225 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
91c7a7cc 2226
2227 nt_distance = dist_nt(previous_nt, nt);
2228
2229 // if no distance between, then we are in sync.
1c611bbd 2230 if (nt_distance == 0) {
2231 nt_attacked = nt;
0de8e387 2232 } else {
c830303d 2233 if (nt_distance == -99999) { // invalid nonce received
91c7a7cc 2234 ++unexpected_random;
3bc7b13d 2235 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
c830303d 2236 isOK = -3; // Card has an unpredictable PRNG. Give up
2237 break;
91c7a7cc 2238 } else {
2239 if (sync_cycles <= 0) sync_cycles += PRNG_SEQUENCE_LENGTH;
2240 LED_B_OFF();
c830303d 2241 continue; // continue trying...
2242 }
1c611bbd 2243 }
4c0cf2d2 2244
0de8e387 2245 if (++sync_tries > MAX_SYNC_TRIES) {
91c7a7cc 2246 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2247 break;
0de8e387 2248 }
4c0cf2d2 2249
4b78d6b3 2250 sync_cycles = (sync_cycles - nt_distance)/elapsed_prng_sequences;
91c7a7cc 2251
4c0cf2d2 2252 if (sync_cycles <= 0)
0de8e387 2253 sync_cycles += PRNG_SEQUENCE_LENGTH;
4c0cf2d2 2254
91c7a7cc 2255 if (MF_DBGLEVEL >= 4)
3bc7b13d 2256 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
4c0cf2d2 2257
91c7a7cc 2258 LED_B_OFF();
1c611bbd 2259 continue;
2260 }
2261 }
91c7a7cc 2262 LED_B_OFF();
1c611bbd 2263
2264 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
4c0cf2d2 2265
91c7a7cc 2266 catch_up_cycles = ABS(dist_nt(nt_attacked, nt));
c830303d 2267 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
1c611bbd 2268 catch_up_cycles = 0;
2269 continue;
91c7a7cc 2270 }
4c0cf2d2 2271 // average?
3bc7b13d 2272 catch_up_cycles /= elapsed_prng_sequences;
4c0cf2d2 2273
1c611bbd 2274 if (catch_up_cycles == last_catch_up) {
4a71da5a 2275 ++consecutive_resyncs;
4c0cf2d2 2276 } else {
1c611bbd 2277 last_catch_up = catch_up_cycles;
2278 consecutive_resyncs = 0;
4b78d6b3 2279 }
4c0cf2d2 2280
1c611bbd 2281 if (consecutive_resyncs < 3) {
91c7a7cc 2282 if (MF_DBGLEVEL >= 4)
2283 Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, catch_up_cycles, consecutive_resyncs);
4c0cf2d2 2284 } else {
2285 sync_cycles += catch_up_cycles;
2286
91c7a7cc 2287 if (MF_DBGLEVEL >= 4)
2288 Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, catch_up_cycles, sync_cycles);
4c0cf2d2 2289
3bc7b13d 2290 last_catch_up = 0;
2291 catch_up_cycles = 0;
2292 consecutive_resyncs = 0;
1c611bbd 2293 }
2294 continue;
2295 }
2296
1c611bbd 2297 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
91c7a7cc 2298 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2299 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2300
495d7f13 2301 if (nt_diff == 0)
6a1f2d82 2302 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2303
6a1f2d82 2304 par_list[nt_diff] = SwapBits(par[0], 8);
91c7a7cc 2305 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; // xor with NACK value to get keystream
1c611bbd 2306
2307 // Test if the information is complete
2308 if (nt_diff == 0x07) {
2309 isOK = 1;
2310 break;
2311 }
2312
2313 nt_diff = (nt_diff + 1) & 0x07;
2314 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2315 par[0] = par_low;
4b78d6b3 2316
1c611bbd 2317 } else {
b0300679 2318 // No NACK.
495d7f13 2319 if (nt_diff == 0 && first_try) {
6a1f2d82 2320 par[0]++;
5ebcb867 2321 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
c830303d 2322 isOK = -2;
2323 break;
2324 }
1c611bbd 2325 } else {
b0300679 2326 // Why this?
6a1f2d82 2327 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2328 }
2329 }
4b78d6b3 2330
91c7a7cc 2331 // reset the resyncs since we got a complete transaction on right time.
4b78d6b3 2332 consecutive_resyncs = 0;
91c7a7cc 2333 } // end for loop
1c611bbd 2334
1c611bbd 2335 mf_nr_ar[3] &= 0x1F;
5ebcb867 2336
bc939371 2337 if (MF_DBGLEVEL >= 4) Dbprintf("Number of sent auth requestes: %u", i);
d26849d4 2338
b0300679 2339 uint8_t buf[28] = {0x00};
91c7a7cc 2340 memset(buf, 0x00, sizeof(buf));
b0300679 2341 num_to_bytes(cuid, 4, buf);
1c611bbd 2342 num_to_bytes(nt, 4, buf + 4);
2343 memcpy(buf + 8, par_list, 8);
2344 memcpy(buf + 16, ks_list, 8);
2345 memcpy(buf + 24, mf_nr_ar, 4);
2346
91c7a7cc 2347 cmd_send(CMD_ACK, isOK, 0, 0, buf, sizeof(buf) );
1c611bbd 2348
1c611bbd 2349 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2350 LEDsoff();
99cf19d9 2351 set_tracing(FALSE);
20f9a2a1 2352}
1c611bbd 2353
0de8e387 2354/**
d2f487af 2355 *MIFARE 1K simulate.
2356 *
2357 *@param flags :
0194ce8f 2358 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2359 * FLAG_4B_UID_IN_DATA - use 4-byte UID in the data-section
2360 * FLAG_7B_UID_IN_DATA - use 7-byte UID in the data-section
2361 * FLAG_10B_UID_IN_DATA - use 10-byte UID in the data-section
2362 * FLAG_UID_IN_EMUL - use 4-byte UID from emulator memory
2363 * FLAG_NR_AR_ATTACK - collect NR_AR responses for bruteforcing later
d2f487af 2364 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2365 */
91c7a7cc 2366void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain) {
50193c1e 2367 int cardSTATE = MFEMUL_NOFIELD;
0194ce8f 2368 int _UID_LEN = 0; // 4, 7, 10
9ca155ba 2369 int vHf = 0; // in mV
0194ce8f 2370 int res = 0;
0a39986e
M
2371 uint32_t selTimer = 0;
2372 uint32_t authTimer = 0;
6a1f2d82 2373 uint16_t len = 0;
8f51ddb0 2374 uint8_t cardWRBL = 0;
9ca155ba
M
2375 uint8_t cardAUTHSC = 0;
2376 uint8_t cardAUTHKEY = 0xff; // no authentication
2377 uint32_t cuid = 0;
51969283 2378 uint32_t ans = 0;
0014cb46
M
2379 uint32_t cardINTREG = 0;
2380 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2381 struct Crypto1State mpcs = {0, 0};
2382 struct Crypto1State *pcs;
2383 pcs = &mpcs;
0194ce8f 2384 uint32_t numReads = 0; //Counts numer of times reader read a block
5ebcb867 2385 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2386 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2387 uint8_t response[MAX_MIFARE_FRAME_SIZE] = {0x00};
2388 uint8_t response_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
9ca155ba 2389
bc939371 2390 uint8_t atqa[] = {0x04, 0x00}; // Mifare classic 1k
2391 uint8_t sak_4[] = {0x0C, 0x00, 0x00}; // CL1 - 4b uid
2392 uint8_t sak_7[] = {0x0C, 0x00, 0x00}; // CL2 - 7b uid
2393 uint8_t sak_10[] = {0x0C, 0x00, 0x00}; // CL3 - 10b uid
0194ce8f 2394 //uint8_t sak[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
2395
2396 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2397 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2398 uint8_t rUIDBCC3[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2399
2400 uint8_t rAUTH_NT[] = {0x01, 0x01, 0x01, 0x01}; // very random nonce
2401 //uint8_t rAUTH_NT[] = {0x55, 0x41, 0x49, 0x92};// nonce from nested? why this?
d2f487af 2402 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
7bc95e2e 2403
bc939371 2404 // Here, we collect CUID, NT, NR, AR, CUID2, NT2, NR2, AR2
d2f487af 2405 // This can be used in a reader-only attack.
bc939371 2406 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0,0};
d2f487af 2407 uint8_t ar_nr_collected = 0;
0014cb46 2408
7bc95e2e 2409 // Authenticate response - nonce
51969283 2410 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
bc939371 2411 ar_nr_responses[1] = nonce;
7bc95e2e 2412
d2f487af 2413 //-- Determine the UID
0194ce8f 2414 // Can be set from emulator memory or incoming data
2415 // Length: 4,7,or 10 bytes
bc939371 2416 if ( (flags & FLAG_UID_IN_EMUL) == FLAG_UID_IN_EMUL)
2417 emlGetMemBt(datain, 0, 10); // load 10bytes from EMUL to the datain pointer. to be used below.
2418
2419 if ( (flags & FLAG_4B_UID_IN_DATA) == FLAG_4B_UID_IN_DATA) {
0194ce8f 2420 memcpy(rUIDBCC1, datain, 4);
2421 _UID_LEN = 4;
bc939371 2422 } else if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA) {
0194ce8f 2423 memcpy(&rUIDBCC1[1], datain, 3);
2424 memcpy( rUIDBCC2, datain+3, 4);
2425 _UID_LEN = 7;
bc939371 2426 } else if ( (flags & FLAG_10B_UID_IN_DATA) == FLAG_10B_UID_IN_DATA) {
0194ce8f 2427 memcpy(&rUIDBCC1[1], datain, 3);
bc939371 2428 memcpy(&rUIDBCC2[1], datain+3, 3);
2429 memcpy( rUIDBCC3, datain+6, 4);
0194ce8f 2430 _UID_LEN = 10;
d2f487af 2431 }
7bc95e2e 2432
0194ce8f 2433 switch (_UID_LEN) {
2434 case 4:
bc939371 2435 sak_4[0] &= 0xFB;
0194ce8f 2436 // save CUID
2437 ar_nr_responses[0] = cuid = bytes_to_num(rUIDBCC1, 4);
2438 // BCC
2439 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
bc939371 2440 if (MF_DBGLEVEL >= 2) {
0194ce8f 2441 Dbprintf("4B UID: %02x%02x%02x%02x",
2442 rUIDBCC1[0],
2443 rUIDBCC1[1],
2444 rUIDBCC1[2],
2445 rUIDBCC1[3]
2446 );
2447 }
2448 break;
2449 case 7:
2450 atqa[0] |= 0x40;
bc939371 2451 sak_7[0] &= 0xFB;
0194ce8f 2452 // save CUID
bc939371 2453 ar_nr_responses[0] = cuid = bytes_to_num(rUIDBCC2, 4);
2454 // CascadeTag, CT
2455 rUIDBCC1[0] = 0x88;
0194ce8f 2456 // BCC
2457 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2458 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
bc939371 2459 if (MF_DBGLEVEL >= 2) {
0194ce8f 2460 Dbprintf("7B UID: %02x %02x %02x %02x %02x %02x %02x",
0194ce8f 2461 rUIDBCC1[1],
2462 rUIDBCC1[2],
2463 rUIDBCC1[3],
2464 rUIDBCC2[0],
2465 rUIDBCC2[1],
2466 rUIDBCC2[2],
2467 rUIDBCC2[3]
2468 );
2469 }
2470 break;
2471 case 10:
bc939371 2472 atqa[0] |= 0x80;
2473 sak_10[0] &= 0xFB;
0194ce8f 2474 // save CUID
2475 ar_nr_responses[0] = cuid = bytes_to_num(rUIDBCC3, 4);
bc939371 2476 // CascadeTag, CT
2477 rUIDBCC1[0] = 0x88;
2478 rUIDBCC2[0] = 0x88;
0194ce8f 2479 // BCC
2480 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
0194ce8f 2481 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2482 rUIDBCC3[4] = rUIDBCC3[0] ^ rUIDBCC3[1] ^ rUIDBCC3[2] ^ rUIDBCC3[3];
bc939371 2483
2484 if (MF_DBGLEVEL >= 2) {
0194ce8f 2485 Dbprintf("10B UID: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
0194ce8f 2486 rUIDBCC1[1],
2487 rUIDBCC1[2],
2488 rUIDBCC1[3],
0194ce8f 2489 rUIDBCC2[1],
2490 rUIDBCC2[2],
2491 rUIDBCC2[3],
2492 rUIDBCC3[0],
2493 rUIDBCC3[1],
2494 rUIDBCC3[2],
2495 rUIDBCC3[3]
2496 );
2497 }
2498 break;
2499 default:
2500 break;
d2f487af 2501 }
bc939371 2502 // calc some crcs
2503 ComputeCrc14443(CRC_14443_A, sak_4, 1, &sak_4[1], &sak_4[2]);
2504 ComputeCrc14443(CRC_14443_A, sak_7, 1, &sak_7[1], &sak_7[2]);
2505 ComputeCrc14443(CRC_14443_A, sak_10, 1, &sak_10[1], &sak_10[2]);
2506
99cf19d9 2507 // We need to listen to the high-frequency, peak-detected path.
2508 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2509
2510 // free eventually allocated BigBuf memory but keep Emulator Memory
2511 BigBuf_free_keep_EM();
99cf19d9 2512 clear_trace();
2513 set_tracing(TRUE);
2514
7bc95e2e 2515 bool finished = FALSE;
2b1f4228 2516 while (!BUTTON_PRESS() && !finished && !usb_poll_validate_length()) {
9ca155ba 2517 WDT_HIT();
9ca155ba
M
2518
2519 // find reader field
9ca155ba 2520 if (cardSTATE == MFEMUL_NOFIELD) {
0c8d25eb 2521 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
9ca155ba 2522 if (vHf > MF_MINFIELDV) {
0014cb46 2523 cardSTATE_TO_IDLE();
9ca155ba
M
2524 LED_A_ON();
2525 }
2526 }
0194ce8f 2527 if (cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2528
d2f487af 2529 //Now, get data
6a1f2d82 2530 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2531 if (res == 2) { //Field is off!
2532 cardSTATE = MFEMUL_NOFIELD;
2533 LEDsoff();
2534 continue;
7bc95e2e 2535 } else if (res == 1) {
2536 break; //return value 1 means button press
2537 }
2538
d2f487af 2539 // REQ or WUP request in ANY state and WUP in HALTED state
0194ce8f 2540 if (len == 1 && ((receivedCmd[0] == ISO14443A_CMD_REQA && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == ISO14443A_CMD_WUPA)) {
d2f487af 2541 selTimer = GetTickCount();
0194ce8f 2542 EmSendCmdEx(atqa, sizeof(atqa), (receivedCmd[0] == ISO14443A_CMD_WUPA));
d2f487af 2543 cardSTATE = MFEMUL_SELECT1;
d2f487af 2544 crypto1_destroy(pcs);
2545 cardAUTHKEY = 0xff;
0194ce8f 2546 LEDsoff();
bc939371 2547 nonce++;
d2f487af 2548 continue;
0a39986e 2549 }
7bc95e2e 2550
50193c1e 2551 switch (cardSTATE) {
d2f487af 2552 case MFEMUL_NOFIELD:
2553 case MFEMUL_HALTED:
50193c1e 2554 case MFEMUL_IDLE:{
6a1f2d82 2555 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2556 break;
2557 }
2558 case MFEMUL_SELECT1:{
0194ce8f 2559 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT && receivedCmd[1] == 0x20)) {
d2f487af 2560 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2561 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2562 break;
9ca155ba 2563 }
9ca155ba 2564 // select card
0a39986e 2565 if (len == 9 &&
0194ce8f 2566 ( receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT &&
2567 receivedCmd[1] == 0x70 &&
2568 memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2569
2570 // SAK 4b
2571 EmSendCmd(sak_4, sizeof(sak_4));
2572 switch(_UID_LEN){
2573 case 4:
2574 cardSTATE = MFEMUL_WORK;
2575 LED_B_ON();
2576 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2577 continue;
2578 case 7:
2579 case 10:
2580 cardSTATE = MFEMUL_SELECT2;
2581 continue;
2582 default:break;
8556b852 2583 }
0194ce8f 2584 } else {
2585 cardSTATE_TO_IDLE();
2586 }
2587 break;
2588 }
2589 case MFEMUL_SELECT2:{
2590 if (!len) {
2591 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2592 break;
2593 }
2594 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 && receivedCmd[1] == 0x20)) {
2595 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2596 break;
2597 }
2598 if (len == 9 &&
2599 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 &&
2600 receivedCmd[1] == 0x70 &&
2601 memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0) ) {
2602
2603 EmSendCmd(sak_7, sizeof(sak_7));
2604 switch(_UID_LEN){
2605 case 7:
2606 cardSTATE = MFEMUL_WORK;
2607 LED_B_ON();
2608 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2609 continue;
2610 case 10:
2611 cardSTATE = MFEMUL_SELECT3;
2612 continue;
2613 default:break;
2614 }
bc939371 2615 }
2616 cardSTATE_TO_IDLE();
0194ce8f 2617 break;
2618 }
2619 case MFEMUL_SELECT3:{
2620 if (!len) {
2621 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2622 break;
2623 }
2624 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 && receivedCmd[1] == 0x20)) {
2625 EmSendCmd(rUIDBCC3, sizeof(rUIDBCC3));
2626 break;
2627 }
2628 if (len == 9 &&
2629 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 &&
2630 receivedCmd[1] == 0x70 &&
2631 memcmp(&receivedCmd[2], rUIDBCC3, 4) == 0) ) {
2632
2633 EmSendCmd(sak_10, sizeof(sak_10));
2634 cardSTATE = MFEMUL_WORK;
2635 LED_B_ON();
2636 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol3 time: %d", GetTickCount() - selTimer);
2637 break;
9ca155ba 2638 }
bc939371 2639 cardSTATE_TO_IDLE();
50193c1e
M
2640 break;
2641 }
d2f487af 2642 case MFEMUL_AUTH1:{
495d7f13 2643 if( len != 8) {
d2f487af 2644 cardSTATE_TO_IDLE();
6a1f2d82 2645 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2646 break;
2647 }
0c8d25eb 2648
bc939371 2649 uint32_t nr = bytes_to_num(receivedCmd, 4);
2650 uint32_t ar = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2651
2652 //Collect AR/NR
46cd801c 2653 //if(ar_nr_collected < 2 && cardAUTHSC == 2){
bc939371 2654 if(ar_nr_collected < 2) {
2655 //if(ar_nr_responses[2] != nr) {
2656 ar_nr_responses[ar_nr_collected*4] = cuid;
2657 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2658 ar_nr_responses[ar_nr_collected*4+2] = nr;
2659 ar_nr_responses[ar_nr_collected*4+3] = ar;
273b57a7 2660 ar_nr_collected++;
bc939371 2661 //}
2662
12d708fe 2663 // Interactive mode flag, means we need to send ACK
bc939371 2664 finished = ( ((flags & FLAG_INTERACTIVE) == FLAG_INTERACTIVE)&& ar_nr_collected == 2);
d2f487af 2665 }
0194ce8f 2666 /*
2667 crypto1_word(pcs, ar , 1);
2668 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2669
2670 test if auth OK
2671 if (cardRr != prng_successor(nonce, 64)){
c3c241f3 2672
0194ce8f 2673 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2674 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2675 cardRr, prng_successor(nonce, 64));
2676 Shouldn't we respond anything here?
2677 Right now, we don't nack or anything, which causes the
2678 reader to do a WUPA after a while. /Martin
2679 -- which is the correct response. /piwi
2680 cardSTATE_TO_IDLE();
2681 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2682 break;
2683 }
2684 */
2685
d2f487af 2686 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
d2f487af 2687 num_to_bytes(ans, 4, rAUTH_AT);
d2f487af 2688 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2689 LED_C_ON();
bc939371 2690
495d7f13 2691 if (MF_DBGLEVEL >= 4) {
2692 Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2693 cardAUTHSC,
2694 cardAUTHKEY == 0 ? 'A' : 'B',
2695 GetTickCount() - authTimer
2696 );
2697 }
0014cb46 2698 cardSTATE = MFEMUL_WORK;
0194ce8f 2699 break;
50193c1e 2700 }
7bc95e2e 2701 case MFEMUL_WORK:{
2702 if (len == 0) {
6a1f2d82 2703 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2704 break;
0194ce8f 2705 }
d2f487af 2706 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2707
495d7f13 2708 if(encrypted_data)
51969283 2709 mf_crypto1_decrypt(pcs, receivedCmd, len);
7bc95e2e 2710
0194ce8f 2711 if (len == 4 && (receivedCmd[0] == MIFARE_AUTH_KEYA ||
2712 receivedCmd[0] == MIFARE_AUTH_KEYB) ) {
2713
d2f487af 2714 authTimer = GetTickCount();
2715 cardAUTHSC = receivedCmd[1] / 4; // received block num
0194ce8f 2716 cardAUTHKEY = receivedCmd[0] - 0x60; // & 1
2717 crypto1_destroy(pcs);
d2f487af 2718 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2719
0194ce8f 2720 if (!encrypted_data) {
2721 // first authentication
d2f487af 2722 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2723 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
0194ce8f 2724
2725 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2726
2727 } else {
2728 // nested authentication
7bc95e2e 2729 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2730 num_to_bytes(ans, 4, rAUTH_AT);
0194ce8f 2731
2732 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
d2f487af 2733 }
0c8d25eb 2734
d2f487af 2735 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
d2f487af 2736 cardSTATE = MFEMUL_AUTH1;
2737 break;
51969283 2738 }
7bc95e2e 2739
8f51ddb0
M
2740 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2741 // BUT... ACK --> NACK
2742 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2743 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2744 break;
2745 }
2746
2747 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2748 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2749 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2750 break;
0a39986e
M
2751 }
2752
7bc95e2e 2753 if(len != 4) {
6a1f2d82 2754 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2755 break;
2756 }
d2f487af 2757
0194ce8f 2758 if ( receivedCmd[0] == ISO14443A_CMD_READBLOCK ||
2759 receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK ||
2760 receivedCmd[0] == MIFARE_CMD_INC ||
2761 receivedCmd[0] == MIFARE_CMD_DEC ||
2762 receivedCmd[0] == MIFARE_CMD_RESTORE ||
2763 receivedCmd[0] == MIFARE_CMD_TRANSFER ) {
2764
7bc95e2e 2765 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2766 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2767 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2768 break;
2769 }
2770
7bc95e2e 2771 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2772 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2773 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2774 break;
2775 }
d2f487af 2776 }
2777 // read block
0194ce8f 2778 if (receivedCmd[0] == ISO14443A_CMD_READBLOCK) {
2779 if (MF_DBGLEVEL >= 4) Dbprintf("Reader reading block %d (0x%02x)", receivedCmd[1], receivedCmd[1]);
495d7f13 2780
8f51ddb0
M
2781 emlGetMem(response, receivedCmd[1], 1);
2782 AppendCrc14443a(response, 16);
6a1f2d82 2783 mf_crypto1_encrypt(pcs, response, 18, response_par);
2784 EmSendCmdPar(response, 18, response_par);
d2f487af 2785 numReads++;
12d708fe 2786 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
d2f487af 2787 Dbprintf("%d reads done, exiting", numReads);
2788 finished = true;
2789 }
0a39986e
M
2790 break;
2791 }
0a39986e 2792 // write block
0194ce8f 2793 if (receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK) {
2794 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)", receivedCmd[1], receivedCmd[1]);
8f51ddb0 2795 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2796 cardSTATE = MFEMUL_WRITEBL2;
2797 cardWRBL = receivedCmd[1];
0a39986e 2798 break;
7bc95e2e 2799 }
0014cb46 2800 // increment, decrement, restore
0194ce8f 2801 if ( receivedCmd[0] == MIFARE_CMD_INC ||
2802 receivedCmd[0] == MIFARE_CMD_DEC ||
2803 receivedCmd[0] == MIFARE_CMD_RESTORE) {
2804
2805 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2806
d2f487af 2807 if (emlCheckValBl(receivedCmd[1])) {
c3c241f3 2808 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2809 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2810 break;
2811 }
2812 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0194ce8f 2813 if (receivedCmd[0] == MIFARE_CMD_INC) cardSTATE = MFEMUL_INTREG_INC;
2814 if (receivedCmd[0] == MIFARE_CMD_DEC) cardSTATE = MFEMUL_INTREG_DEC;
2815 if (receivedCmd[0] == MIFARE_CMD_RESTORE) cardSTATE = MFEMUL_INTREG_REST;
0014cb46 2816 cardWRBL = receivedCmd[1];
0014cb46
M
2817 break;
2818 }
0014cb46 2819 // transfer
0194ce8f 2820 if (receivedCmd[0] == MIFARE_CMD_TRANSFER) {
2821 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)", receivedCmd[0], receivedCmd[1], receivedCmd[1]);
0014cb46
M
2822 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2823 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2824 else
2825 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2826 break;
2827 }
9ca155ba 2828 // halt
0194ce8f 2829 if (receivedCmd[0] == ISO14443A_CMD_HALT && receivedCmd[1] == 0x00) {
9ca155ba 2830 LED_B_OFF();
0a39986e 2831 LED_C_OFF();
0014cb46
M
2832 cardSTATE = MFEMUL_HALTED;
2833 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2834 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2835 break;
9ca155ba 2836 }
d2f487af 2837 // RATS
0194ce8f 2838 if (receivedCmd[0] == ISO14443A_CMD_RATS) {
8f51ddb0
M
2839 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2840 break;
2841 }
d2f487af 2842 // command not allowed
2843 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2844 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2845 break;
8f51ddb0
M
2846 }
2847 case MFEMUL_WRITEBL2:{
495d7f13 2848 if (len == 18) {
8f51ddb0
M
2849 mf_crypto1_decrypt(pcs, receivedCmd, len);
2850 emlSetMem(receivedCmd, cardWRBL, 1);
2851 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2852 cardSTATE = MFEMUL_WORK;
51969283 2853 } else {
0014cb46 2854 cardSTATE_TO_IDLE();
6a1f2d82 2855 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2856 }
8f51ddb0 2857 break;
50193c1e 2858 }
0014cb46
M
2859 case MFEMUL_INTREG_INC:{
2860 mf_crypto1_decrypt(pcs, receivedCmd, len);
2861 memcpy(&ans, receivedCmd, 4);
2862 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2863 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2864 cardSTATE_TO_IDLE();
2865 break;
7bc95e2e 2866 }
6a1f2d82 2867 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2868 cardINTREG = cardINTREG + ans;
2869 cardSTATE = MFEMUL_WORK;
2870 break;
2871 }
2872 case MFEMUL_INTREG_DEC:{
2873 mf_crypto1_decrypt(pcs, receivedCmd, len);
2874 memcpy(&ans, receivedCmd, 4);
2875 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2876 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2877 cardSTATE_TO_IDLE();
2878 break;
2879 }
6a1f2d82 2880 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2881 cardINTREG = cardINTREG - ans;
2882 cardSTATE = MFEMUL_WORK;
2883 break;
2884 }
2885 case MFEMUL_INTREG_REST:{
2886 mf_crypto1_decrypt(pcs, receivedCmd, len);
2887 memcpy(&ans, receivedCmd, 4);
2888 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2889 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2890 cardSTATE_TO_IDLE();
2891 break;
2892 }
6a1f2d82 2893 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2894 cardSTATE = MFEMUL_WORK;
2895 break;
2896 }
50193c1e 2897 }
50193c1e
M
2898 }
2899
810f5379 2900 // Interactive mode flag, means we need to send ACK
bc939371 2901 if((flags & FLAG_INTERACTIVE) == FLAG_INTERACTIVE) {
d2f487af 2902 //May just aswell send the collected ar_nr in the response aswell
bc939371 2903 uint8_t len = ar_nr_collected * 4 * 4;
c3c241f3 2904 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
d2f487af 2905 }
d714d3ef 2906
bc939371 2907 if( ((flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) && MF_DBGLEVEL >= 1 ) {
12d708fe 2908 if(ar_nr_collected > 1 ) {
d2f487af 2909 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
bc939371 2910 Dbprintf("../tools/mfkey/mfkey32v2.exe %08x %08x %08x %08x %08x %08x %08x",
0194ce8f 2911 ar_nr_responses[0], // CUID
bc939371 2912 ar_nr_responses[1], // NT1
2913 ar_nr_responses[2], // NR1
2914 ar_nr_responses[3], // AR1
2915 //ar_nr_responses[4], // CUID2
2916 ar_nr_responses[5], // NT2
2917 ar_nr_responses[6], // NR2
2918 ar_nr_responses[7] // AR2
0194ce8f 2919 );
7bc95e2e 2920 } else {
d2f487af 2921 Dbprintf("Failed to obtain two AR/NR pairs!");
bc939371 2922 if(ar_nr_collected == 1 ) {
2923 Dbprintf("Only got these: UID=%08x, nonce=%08x, NR1=%08x, AR1=%08x",
0194ce8f 2924 ar_nr_responses[0], // CUID
2925 ar_nr_responses[1], // NT
bc939371 2926 ar_nr_responses[2], // NR1
2927 ar_nr_responses[3] // AR1
0194ce8f 2928 );
d2f487af 2929 }
2930 }
2931 }
0194ce8f 2932 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
5ee53a0e 2933
91c7a7cc 2934 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2935 LEDsoff();
5ee53a0e 2936 set_tracing(FALSE);
15c4dc5a 2937}
b62a5a84 2938
d2f487af 2939
b62a5a84
M
2940//-----------------------------------------------------------------------------
2941// MIFARE sniffer.
2942//
0194ce8f 2943// if no activity for 2sec, it sends the collected data to the client.
b62a5a84 2944//-----------------------------------------------------------------------------
bc939371 2945// "hf mf sniff"
5cd9ec01 2946void RAMFUNC SniffMifare(uint8_t param) {
bc939371 2947
b62a5a84 2948 LEDsoff();
810f5379 2949
aaa1a9a2 2950 // free eventually allocated BigBuf memory
2951 BigBuf_free(); BigBuf_Clear_ext(false);
3000dc4e
MHS
2952 clear_trace();
2953 set_tracing(TRUE);
b62a5a84 2954
b62a5a84 2955 // The command (reader -> tag) that we're receiving.
810f5379 2956 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
495d7f13 2957 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
810f5379 2958
b62a5a84 2959 // The response (tag -> reader) that we're receiving.
495d7f13 2960 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE] = {0x00};
2961 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b62a5a84 2962
99cf19d9 2963 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2964
f71f4deb 2965 // allocate the DMA buffer, used to stream samples from the FPGA
0194ce8f 2966 // [iceman] is this sniffed data unsigned?
f71f4deb 2967 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 2968 uint8_t *data = dmaBuf;
2969 uint8_t previous_data = 0;
5cd9ec01
M
2970 int maxDataLen = 0;
2971 int dataLen = 0;
7bc95e2e 2972 bool ReaderIsActive = FALSE;
2973 bool TagIsActive = FALSE;
2974
b62a5a84 2975 // Set up the demodulator for tag -> reader responses.
6a1f2d82 2976 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
2977
2978 // Set up the demodulator for the reader -> tag commands
6a1f2d82 2979 UartInit(receivedCmd, receivedCmdPar);
b62a5a84 2980
0194ce8f 2981 // set transfer address and number of bytes. Start transfer.
2982 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
b62a5a84 2983
b62a5a84 2984 LED_D_OFF();
0194ce8f 2985
39864b0b 2986 MfSniffInit();
b62a5a84 2987
b62a5a84 2988 // And now we loop, receiving samples.
0194ce8f 2989 for(uint32_t sniffCounter = 0;; ) {
91c7a7cc 2990
2991 LED_A_ON();
2992 WDT_HIT();
7bc95e2e 2993
5cd9ec01
M
2994 if(BUTTON_PRESS()) {
2995 DbpString("cancelled by button");
7bc95e2e 2996 break;
5cd9ec01 2997 }
91c7a7cc 2998
7bc95e2e 2999 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3000 // check if a transaction is completed (timeout after 2000ms).
3001 // if yes, stop the DMA transfer and send what we have so far to the client
3002 if (MfSniffSend(2000)) {
3003 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3004 sniffCounter = 0;
3005 data = dmaBuf;
3006 maxDataLen = 0;
3007 ReaderIsActive = FALSE;
3008 TagIsActive = FALSE;
3009 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 3010 }
39864b0b 3011 }
7bc95e2e 3012
3013 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3014 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
495d7f13 3015
3016 if (readBufDataP <= dmaBufDataP) // we are processing the same block of data which is currently being transferred
7bc95e2e 3017 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
495d7f13 3018 else
7bc95e2e 3019 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
495d7f13 3020
5cd9ec01 3021 // test for length of buffer
7bc95e2e 3022 if(dataLen > maxDataLen) { // we are more behind than ever...
3023 maxDataLen = dataLen;
f71f4deb 3024 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 3025 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 3026 break;
b62a5a84
M
3027 }
3028 }
5cd9ec01 3029 if(dataLen < 1) continue;
b62a5a84 3030
7bc95e2e 3031 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
3032 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3033 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3034 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
91c7a7cc 3035 Dbprintf("RxEmpty ERROR, data length:%d", dataLen); // temporary
5cd9ec01
M
3036 }
3037 // secondary buffer sets as primary, secondary buffer was stopped
3038 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3039 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
3040 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3041 }
5cd9ec01
M
3042
3043 LED_A_OFF();
b62a5a84 3044
7bc95e2e 3045 if (sniffCounter & 0x01) {
b62a5a84 3046
495d7f13 3047 // no need to try decoding tag data if the reader is sending
3048 if(!TagIsActive) {
7bc95e2e 3049 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3050 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3051 LED_C_INV();
495d7f13 3052
6a1f2d82 3053 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 3054
f8ada309 3055 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3056 DemodReset();
3057 }
3058 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3059 }
3060
495d7f13 3061 // no need to try decoding tag data if the reader is sending
3062 if(!ReaderIsActive) {
7bc95e2e 3063 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3064 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3065 LED_C_INV();
b62a5a84 3066
6a1f2d82 3067 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 3068
7bc95e2e 3069 DemodReset();
0ec548dc 3070 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3071 }
3072 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3073 }
b62a5a84
M
3074 }
3075
7bc95e2e 3076 previous_data = *data;
3077 sniffCounter++;
5cd9ec01 3078 data++;
495d7f13 3079
3080 if(data == dmaBuf + DMA_BUFFER_SIZE)
5cd9ec01 3081 data = dmaBuf;
7bc95e2e 3082
b62a5a84 3083 } // main cycle
bc939371 3084
3085 if (MF_DBGLEVEL >= 1) Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3086
55acbb2a 3087 FpgaDisableSscDma();
39864b0b 3088 MfSniffEnd();
91c7a7cc 3089 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3090 LEDsoff();
5ee53a0e 3091 set_tracing(FALSE);
3803d529 3092}
Impressum, Datenschutz