NET "PHY_CLOCK" LOC = "L5" | IOSTANDARD = LVCMOS33;
NET "LED_2" LOC = "AB5" | IOSTANDARD = LVTTL | DRIVE = 24 ;
+
+INST DCM_INST CLK_FEEDBACK = 1X;
+INST DCM_INST CLKDV_DIVIDE = 2.0;
+INST DCM_INST CLKFX_DIVIDE = 29;
+INST DCM_INST CLKFX_MULTIPLY = 22;
+INST DCM_INST CLKIN_DIVIDE_BY_2 = FALSE;
+INST DCM_INST CLKIN_PERIOD = 30.303;
+INST DCM_INST CLKOUT_PHASE_SHIFT = NONE;
+INST DCM_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
+INST DCM_INST DFS_FREQUENCY_MODE = LOW;
+INST DCM_INST DLL_FREQUENCY_MODE = LOW;
+INST DCM_INST DUTY_CYCLE_CORRECTION = TRUE;
+INST DCM_INST FACTORY_JF = 8080;
+INST DCM_INST PHASE_SHIFT = 0;
+INST DCM_INST STARTUP_WAIT = FALSE;
--- /dev/null
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 9.1.02i
+-- \ \ Application : xaw2vhdl
+-- / / Filename : phydcm.vhd
+-- /___/ /\ Timestamp : 03/21/2007 14:47:39
+-- \ \ / \
+-- \___\/\___\
+--
+--Command: xaw2vhdl-st phydcm.xaw phydcm
+--Design Name: phydcm
+--Device: xc3s1500-fg456-4
+--
+-- Module phydcm
+-- Generated by Xilinx Architecture Wizard
+-- Written for synthesis tool: XST
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity phydcm is
+ port ( CLKIN_IN : in std_logic;
+ RST_IN : in std_logic;
+ CLKFX_OUT : out std_logic;
+ CLKIN_IBUFG_OUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ LOCKED_OUT : out std_logic);
+end phydcm;
+
+architecture BEHAVIORAL of phydcm is
+ signal CLKFB_IN : std_logic;
+ signal CLKFX_BUF : std_logic;
+ signal CLKIN_IBUFG : std_logic;
+ signal CLK0_BUF : std_logic;
+ signal GND_BIT : std_logic;
+ component BUFG
+ port ( I : in std_logic;
+ O : out std_logic);
+ end component;
+
+ component IBUFG
+ port ( I : in std_logic;
+ O : out std_logic);
+ end component;
+
+ -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI
+ -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns
+ component DCM
+ generic( CLK_FEEDBACK : string := "1X";
+ CLKDV_DIVIDE : real := 2.0;
+ CLKFX_DIVIDE : integer := 1;
+ CLKFX_MULTIPLY : integer := 4;
+ CLKIN_DIVIDE_BY_2 : boolean := FALSE;
+ CLKIN_PERIOD : real := 10.0;
+ CLKOUT_PHASE_SHIFT : string := "NONE";
+ DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
+ DFS_FREQUENCY_MODE : string := "LOW";
+ DLL_FREQUENCY_MODE : string := "LOW";
+ DUTY_CYCLE_CORRECTION : boolean := TRUE;
+ FACTORY_JF : bit_vector := x"C080";
+ PHASE_SHIFT : integer := 0;
+ STARTUP_WAIT : boolean := FALSE;
+ DSS_MODE : string := "NONE");
+ port ( CLKIN : in std_logic;
+ CLKFB : in std_logic;
+ RST : in std_logic;
+ PSEN : in std_logic;
+ PSINCDEC : in std_logic;
+ PSCLK : in std_logic;
+ DSSEN : in std_logic;
+ CLK0 : out std_logic;
+ CLK90 : out std_logic;
+ CLK180 : out std_logic;
+ CLK270 : out std_logic;
+ CLKDV : out std_logic;
+ CLK2X : out std_logic;
+ CLK2X180 : out std_logic;
+ CLKFX : out std_logic;
+ CLKFX180 : out std_logic;
+ STATUS : out std_logic_vector (7 downto 0);
+ LOCKED : out std_logic;
+ PSDONE : out std_logic);
+ end component;
+
+begin
+ GND_BIT <= '0';
+ CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
+ CLK0_OUT <= CLKFB_IN;
+ CLKFX_BUFG_INST : BUFG
+ port map (I=>CLKFX_BUF,
+ O=>CLKFX_OUT);
+
+ CLKIN_IBUFG_INST : IBUFG
+ port map (I=>CLKIN_IN,
+ O=>CLKIN_IBUFG);
+
+ CLK0_BUFG_INST : BUFG
+ port map (I=>CLK0_BUF,
+ O=>CLKFB_IN);
+
+ DCM_INST : DCM
+ generic map( CLK_FEEDBACK => "1X",
+ CLKDV_DIVIDE => 2.0,
+ CLKFX_DIVIDE => 29,
+ CLKFX_MULTIPLY => 22,
+ CLKIN_DIVIDE_BY_2 => FALSE,
+ CLKIN_PERIOD => 30.303,
+ CLKOUT_PHASE_SHIFT => "NONE",
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+ DFS_FREQUENCY_MODE => "LOW",
+ DLL_FREQUENCY_MODE => "LOW",
+ DUTY_CYCLE_CORRECTION => TRUE,
+ FACTORY_JF => x"8080",
+ PHASE_SHIFT => 0,
+ STARTUP_WAIT => FALSE)
+ port map (CLKFB=>CLKFB_IN,
+ CLKIN=>CLKIN_IBUFG,
+ DSSEN=>GND_BIT,
+ PSCLK=>GND_BIT,
+ PSEN=>GND_BIT,
+ PSINCDEC=>GND_BIT,
+ RST=>RST_IN,
+ CLKDV=>open,
+ CLKFX=>CLKFX_BUF,
+ CLKFX180=>open,
+ CLK0=>CLK0_BUF,
+ CLK2X=>open,
+ CLK2X180=>open,
+ CLK90=>open,
+ CLK180=>open,
+ CLK270=>open,
+ LOCKED=>LOCKED_OUT,
+ PSDONE=>open,
+ STATUS=>open);
+
+end BEHAVIORAL;
+
+
);
end component;
+component phydcm is
+port ( CLKIN_IN : in std_logic;
+ RST_IN : in std_logic;
+ CLKFX_OUT : out std_logic;
+ CLKIN_IBUFG_OUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ LOCKED_OUT : out std_logic);
+end component;
+
signal pci_rst_o : std_logic;
signal pci_rst_oe_o : std_logic;
signal pci_inta_o : std_logic;
wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2);
wb_clk_i <= PCI_CLOCK;
-PHY_CLOCK <= PCI_CLOCK;
data(31 downto 0) <= wbm_adr_o;
data(40 downto 33) <= wbm_adr_o (7 downto 0);
trig0 => trig0
);
+eth_dcm : phydcm
+port map (
+ CLKIN_IN => PCI_CLOCK,
+ RST_IN => not PCI_RSTn,
+ CLKFX_OUT => PHY_CLOCK
+-- CLKIN_IBUFG_OUT
+-- CLK0_OUT
+-- LOCKED_OUT
+ );
+
end architecture ethernet_arch;
projects / raggedstone / commitdiff