]> git.zerfleddert.de Git - proxmark3-svn/blame - armsrc/iso14443a.c
lf hid fskdemod bug
[proxmark3-svn] / armsrc / iso14443a.c
CommitLineData
15c4dc5a 1//-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
e30c654b 13#include "proxmark3.h"
15c4dc5a 14#include "apps.h"
f7e3ed82 15#include "util.h"
9ab7a6c7 16#include "string.h"
902cb3c0 17#include "cmd.h"
9ab7a6c7 18
15c4dc5a 19#include "iso14443crc.h"
534983d7 20#include "iso14443a.h"
20f9a2a1
M
21#include "crapto1.h"
22#include "mifareutil.h"
15c4dc5a 23
534983d7 24static uint32_t iso14a_timeout;
1e262141 25int rsamples = 0;
26int tracing = TRUE;
27uint8_t trigger = 0;
b0127e65 28// the block number for the ISO14443-4 PCB
29static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 30
7bc95e2e 31//
32// ISO14443 timing:
33//
34// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
35#define REQUEST_GUARD_TIME (7000/16 + 1)
36// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
37#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
38// bool LastCommandWasRequest = FALSE;
39
40//
41// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
42//
d714d3ef 43// When the PM acts as reader and is receiving tag data, it takes
44// 3 ticks delay in the AD converter
45// 16 ticks until the modulation detector completes and sets curbit
46// 8 ticks until bit_to_arm is assigned from curbit
47// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 48// 4*16 ticks until we measure the time
49// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 50#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 51
52// When the PM acts as a reader and is sending, it takes
53// 4*16 ticks until we can write data to the sending hold register
54// 8*16 ticks until the SHR is transferred to the Sending Shift Register
55// 8 ticks until the first transfer starts
56// 8 ticks later the FPGA samples the data
57// 1 tick to assign mod_sig_coil
58#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
59
60// When the PM acts as tag and is receiving it takes
d714d3ef 61// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 62// 3 ticks for the A/D conversion,
63// 8 ticks on average until the start of the SSC transfer,
64// 8 ticks until the SSC samples the first data
65// 7*16 ticks to complete the transfer from FPGA to ARM
66// 8 ticks until the next ssp_clk rising edge
d714d3ef 67// 4*16 ticks until we measure the time
7bc95e2e 68// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 69#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 70
71// The FPGA will report its internal sending delay in
72uint16_t FpgaSendQueueDelay;
73// the 5 first bits are the number of bits buffered in mod_sig_buf
74// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
75#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
76
77// When the PM acts as tag and is sending, it takes
d714d3ef 78// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 79// 8*16 ticks until the SHR is transferred to the Sending Shift Register
80// 8 ticks until the first transfer starts
81// 8 ticks later the FPGA samples the data
82// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
83// + 1 tick to assign mod_sig_coil
d714d3ef 84#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 85
86// When the PM acts as sniffer and is receiving tag data, it takes
87// 3 ticks A/D conversion
d714d3ef 88// 14 ticks to complete the modulation detection
89// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 90// + the delays in transferring data - which is the same for
91// sniffing reader and tag data and therefore not relevant
d714d3ef 92#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 93
d714d3ef 94// When the PM acts as sniffer and is receiving reader data, it takes
95// 2 ticks delay in analogue RF receiver (for the falling edge of the
96// start bit, which marks the start of the communication)
7bc95e2e 97// 3 ticks A/D conversion
d714d3ef 98// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 99// + the delays in transferring data - which is the same for
100// sniffing reader and tag data and therefore not relevant
d714d3ef 101#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 102
103//variables used for timing purposes:
104//these are in ssp_clk cycles:
6a1f2d82 105static uint32_t NextTransferTime;
106static uint32_t LastTimeProxToAirStart;
107static uint32_t LastProxToAirDuration;
7bc95e2e 108
109
110
8f51ddb0 111// CARD TO READER - manchester
72934aa3 112// Sequence D: 11110000 modulation with subcarrier during first half
113// Sequence E: 00001111 modulation with subcarrier during second half
114// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 115// READER TO CARD - miller
72934aa3 116// Sequence X: 00001100 drop after half a period
117// Sequence Y: 00000000 no drop
118// Sequence Z: 11000000 drop at start
119#define SEC_D 0xf0
120#define SEC_E 0x0f
121#define SEC_F 0x00
122#define SEC_X 0x0c
123#define SEC_Y 0x00
124#define SEC_Z 0xc0
15c4dc5a 125
1e262141 126const uint8_t OddByteParity[256] = {
15c4dc5a 127 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
130 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
131 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
138 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
139 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
142 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
143};
144
902cb3c0 145void iso14a_set_trigger(bool enable) {
534983d7 146 trigger = enable;
147}
148
902cb3c0 149void iso14a_clear_trace() {
117d9ec2 150 uint8_t *trace = BigBuf_get_addr();
f71f4deb 151 uint16_t max_traceLen = BigBuf_max_traceLen();
152 memset(trace, 0x44, max_traceLen);
8556b852
M
153 traceLen = 0;
154}
d19929cb 155
902cb3c0 156void iso14a_set_tracing(bool enable) {
8556b852
M
157 tracing = enable;
158}
d19929cb 159
b0127e65 160void iso14a_set_timeout(uint32_t timeout) {
161 iso14a_timeout = timeout;
162}
8556b852 163
15c4dc5a 164//-----------------------------------------------------------------------------
165// Generate the parity value for a byte sequence
e30c654b 166//
15c4dc5a 167//-----------------------------------------------------------------------------
20f9a2a1
M
168byte_t oddparity (const byte_t bt)
169{
5f6d6c90 170 return OddByteParity[bt];
20f9a2a1
M
171}
172
6a1f2d82 173void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
15c4dc5a 174{
6a1f2d82 175 uint16_t paritybit_cnt = 0;
176 uint16_t paritybyte_cnt = 0;
177 uint8_t parityBits = 0;
178
179 for (uint16_t i = 0; i < iLen; i++) {
180 // Generate the parity bits
181 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
182 if (paritybit_cnt == 7) {
183 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
184 parityBits = 0; // and advance to next Parity Byte
185 paritybyte_cnt++;
186 paritybit_cnt = 0;
187 } else {
188 paritybit_cnt++;
189 }
5f6d6c90 190 }
6a1f2d82 191
192 // save remaining parity bits
193 par[paritybyte_cnt] = parityBits;
194
15c4dc5a 195}
196
534983d7 197void AppendCrc14443a(uint8_t* data, int len)
15c4dc5a 198{
5f6d6c90 199 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 200}
201
1e262141 202// The function LogTrace() is also used by the iClass implementation in iClass.c
6a1f2d82 203bool RAMFUNC LogTrace(const uint8_t *btBytes, uint16_t iLen, uint32_t timestamp_start, uint32_t timestamp_end, uint8_t *parity, bool readerToTag)
15c4dc5a 204{
fdcd43eb 205 if (!tracing) return FALSE;
6a1f2d82 206
117d9ec2 207 uint8_t *trace = BigBuf_get_addr();
6a1f2d82 208 uint16_t num_paritybytes = (iLen-1)/8 + 1; // number of valid paritybytes in *parity
209 uint16_t duration = timestamp_end - timestamp_start;
210
7bc95e2e 211 // Return when trace is full
f71f4deb 212 uint16_t max_traceLen = BigBuf_max_traceLen();
213 if (traceLen + sizeof(iLen) + sizeof(timestamp_start) + sizeof(duration) + num_paritybytes + iLen >= max_traceLen) {
7bc95e2e 214 tracing = FALSE; // don't trace any more
215 return FALSE;
216 }
217
6a1f2d82 218 // Traceformat:
219 // 32 bits timestamp (little endian)
220 // 16 bits duration (little endian)
221 // 16 bits data length (little endian, Highest Bit used as readerToTag flag)
222 // y Bytes data
223 // x Bytes parity (one byte per 8 bytes data)
224
225 // timestamp (start)
226 trace[traceLen++] = ((timestamp_start >> 0) & 0xff);
227 trace[traceLen++] = ((timestamp_start >> 8) & 0xff);
228 trace[traceLen++] = ((timestamp_start >> 16) & 0xff);
229 trace[traceLen++] = ((timestamp_start >> 24) & 0xff);
230
231 // duration
232 trace[traceLen++] = ((duration >> 0) & 0xff);
233 trace[traceLen++] = ((duration >> 8) & 0xff);
234
235 // data length
236 trace[traceLen++] = ((iLen >> 0) & 0xff);
237 trace[traceLen++] = ((iLen >> 8) & 0xff);
17cba269 238
6a1f2d82 239 // readerToTag flag
17cba269 240 if (!readerToTag) {
7bc95e2e 241 trace[traceLen - 1] |= 0x80;
242 }
6a1f2d82 243
244 // data bytes
7bc95e2e 245 if (btBytes != NULL && iLen != 0) {
246 memcpy(trace + traceLen, btBytes, iLen);
247 }
248 traceLen += iLen;
6a1f2d82 249
250 // parity bytes
251 if (parity != NULL && iLen != 0) {
252 memcpy(trace + traceLen, parity, num_paritybytes);
253 }
254 traceLen += num_paritybytes;
255
7bc95e2e 256 return TRUE;
15c4dc5a 257}
258
7bc95e2e 259//=============================================================================
260// ISO 14443 Type A - Miller decoder
261//=============================================================================
262// Basics:
263// This decoder is used when the PM3 acts as a tag.
264// The reader will generate "pauses" by temporarily switching of the field.
265// At the PM3 antenna we will therefore measure a modulated antenna voltage.
266// The FPGA does a comparison with a threshold and would deliver e.g.:
267// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
268// The Miller decoder needs to identify the following sequences:
269// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
270// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
271// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
272// Note 1: the bitstream may start at any time. We therefore need to sync.
273// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 274//-----------------------------------------------------------------------------
b62a5a84 275static tUart Uart;
15c4dc5a 276
d7aa3739 277// Lookup-Table to decide if 4 raw bits are a modulation.
278// We accept two or three consecutive "0" in any position with the rest "1"
279const bool Mod_Miller_LUT[] = {
280 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
281 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
282};
283#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
284#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
285
7bc95e2e 286void UartReset()
15c4dc5a 287{
7bc95e2e 288 Uart.state = STATE_UNSYNCD;
289 Uart.bitCount = 0;
290 Uart.len = 0; // number of decoded data bytes
6a1f2d82 291 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 292 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 293 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 294 Uart.twoBits = 0x0000; // buffer for 2 Bits
295 Uart.highCnt = 0;
296 Uart.startTime = 0;
297 Uart.endTime = 0;
298}
15c4dc5a 299
6a1f2d82 300void UartInit(uint8_t *data, uint8_t *parity)
301{
302 Uart.output = data;
303 Uart.parity = parity;
304 UartReset();
305}
d714d3ef 306
7bc95e2e 307// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
308static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
309{
15c4dc5a 310
7bc95e2e 311 Uart.twoBits = (Uart.twoBits << 8) | bit;
312
313 if (Uart.state == STATE_UNSYNCD) { // not yet synced
3fe4ff4f 314
7bc95e2e 315 if (Uart.highCnt < 7) { // wait for a stable unmodulated signal
316 if (Uart.twoBits == 0xffff) {
317 Uart.highCnt++;
318 } else {
319 Uart.highCnt = 0;
15c4dc5a 320 }
7bc95e2e 321 } else {
322 Uart.syncBit = 0xFFFF; // not set
323 // look for 00xx1111 (the start bit)
324 if ((Uart.twoBits & 0x6780) == 0x0780) Uart.syncBit = 7;
325 else if ((Uart.twoBits & 0x33C0) == 0x03C0) Uart.syncBit = 6;
326 else if ((Uart.twoBits & 0x19E0) == 0x01E0) Uart.syncBit = 5;
327 else if ((Uart.twoBits & 0x0CF0) == 0x00F0) Uart.syncBit = 4;
328 else if ((Uart.twoBits & 0x0678) == 0x0078) Uart.syncBit = 3;
329 else if ((Uart.twoBits & 0x033C) == 0x003C) Uart.syncBit = 2;
330 else if ((Uart.twoBits & 0x019E) == 0x001E) Uart.syncBit = 1;
331 else if ((Uart.twoBits & 0x00CF) == 0x000F) Uart.syncBit = 0;
332 if (Uart.syncBit != 0xFFFF) {
333 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
334 Uart.startTime -= Uart.syncBit;
d7aa3739 335 Uart.endTime = Uart.startTime;
7bc95e2e 336 Uart.state = STATE_START_OF_COMMUNICATION;
15c4dc5a 337 }
7bc95e2e 338 }
15c4dc5a 339
7bc95e2e 340 } else {
15c4dc5a 341
d7aa3739 342 if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
343 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
344 UartReset();
345 Uart.highCnt = 6;
346 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 347 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
348 UartReset();
349 Uart.highCnt = 6;
350 } else {
351 Uart.bitCount++;
352 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
353 Uart.state = STATE_MILLER_Z;
354 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
355 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
356 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
357 Uart.parityBits <<= 1; // make room for the parity bit
358 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
359 Uart.bitCount = 0;
360 Uart.shiftReg = 0;
6a1f2d82 361 if((Uart.len&0x0007) == 0) { // every 8 data bytes
362 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
363 Uart.parityBits = 0;
364 }
15c4dc5a 365 }
7bc95e2e 366 }
d7aa3739 367 }
368 } else {
369 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 370 Uart.bitCount++;
371 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
372 Uart.state = STATE_MILLER_X;
373 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
374 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
375 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
376 Uart.parityBits <<= 1; // make room for the new parity bit
377 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
378 Uart.bitCount = 0;
379 Uart.shiftReg = 0;
6a1f2d82 380 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
381 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
382 Uart.parityBits = 0;
383 }
7bc95e2e 384 }
d7aa3739 385 } else { // no modulation in both halves - Sequence Y
7bc95e2e 386 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 387 Uart.state = STATE_UNSYNCD;
6a1f2d82 388 Uart.bitCount--; // last "0" was part of EOC sequence
389 Uart.shiftReg <<= 1; // drop it
390 if(Uart.bitCount > 0) { // if we decoded some bits
391 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
392 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
393 Uart.parityBits <<= 1; // add a (void) parity bit
394 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
395 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
396 return TRUE;
397 } else if (Uart.len & 0x0007) { // there are some parity bits to store
398 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
399 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 400 }
401 if (Uart.len) {
6a1f2d82 402 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 403 } else {
3fe4ff4f 404 UartReset(); // Nothing receiver - start over
7bc95e2e 405 }
15c4dc5a 406 }
7bc95e2e 407 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
408 UartReset();
409 Uart.highCnt = 6;
410 } else { // a logic "0"
411 Uart.bitCount++;
412 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
413 Uart.state = STATE_MILLER_Y;
414 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
415 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
416 Uart.parityBits <<= 1; // make room for the parity bit
417 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
418 Uart.bitCount = 0;
419 Uart.shiftReg = 0;
6a1f2d82 420 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
421 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
422 Uart.parityBits = 0;
423 }
15c4dc5a 424 }
425 }
d7aa3739 426 }
15c4dc5a 427 }
7bc95e2e 428
429 }
15c4dc5a 430
7bc95e2e 431 return FALSE; // not finished yet, need more data
15c4dc5a 432}
433
7bc95e2e 434
435
15c4dc5a 436//=============================================================================
e691fc45 437// ISO 14443 Type A - Manchester decoder
15c4dc5a 438//=============================================================================
e691fc45 439// Basics:
7bc95e2e 440// This decoder is used when the PM3 acts as a reader.
e691fc45 441// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
442// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
443// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
444// The Manchester decoder needs to identify the following sequences:
445// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
446// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
447// 8 ticks unmodulated: Sequence F = end of communication
448// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 449// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 450// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 451static tDemod Demod;
15c4dc5a 452
d7aa3739 453// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 454// We accept three or four "1" in any position
7bc95e2e 455const bool Mod_Manchester_LUT[] = {
d7aa3739 456 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 457 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 458};
459
460#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
461#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 462
2f2d9fc5 463
7bc95e2e 464void DemodReset()
e691fc45 465{
7bc95e2e 466 Demod.state = DEMOD_UNSYNCD;
467 Demod.len = 0; // number of decoded data bytes
6a1f2d82 468 Demod.parityLen = 0;
7bc95e2e 469 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
470 Demod.parityBits = 0; //
471 Demod.collisionPos = 0; // Position of collision bit
472 Demod.twoBits = 0xffff; // buffer for 2 Bits
473 Demod.highCnt = 0;
474 Demod.startTime = 0;
475 Demod.endTime = 0;
e691fc45 476}
15c4dc5a 477
6a1f2d82 478void DemodInit(uint8_t *data, uint8_t *parity)
479{
480 Demod.output = data;
481 Demod.parity = parity;
482 DemodReset();
483}
484
7bc95e2e 485// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
486static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
e691fc45 487{
7bc95e2e 488
489 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 490
7bc95e2e 491 if (Demod.state == DEMOD_UNSYNCD) {
492
493 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
494 if (Demod.twoBits == 0x0000) {
495 Demod.highCnt++;
496 } else {
497 Demod.highCnt = 0;
498 }
499 } else {
500 Demod.syncBit = 0xFFFF; // not set
501 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
502 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
503 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
504 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
505 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
506 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
507 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
508 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 509 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 510 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
511 Demod.startTime -= Demod.syncBit;
512 Demod.bitCount = offset; // number of decoded data bits
e691fc45 513 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 514 }
7bc95e2e 515 }
15c4dc5a 516
7bc95e2e 517 } else {
15c4dc5a 518
7bc95e2e 519 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
520 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 521 if (!Demod.collisionPos) {
522 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
523 }
524 } // modulation in first half only - Sequence D = 1
7bc95e2e 525 Demod.bitCount++;
526 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
527 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 528 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 529 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 530 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
531 Demod.bitCount = 0;
532 Demod.shiftReg = 0;
6a1f2d82 533 if((Demod.len&0x0007) == 0) { // every 8 data bytes
534 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
535 Demod.parityBits = 0;
536 }
15c4dc5a 537 }
7bc95e2e 538 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
539 } else { // no modulation in first half
540 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 541 Demod.bitCount++;
7bc95e2e 542 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 543 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 544 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 545 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 546 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
547 Demod.bitCount = 0;
548 Demod.shiftReg = 0;
6a1f2d82 549 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
550 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
551 Demod.parityBits = 0;
552 }
15c4dc5a 553 }
7bc95e2e 554 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 555 } else { // no modulation in both halves - End of communication
6a1f2d82 556 if(Demod.bitCount > 0) { // there are some remaining data bits
557 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
558 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
559 Demod.parityBits <<= 1; // add a (void) parity bit
560 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
561 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
562 return TRUE;
563 } else if (Demod.len & 0x0007) { // there are some parity bits to store
564 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
565 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 566 }
567 if (Demod.len) {
d7aa3739 568 return TRUE; // we are finished with decoding the raw data sequence
569 } else { // nothing received. Start over
570 DemodReset();
e691fc45 571 }
15c4dc5a 572 }
7bc95e2e 573 }
e691fc45 574
575 }
15c4dc5a 576
e691fc45 577 return FALSE; // not finished yet, need more data
15c4dc5a 578}
579
580//=============================================================================
581// Finally, a `sniffer' for ISO 14443 Type A
582// Both sides of communication!
583//=============================================================================
584
585//-----------------------------------------------------------------------------
586// Record the sequence of commands sent by the reader to the tag, with
587// triggering so that we start recording at the point that the tag is moved
588// near the reader.
589//-----------------------------------------------------------------------------
5cd9ec01
M
590void RAMFUNC SnoopIso14443a(uint8_t param) {
591 // param:
592 // bit 0 - trigger from first card answer
593 // bit 1 - trigger from first reader 7-bit request
594
595 LEDsoff();
5cd9ec01
M
596
597 // We won't start recording the frames that we acquire until we trigger;
598 // a good trigger condition to get started is probably when we see a
599 // response from the tag.
600 // triggered == FALSE -- to wait first for card
7bc95e2e 601 bool triggered = !(param & 0x03);
602
f71f4deb 603 // Allocate memory from BigBuf for some buffers
604 // free all previous allocations first
605 BigBuf_free();
606
5cd9ec01 607 // The command (reader -> tag) that we're receiving.
f71f4deb 608 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
609 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 610
5cd9ec01 611 // The response (tag -> reader) that we're receiving.
f71f4deb 612 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
613 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
614
615 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 616 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
617
618 // init trace buffer
619 iso14a_clear_trace();
620 iso14a_set_tracing(TRUE);
621
7bc95e2e 622 uint8_t *data = dmaBuf;
623 uint8_t previous_data = 0;
5cd9ec01
M
624 int maxDataLen = 0;
625 int dataLen = 0;
7bc95e2e 626 bool TagIsActive = FALSE;
627 bool ReaderIsActive = FALSE;
628
629 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
15c4dc5a 630
5cd9ec01 631 // Set up the demodulator for tag -> reader responses.
6a1f2d82 632 DemodInit(receivedResponse, receivedResponsePar);
633
5cd9ec01 634 // Set up the demodulator for the reader -> tag commands
6a1f2d82 635 UartInit(receivedCmd, receivedCmdPar);
636
7bc95e2e 637 // Setup and start DMA.
5cd9ec01 638 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 639
5cd9ec01 640 // And now we loop, receiving samples.
7bc95e2e 641 for(uint32_t rsamples = 0; TRUE; ) {
642
5cd9ec01
M
643 if(BUTTON_PRESS()) {
644 DbpString("cancelled by button");
7bc95e2e 645 break;
5cd9ec01 646 }
15c4dc5a 647
5cd9ec01
M
648 LED_A_ON();
649 WDT_HIT();
15c4dc5a 650
5cd9ec01
M
651 int register readBufDataP = data - dmaBuf;
652 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
653 if (readBufDataP <= dmaBufDataP){
654 dataLen = dmaBufDataP - readBufDataP;
655 } else {
7bc95e2e 656 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
657 }
658 // test for length of buffer
659 if(dataLen > maxDataLen) {
660 maxDataLen = dataLen;
f71f4deb 661 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 662 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
663 break;
5cd9ec01
M
664 }
665 }
666 if(dataLen < 1) continue;
667
668 // primary buffer was stopped( <-- we lost data!
669 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
670 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
671 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 672 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
673 }
674 // secondary buffer sets as primary, secondary buffer was stopped
675 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
676 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
677 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
678 }
679
680 LED_A_OFF();
7bc95e2e 681
682 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 683
7bc95e2e 684 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
685 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
686 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
687 LED_C_ON();
5cd9ec01 688
7bc95e2e 689 // check - if there is a short 7bit request from reader
690 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 691
7bc95e2e 692 if(triggered) {
6a1f2d82 693 if (!LogTrace(receivedCmd,
694 Uart.len,
695 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
696 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
697 Uart.parity,
698 TRUE)) break;
7bc95e2e 699 }
700 /* And ready to receive another command. */
701 UartReset();
702 /* And also reset the demod code, which might have been */
703 /* false-triggered by the commands from the reader. */
704 DemodReset();
705 LED_B_OFF();
706 }
707 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 708 }
3be2a5ae 709
7bc95e2e 710 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
711 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
712 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
713 LED_B_ON();
5cd9ec01 714
6a1f2d82 715 if (!LogTrace(receivedResponse,
716 Demod.len,
717 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
718 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
719 Demod.parity,
720 FALSE)) break;
5cd9ec01 721
7bc95e2e 722 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 723
7bc95e2e 724 // And ready to receive another response.
725 DemodReset();
726 LED_C_OFF();
727 }
728 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
729 }
5cd9ec01
M
730 }
731
7bc95e2e 732 previous_data = *data;
733 rsamples++;
5cd9ec01 734 data++;
d714d3ef 735 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
736 data = dmaBuf;
737 }
738 } // main cycle
739
740 DbpString("COMMAND FINISHED");
15c4dc5a 741
7bc95e2e 742 FpgaDisableSscDma();
743 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
744 Dbprintf("traceLen=%d, Uart.output[0]=%08x", traceLen, (uint32_t)Uart.output[0]);
5cd9ec01 745 LEDsoff();
15c4dc5a 746}
747
15c4dc5a 748//-----------------------------------------------------------------------------
749// Prepare tag messages
750//-----------------------------------------------------------------------------
6a1f2d82 751static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
15c4dc5a 752{
8f51ddb0 753 ToSendReset();
15c4dc5a 754
755 // Correction bit, might be removed when not needed
756 ToSendStuffBit(0);
757 ToSendStuffBit(0);
758 ToSendStuffBit(0);
759 ToSendStuffBit(0);
760 ToSendStuffBit(1); // 1
761 ToSendStuffBit(0);
762 ToSendStuffBit(0);
763 ToSendStuffBit(0);
8f51ddb0 764
15c4dc5a 765 // Send startbit
72934aa3 766 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 767 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 768
6a1f2d82 769 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 770 uint8_t b = cmd[i];
15c4dc5a 771
772 // Data bits
6a1f2d82 773 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 774 if(b & 1) {
72934aa3 775 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 776 } else {
72934aa3 777 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
778 }
779 b >>= 1;
780 }
15c4dc5a 781
0014cb46 782 // Get the parity bit
6a1f2d82 783 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 784 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 785 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 786 } else {
72934aa3 787 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 788 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 789 }
8f51ddb0 790 }
15c4dc5a 791
8f51ddb0
M
792 // Send stopbit
793 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 794
8f51ddb0
M
795 // Convert from last byte pos to length
796 ToSendMax++;
8f51ddb0
M
797}
798
6a1f2d82 799static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
800{
801 uint8_t par[MAX_PARITY_SIZE];
802
803 GetParity(cmd, len, par);
804 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 805}
806
15c4dc5a 807
8f51ddb0
M
808static void Code4bitAnswerAsTag(uint8_t cmd)
809{
810 int i;
811
5f6d6c90 812 ToSendReset();
8f51ddb0
M
813
814 // Correction bit, might be removed when not needed
815 ToSendStuffBit(0);
816 ToSendStuffBit(0);
817 ToSendStuffBit(0);
818 ToSendStuffBit(0);
819 ToSendStuffBit(1); // 1
820 ToSendStuffBit(0);
821 ToSendStuffBit(0);
822 ToSendStuffBit(0);
823
824 // Send startbit
825 ToSend[++ToSendMax] = SEC_D;
826
827 uint8_t b = cmd;
828 for(i = 0; i < 4; i++) {
829 if(b & 1) {
830 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 831 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
832 } else {
833 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 834 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
835 }
836 b >>= 1;
837 }
838
839 // Send stopbit
840 ToSend[++ToSendMax] = SEC_F;
841
5f6d6c90 842 // Convert from last byte pos to length
843 ToSendMax++;
15c4dc5a 844}
845
846//-----------------------------------------------------------------------------
847// Wait for commands from reader
848// Stop when button is pressed
849// Or return TRUE when command is captured
850//-----------------------------------------------------------------------------
6a1f2d82 851static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
15c4dc5a 852{
853 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
854 // only, since we are receiving, not transmitting).
855 // Signal field is off with the appropriate LED
856 LED_D_OFF();
857 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
858
859 // Now run a `software UART' on the stream of incoming samples.
6a1f2d82 860 UartInit(received, parity);
7bc95e2e 861
862 // clear RXRDY:
863 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 864
865 for(;;) {
866 WDT_HIT();
867
868 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 869
15c4dc5a 870 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 871 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
872 if(MillerDecoding(b, 0)) {
873 *len = Uart.len;
15c4dc5a 874 return TRUE;
875 }
7bc95e2e 876 }
15c4dc5a 877 }
878}
28afbd2b 879
6a1f2d82 880static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
7bc95e2e 881int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
28afbd2b 882int EmSend4bit(uint8_t resp);
6a1f2d82 883int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
884int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
885int EmSendCmd(uint8_t *resp, uint16_t respLen);
886int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
887bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
888 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
15c4dc5a 889
117d9ec2 890static uint8_t* free_buffer_pointer;
ce02f6f9 891
892typedef struct {
893 uint8_t* response;
894 size_t response_n;
895 uint8_t* modulation;
896 size_t modulation_n;
7bc95e2e 897 uint32_t ProxToAirDuration;
ce02f6f9 898} tag_response_info_t;
899
ce02f6f9 900bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 901 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 902 // This will need the following byte array for a modulation sequence
903 // 144 data bits (18 * 8)
904 // 18 parity bits
905 // 2 Start and stop
906 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
907 // 1 just for the case
908 // ----------- +
909 // 166 bytes, since every bit that needs to be send costs us a byte
910 //
f71f4deb 911
912
ce02f6f9 913 // Prepare the tag modulation bits from the message
914 CodeIso14443aAsTag(response_info->response,response_info->response_n);
915
916 // Make sure we do not exceed the free buffer space
917 if (ToSendMax > max_buffer_size) {
918 Dbprintf("Out of memory, when modulating bits for tag answer:");
919 Dbhexdump(response_info->response_n,response_info->response,false);
920 return false;
921 }
922
923 // Copy the byte array, used for this modulation to the buffer position
924 memcpy(response_info->modulation,ToSend,ToSendMax);
925
7bc95e2e 926 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
ce02f6f9 927 response_info->modulation_n = ToSendMax;
7bc95e2e 928 response_info->ProxToAirDuration = LastProxToAirDuration;
ce02f6f9 929
930 return true;
931}
932
f71f4deb 933
934// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
935// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
936// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
937// -> need 273 bytes buffer
938#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
939
ce02f6f9 940bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
941 // Retrieve and store the current buffer index
942 response_info->modulation = free_buffer_pointer;
943
944 // Determine the maximum size we can use from our buffer
f71f4deb 945 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
ce02f6f9 946
947 // Forward the prepare tag modulation function to the inner function
f71f4deb 948 if (prepare_tag_modulation(response_info, max_buffer_size)) {
ce02f6f9 949 // Update the free buffer offset
950 free_buffer_pointer += ToSendMax;
951 return true;
952 } else {
953 return false;
954 }
955}
956
15c4dc5a 957//-----------------------------------------------------------------------------
958// Main loop of simulated tag: receive commands from reader, decide what
959// response to send, and send it.
960//-----------------------------------------------------------------------------
28afbd2b 961void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
15c4dc5a 962{
81cd0474 963 uint8_t sak;
964
965 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
966 uint8_t response1[2];
967
968 switch (tagType) {
969 case 1: { // MIFARE Classic
970 // Says: I am Mifare 1k - original line
971 response1[0] = 0x04;
972 response1[1] = 0x00;
973 sak = 0x08;
974 } break;
975 case 2: { // MIFARE Ultralight
976 // Says: I am a stupid memory tag, no crypto
977 response1[0] = 0x04;
978 response1[1] = 0x00;
979 sak = 0x00;
980 } break;
981 case 3: { // MIFARE DESFire
982 // Says: I am a DESFire tag, ph33r me
983 response1[0] = 0x04;
984 response1[1] = 0x03;
985 sak = 0x20;
986 } break;
987 case 4: { // ISO/IEC 14443-4
988 // Says: I am a javacard (JCOP)
989 response1[0] = 0x04;
990 response1[1] = 0x00;
991 sak = 0x28;
992 } break;
3fe4ff4f 993 case 5: { // MIFARE TNP3XXX
994 // Says: I am a toy
995 response1[0] = 0x01;
996 response1[1] = 0x0f;
997 sak = 0x01;
998 } break;
81cd0474 999 default: {
1000 Dbprintf("Error: unkown tagtype (%d)",tagType);
1001 return;
1002 } break;
1003 }
1004
1005 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 1006 uint8_t response2[5] = {0x00};
81cd0474 1007
1008 // Check if the uid uses the (optional) part
c8b6da22 1009 uint8_t response2a[5] = {0x00};
1010
81cd0474 1011 if (uid_2nd) {
1012 response2[0] = 0x88;
1013 num_to_bytes(uid_1st,3,response2+1);
1014 num_to_bytes(uid_2nd,4,response2a);
1015 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1016
1017 // Configure the ATQA and SAK accordingly
1018 response1[0] |= 0x40;
1019 sak |= 0x04;
1020 } else {
1021 num_to_bytes(uid_1st,4,response2);
1022 // Configure the ATQA and SAK accordingly
1023 response1[0] &= 0xBF;
1024 sak &= 0xFB;
1025 }
1026
1027 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1028 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1029
1030 // Prepare the mandatory SAK (for 4 and 7 byte UID)
c8b6da22 1031 uint8_t response3[3] = {0x00};
81cd0474 1032 response3[0] = sak;
1033 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1034
1035 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 1036 uint8_t response3a[3] = {0x00};
81cd0474 1037 response3a[0] = sak & 0xFB;
1038 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1039
254b70a4 1040 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
6a1f2d82 1041 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1042 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1043 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1044 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1045 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 1046 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1047
7bc95e2e 1048 #define TAG_RESPONSE_COUNT 7
1049 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1050 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1051 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1052 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1053 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1054 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1055 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1056 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1057 };
1058
1059 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1060 // Such a response is less time critical, so we can prepare them on the fly
1061 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1062 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1063 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1064 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1065 tag_response_info_t dynamic_response_info = {
1066 .response = dynamic_response_buffer,
1067 .response_n = 0,
1068 .modulation = dynamic_modulation_buffer,
1069 .modulation_n = 0
1070 };
ce02f6f9 1071
f71f4deb 1072 BigBuf_free_keep_EM();
1073
1074 // allocate buffers:
1075 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1076 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1077 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1078
1079 // clear trace
1080 iso14a_clear_trace();
1081 iso14a_set_tracing(TRUE);
1082
7bc95e2e 1083 // Prepare the responses of the anticollision phase
ce02f6f9 1084 // there will be not enough time to do this at the moment the reader sends it REQA
7bc95e2e 1085 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1086 prepare_allocated_tag_modulation(&responses[i]);
1087 }
15c4dc5a 1088
7bc95e2e 1089 int len = 0;
15c4dc5a 1090
1091 // To control where we are in the protocol
1092 int order = 0;
1093 int lastorder;
1094
1095 // Just to allow some checks
1096 int happened = 0;
1097 int happened2 = 0;
81cd0474 1098 int cmdsRecvd = 0;
15c4dc5a 1099
254b70a4 1100 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 1101 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
15c4dc5a 1102
254b70a4 1103 cmdsRecvd = 0;
7bc95e2e 1104 tag_response_info_t* p_response;
15c4dc5a 1105
254b70a4 1106 LED_A_ON();
1107 for(;;) {
7bc95e2e 1108 // Clean receive command buffer
1109
6a1f2d82 1110 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1111 DbpString("Button press");
254b70a4 1112 break;
1113 }
7bc95e2e 1114
1115 p_response = NULL;
1116
254b70a4 1117 // Okay, look at the command now.
1118 lastorder = order;
1119 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1120 p_response = &responses[0]; order = 1;
254b70a4 1121 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1122 p_response = &responses[0]; order = 6;
254b70a4 1123 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1124 p_response = &responses[1]; order = 2;
6a1f2d82 1125 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1126 p_response = &responses[2]; order = 20;
254b70a4 1127 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1128 p_response = &responses[3]; order = 3;
254b70a4 1129 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1130 p_response = &responses[4]; order = 30;
254b70a4 1131 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
6a1f2d82 1132 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
7bc95e2e 1133 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
5f6d6c90 1134 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
7bc95e2e 1135 p_response = NULL;
254b70a4 1136 } else if(receivedCmd[0] == 0x50) { // Received a HALT
3fe4ff4f 1137
7bc95e2e 1138 if (tracing) {
6a1f2d82 1139 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1140 }
1141 p_response = NULL;
254b70a4 1142 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
ce02f6f9 1143 p_response = &responses[5]; order = 7;
254b70a4 1144 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
7bc95e2e 1145 if (tagType == 1 || tagType == 2) { // RATS not supported
1146 EmSend4bit(CARD_NACK_NA);
1147 p_response = NULL;
1148 } else {
1149 p_response = &responses[6]; order = 70;
1150 }
6a1f2d82 1151 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
7bc95e2e 1152 if (tracing) {
6a1f2d82 1153 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1154 }
1155 uint32_t nr = bytes_to_num(receivedCmd,4);
1156 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1157 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1158 } else {
1159 // Check for ISO 14443A-4 compliant commands, look at left nibble
1160 switch (receivedCmd[0]) {
1161
1162 case 0x0B:
1163 case 0x0A: { // IBlock (command)
1164 dynamic_response_info.response[0] = receivedCmd[0];
1165 dynamic_response_info.response[1] = 0x00;
1166 dynamic_response_info.response[2] = 0x90;
1167 dynamic_response_info.response[3] = 0x00;
1168 dynamic_response_info.response_n = 4;
1169 } break;
1170
1171 case 0x1A:
1172 case 0x1B: { // Chaining command
1173 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1174 dynamic_response_info.response_n = 2;
1175 } break;
1176
1177 case 0xaa:
1178 case 0xbb: {
1179 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1180 dynamic_response_info.response_n = 2;
1181 } break;
1182
1183 case 0xBA: { //
1184 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1185 dynamic_response_info.response_n = 2;
1186 } break;
1187
1188 case 0xCA:
1189 case 0xC2: { // Readers sends deselect command
1190 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1191 dynamic_response_info.response_n = 2;
1192 } break;
1193
1194 default: {
1195 // Never seen this command before
1196 if (tracing) {
6a1f2d82 1197 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1198 }
1199 Dbprintf("Received unknown command (len=%d):",len);
1200 Dbhexdump(len,receivedCmd,false);
1201 // Do not respond
1202 dynamic_response_info.response_n = 0;
1203 } break;
1204 }
ce02f6f9 1205
7bc95e2e 1206 if (dynamic_response_info.response_n > 0) {
1207 // Copy the CID from the reader query
1208 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1209
7bc95e2e 1210 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1211 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1212 dynamic_response_info.response_n += 2;
ce02f6f9 1213
7bc95e2e 1214 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1215 Dbprintf("Error preparing tag response");
1216 if (tracing) {
6a1f2d82 1217 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1218 }
1219 break;
1220 }
1221 p_response = &dynamic_response_info;
1222 }
81cd0474 1223 }
15c4dc5a 1224
1225 // Count number of wakeups received after a halt
1226 if(order == 6 && lastorder == 5) { happened++; }
1227
1228 // Count number of other messages after a halt
1229 if(order != 6 && lastorder == 5) { happened2++; }
1230
15c4dc5a 1231 if(cmdsRecvd > 999) {
1232 DbpString("1000 commands later...");
254b70a4 1233 break;
15c4dc5a 1234 }
ce02f6f9 1235 cmdsRecvd++;
1236
1237 if (p_response != NULL) {
7bc95e2e 1238 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1239 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1240 uint8_t par[MAX_PARITY_SIZE];
1241 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1242
7bc95e2e 1243 EmLogTrace(Uart.output,
1244 Uart.len,
1245 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1246 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1247 Uart.parity,
7bc95e2e 1248 p_response->response,
1249 p_response->response_n,
1250 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1251 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1252 par);
7bc95e2e 1253 }
1254
1255 if (!tracing) {
1256 Dbprintf("Trace Full. Simulation stopped.");
1257 break;
1258 }
1259 }
15c4dc5a 1260
1261 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1262 LED_A_OFF();
f71f4deb 1263 BigBuf_free_keep_EM();
15c4dc5a 1264}
1265
9492e0b0 1266
1267// prepare a delayed transfer. This simply shifts ToSend[] by a number
1268// of bits specified in the delay parameter.
1269void PrepareDelayedTransfer(uint16_t delay)
1270{
1271 uint8_t bitmask = 0;
1272 uint8_t bits_to_shift = 0;
1273 uint8_t bits_shifted = 0;
1274
1275 delay &= 0x07;
1276 if (delay) {
1277 for (uint16_t i = 0; i < delay; i++) {
1278 bitmask |= (0x01 << i);
1279 }
7bc95e2e 1280 ToSend[ToSendMax++] = 0x00;
9492e0b0 1281 for (uint16_t i = 0; i < ToSendMax; i++) {
1282 bits_to_shift = ToSend[i] & bitmask;
1283 ToSend[i] = ToSend[i] >> delay;
1284 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1285 bits_shifted = bits_to_shift;
1286 }
1287 }
1288}
1289
7bc95e2e 1290
1291//-------------------------------------------------------------------------------------
15c4dc5a 1292// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1293// Parameter timing:
7bc95e2e 1294// if NULL: transfer at next possible time, taking into account
1295// request guard time and frame delay time
1296// if == 0: transfer immediately and return time of transfer
9492e0b0 1297// if != 0: delay transfer until time specified
7bc95e2e 1298//-------------------------------------------------------------------------------------
6a1f2d82 1299static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1300{
7bc95e2e 1301
9492e0b0 1302 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1303
7bc95e2e 1304 uint32_t ThisTransferTime = 0;
e30c654b 1305
9492e0b0 1306 if (timing) {
1307 if(*timing == 0) { // Measure time
7bc95e2e 1308 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
9492e0b0 1309 } else {
1310 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1311 }
7bc95e2e 1312 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1313 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1314 LastTimeProxToAirStart = *timing;
1315 } else {
1316 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1317 while(GetCountSspClk() < ThisTransferTime);
1318 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1319 }
1320
7bc95e2e 1321 // clear TXRDY
1322 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1323
7bc95e2e 1324 uint16_t c = 0;
9492e0b0 1325 for(;;) {
1326 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1327 AT91C_BASE_SSC->SSC_THR = cmd[c];
1328 c++;
1329 if(c >= len) {
1330 break;
1331 }
1332 }
1333 }
7bc95e2e 1334
1335 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1336}
1337
7bc95e2e 1338
15c4dc5a 1339//-----------------------------------------------------------------------------
195af472 1340// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1341//-----------------------------------------------------------------------------
6a1f2d82 1342void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1343{
7bc95e2e 1344 int i, j;
1345 int last;
1346 uint8_t b;
e30c654b 1347
7bc95e2e 1348 ToSendReset();
e30c654b 1349
7bc95e2e 1350 // Start of Communication (Seq. Z)
1351 ToSend[++ToSendMax] = SEC_Z;
1352 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1353 last = 0;
1354
1355 size_t bytecount = nbytes(bits);
1356 // Generate send structure for the data bits
1357 for (i = 0; i < bytecount; i++) {
1358 // Get the current byte to send
1359 b = cmd[i];
1360 size_t bitsleft = MIN((bits-(i*8)),8);
1361
1362 for (j = 0; j < bitsleft; j++) {
1363 if (b & 1) {
1364 // Sequence X
1365 ToSend[++ToSendMax] = SEC_X;
1366 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1367 last = 1;
1368 } else {
1369 if (last == 0) {
1370 // Sequence Z
1371 ToSend[++ToSendMax] = SEC_Z;
1372 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1373 } else {
1374 // Sequence Y
1375 ToSend[++ToSendMax] = SEC_Y;
1376 last = 0;
1377 }
1378 }
1379 b >>= 1;
1380 }
1381
6a1f2d82 1382 // Only transmit parity bit if we transmitted a complete byte
7bc95e2e 1383 if (j == 8) {
1384 // Get the parity bit
6a1f2d82 1385 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1386 // Sequence X
1387 ToSend[++ToSendMax] = SEC_X;
1388 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1389 last = 1;
1390 } else {
1391 if (last == 0) {
1392 // Sequence Z
1393 ToSend[++ToSendMax] = SEC_Z;
1394 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1395 } else {
1396 // Sequence Y
1397 ToSend[++ToSendMax] = SEC_Y;
1398 last = 0;
1399 }
1400 }
1401 }
1402 }
e30c654b 1403
7bc95e2e 1404 // End of Communication: Logic 0 followed by Sequence Y
1405 if (last == 0) {
1406 // Sequence Z
1407 ToSend[++ToSendMax] = SEC_Z;
1408 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1409 } else {
1410 // Sequence Y
1411 ToSend[++ToSendMax] = SEC_Y;
1412 last = 0;
1413 }
1414 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1415
7bc95e2e 1416 // Convert to length of command:
1417 ToSendMax++;
15c4dc5a 1418}
1419
195af472 1420//-----------------------------------------------------------------------------
1421// Prepare reader command to send to FPGA
1422//-----------------------------------------------------------------------------
6a1f2d82 1423void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
195af472 1424{
6a1f2d82 1425 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1426}
1427
9ca155ba
M
1428//-----------------------------------------------------------------------------
1429// Wait for commands from reader
1430// Stop when button is pressed (return 1) or field was gone (return 2)
1431// Or return 0 when command is captured
1432//-----------------------------------------------------------------------------
6a1f2d82 1433static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
9ca155ba
M
1434{
1435 *len = 0;
1436
1437 uint32_t timer = 0, vtime = 0;
1438 int analogCnt = 0;
1439 int analogAVG = 0;
1440
1441 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1442 // only, since we are receiving, not transmitting).
1443 // Signal field is off with the appropriate LED
1444 LED_D_OFF();
1445 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1446
1447 // Set ADC to read field strength
1448 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1449 AT91C_BASE_ADC->ADC_MR =
1450 ADC_MODE_PRESCALE(32) |
1451 ADC_MODE_STARTUP_TIME(16) |
1452 ADC_MODE_SAMPLE_HOLD_TIME(8);
1453 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1454 // start ADC
1455 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1456
1457 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1458 UartInit(received, parity);
7bc95e2e 1459
1460 // Clear RXRDY:
1461 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba
M
1462
1463 for(;;) {
1464 WDT_HIT();
1465
1466 if (BUTTON_PRESS()) return 1;
1467
1468 // test if the field exists
1469 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1470 analogCnt++;
1471 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1472 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1473 if (analogCnt >= 32) {
1474 if ((33000 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1475 vtime = GetTickCount();
1476 if (!timer) timer = vtime;
1477 // 50ms no field --> card to idle state
1478 if (vtime - timer > 50) return 2;
1479 } else
1480 if (timer) timer = 0;
1481 analogCnt = 0;
1482 analogAVG = 0;
1483 }
1484 }
7bc95e2e 1485
9ca155ba 1486 // receive and test the miller decoding
7bc95e2e 1487 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1488 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1489 if(MillerDecoding(b, 0)) {
1490 *len = Uart.len;
9ca155ba
M
1491 return 0;
1492 }
7bc95e2e 1493 }
1494
9ca155ba
M
1495 }
1496}
1497
9ca155ba 1498
6a1f2d82 1499static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
7bc95e2e 1500{
1501 uint8_t b;
1502 uint16_t i = 0;
1503 uint32_t ThisTransferTime;
1504
9ca155ba
M
1505 // Modulate Manchester
1506 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1507
1508 // include correction bit if necessary
1509 if (Uart.parityBits & 0x01) {
1510 correctionNeeded = TRUE;
1511 }
1512 if(correctionNeeded) {
9ca155ba
M
1513 // 1236, so correction bit needed
1514 i = 0;
7bc95e2e 1515 } else {
1516 i = 1;
9ca155ba 1517 }
7bc95e2e 1518
d714d3ef 1519 // clear receiving shift register and holding register
7bc95e2e 1520 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1521 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1522 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1523 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1524
7bc95e2e 1525 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1526 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1527 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1528 if (AT91C_BASE_SSC->SSC_RHR) break;
1529 }
1530
1531 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1532
1533 // Clear TXRDY:
1534 AT91C_BASE_SSC->SSC_THR = SEC_F;
1535
9ca155ba 1536 // send cycle
7bc95e2e 1537 for(; i <= respLen; ) {
9ca155ba 1538 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1539 AT91C_BASE_SSC->SSC_THR = resp[i++];
1540 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1541 }
7bc95e2e 1542
9ca155ba
M
1543 if(BUTTON_PRESS()) {
1544 break;
1545 }
1546 }
1547
7bc95e2e 1548 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1549 for (i = 0; i < 2 ; ) {
1550 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1551 AT91C_BASE_SSC->SSC_THR = SEC_F;
1552 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1553 i++;
1554 }
1555 }
1556
1557 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1558
9ca155ba
M
1559 return 0;
1560}
1561
7bc95e2e 1562int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1563 Code4bitAnswerAsTag(resp);
0a39986e 1564 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1565 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1566 uint8_t par[1];
1567 GetParity(&resp, 1, par);
7bc95e2e 1568 EmLogTrace(Uart.output,
1569 Uart.len,
1570 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1571 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1572 Uart.parity,
7bc95e2e 1573 &resp,
1574 1,
1575 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1576 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1577 par);
0a39986e 1578 return res;
9ca155ba
M
1579}
1580
8f51ddb0 1581int EmSend4bit(uint8_t resp){
7bc95e2e 1582 return EmSend4bitEx(resp, false);
8f51ddb0
M
1583}
1584
6a1f2d82 1585int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1586 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1587 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1588 // do the tracing for the previous reader request and this tag answer:
1589 EmLogTrace(Uart.output,
1590 Uart.len,
1591 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1592 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1593 Uart.parity,
7bc95e2e 1594 resp,
1595 respLen,
1596 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1597 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1598 par);
8f51ddb0
M
1599 return res;
1600}
1601
6a1f2d82 1602int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1603 uint8_t par[MAX_PARITY_SIZE];
1604 GetParity(resp, respLen, par);
1605 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
8f51ddb0
M
1606}
1607
6a1f2d82 1608int EmSendCmd(uint8_t *resp, uint16_t respLen){
1609 uint8_t par[MAX_PARITY_SIZE];
1610 GetParity(resp, respLen, par);
1611 return EmSendCmdExPar(resp, respLen, false, par);
8f51ddb0
M
1612}
1613
6a1f2d82 1614int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1615 return EmSendCmdExPar(resp, respLen, false, par);
1616}
1617
6a1f2d82 1618bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1619 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1620{
1621 if (tracing) {
1622 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1623 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1624 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1625 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1626 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1627 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1628 reader_EndTime = tag_StartTime - exact_fdt;
1629 reader_StartTime = reader_EndTime - reader_modlen;
6a1f2d82 1630 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
7bc95e2e 1631 return FALSE;
6a1f2d82 1632 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
7bc95e2e 1633 } else {
1634 return TRUE;
1635 }
9ca155ba
M
1636}
1637
15c4dc5a 1638//-----------------------------------------------------------------------------
1639// Wait a certain time for tag response
1640// If a response is captured return TRUE
e691fc45 1641// If it takes too long return FALSE
15c4dc5a 1642//-----------------------------------------------------------------------------
6a1f2d82 1643static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1644{
52bfb955 1645 uint32_t c;
e691fc45 1646
15c4dc5a 1647 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1648 // only, since we are receiving, not transmitting).
1649 // Signal field is on with the appropriate LED
1650 LED_D_ON();
1651 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1652
534983d7 1653 // Now get the answer from the card
6a1f2d82 1654 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1655
7bc95e2e 1656 // clear RXRDY:
1657 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1658
15c4dc5a 1659 c = 0;
1660 for(;;) {
534983d7 1661 WDT_HIT();
15c4dc5a 1662
534983d7 1663 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1664 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1665 if(ManchesterDecoding(b, offset, 0)) {
1666 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1667 return TRUE;
6a1f2d82 1668 } else if (c++ > iso14a_timeout) {
7bc95e2e 1669 return FALSE;
15c4dc5a 1670 }
534983d7 1671 }
1672 }
15c4dc5a 1673}
1674
6a1f2d82 1675void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1676{
6a1f2d82 1677 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1678
7bc95e2e 1679 // Send command to tag
1680 TransmitFor14443a(ToSend, ToSendMax, timing);
1681 if(trigger)
1682 LED_A_ON();
dfc3c505 1683
7bc95e2e 1684 // Log reader command in trace buffer
1685 if (tracing) {
6a1f2d82 1686 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
7bc95e2e 1687 }
15c4dc5a 1688}
1689
6a1f2d82 1690void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1691{
6a1f2d82 1692 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1693}
15c4dc5a 1694
6a1f2d82 1695void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1696{
1697 // Generate parity and redirect
6a1f2d82 1698 uint8_t par[MAX_PARITY_SIZE];
1699 GetParity(frame, len/8, par);
1700 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1701}
1702
6a1f2d82 1703void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1704{
1705 // Generate parity and redirect
6a1f2d82 1706 uint8_t par[MAX_PARITY_SIZE];
1707 GetParity(frame, len, par);
1708 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1709}
1710
6a1f2d82 1711int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1712{
6a1f2d82 1713 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
7bc95e2e 1714 if (tracing) {
6a1f2d82 1715 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1716 }
e691fc45 1717 return Demod.len;
1718}
1719
6a1f2d82 1720int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
15c4dc5a 1721{
6a1f2d82 1722 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
7bc95e2e 1723 if (tracing) {
6a1f2d82 1724 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1725 }
e691fc45 1726 return Demod.len;
f89c7050
M
1727}
1728
e691fc45 1729/* performs iso14443a anticollision procedure
534983d7 1730 * fills the uid pointer unless NULL
1731 * fills resp_data unless NULL */
6a1f2d82 1732int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1733 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1734 uint8_t sel_all[] = { 0x93,0x20 };
1735 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1736 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
f71f4deb 1737 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1738 uint8_t resp_par[MAX_PARITY_SIZE];
6a1f2d82 1739 byte_t uid_resp[4];
1740 size_t uid_resp_len;
1741
1742 uint8_t sak = 0x04; // cascade uid
1743 int cascade_level = 0;
1744 int len;
1745
1746 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
9492e0b0 1747 ReaderTransmitBitsPar(wupa,7,0, NULL);
7bc95e2e 1748
6a1f2d82 1749 // Receive the ATQA
1750 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1751
1752 if(p_hi14a_card) {
1753 memcpy(p_hi14a_card->atqa, resp, 2);
1754 p_hi14a_card->uidlen = 0;
1755 memset(p_hi14a_card->uid,0,10);
1756 }
5f6d6c90 1757
6a1f2d82 1758 // clear uid
1759 if (uid_ptr) {
1760 memset(uid_ptr,0,10);
1761 }
79a73ab2 1762
6a1f2d82 1763 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1764 // which case we need to make a cascade 2 request and select - this is a long UID
1765 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1766 for(; sak & 0x04; cascade_level++) {
1767 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1768 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1769
1770 // SELECT_ALL
1771 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1772 if (!ReaderReceive(resp, resp_par)) return 0;
1773
1774 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1775 memset(uid_resp, 0, 4);
1776 uint16_t uid_resp_bits = 0;
1777 uint16_t collision_answer_offset = 0;
1778 // anti-collision-loop:
1779 while (Demod.collisionPos) {
1780 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1781 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1782 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
758f1fd1 1783 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1784 }
1785 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1786 uid_resp_bits++;
1787 // construct anticollosion command:
1788 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1789 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1790 sel_uid[2+i] = uid_resp[i];
1791 }
1792 collision_answer_offset = uid_resp_bits%8;
1793 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1794 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
e691fc45 1795 }
6a1f2d82 1796 // finally, add the last bits and BCC of the UID
1797 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1798 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1799 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
e691fc45 1800 }
e691fc45 1801
6a1f2d82 1802 } else { // no collision, use the response to SELECT_ALL as current uid
1803 memcpy(uid_resp, resp, 4);
1804 }
1805 uid_resp_len = 4;
5f6d6c90 1806
6a1f2d82 1807 // calculate crypto UID. Always use last 4 Bytes.
1808 if(cuid_ptr) {
1809 *cuid_ptr = bytes_to_num(uid_resp, 4);
1810 }
e30c654b 1811
6a1f2d82 1812 // Construct SELECT UID command
1813 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1814 memcpy(sel_uid+2, uid_resp, 4); // the UID
1815 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1816 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1817 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1818
1819 // Receive the SAK
1820 if (!ReaderReceive(resp, resp_par)) return 0;
1821 sak = resp[0];
1822
52ab55ab 1823 // Test if more parts of the uid are coming
6a1f2d82 1824 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1825 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1826 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1827 uid_resp[0] = uid_resp[1];
1828 uid_resp[1] = uid_resp[2];
1829 uid_resp[2] = uid_resp[3];
1830
1831 uid_resp_len = 3;
1832 }
5f6d6c90 1833
6a1f2d82 1834 if(uid_ptr) {
1835 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1836 }
5f6d6c90 1837
6a1f2d82 1838 if(p_hi14a_card) {
1839 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1840 p_hi14a_card->uidlen += uid_resp_len;
1841 }
1842 }
79a73ab2 1843
6a1f2d82 1844 if(p_hi14a_card) {
1845 p_hi14a_card->sak = sak;
1846 p_hi14a_card->ats_len = 0;
1847 }
534983d7 1848
3fe4ff4f 1849 // non iso14443a compliant tag
1850 if( (sak & 0x20) == 0) return 2;
534983d7 1851
6a1f2d82 1852 // Request for answer to select
1853 AppendCrc14443a(rats, 2);
1854 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1855
6a1f2d82 1856 if (!(len = ReaderReceive(resp, resp_par))) return 0;
5191b3d1 1857
3fe4ff4f 1858
6a1f2d82 1859 if(p_hi14a_card) {
1860 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1861 p_hi14a_card->ats_len = len;
1862 }
5f6d6c90 1863
6a1f2d82 1864 // reset the PCB block number
1865 iso14_pcb_blocknum = 0;
6a1f2d82 1866 return 1;
7e758047 1867}
15c4dc5a 1868
7bc95e2e 1869void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1870 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1871 // Set up the synchronous serial port
1872 FpgaSetupSsc();
7bc95e2e 1873 // connect Demodulated Signal to ADC:
7e758047 1874 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
e30c654b 1875
7e758047 1876 // Signal field is on with the appropriate LED
7bc95e2e 1877 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1878 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1879 LED_D_ON();
1880 } else {
1881 LED_D_OFF();
1882 }
1883 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
534983d7 1884
7bc95e2e 1885 // Start the timer
1886 StartCountSspClk();
1887
1888 DemodReset();
1889 UartReset();
1890 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1891 iso14a_set_timeout(1050); // 10ms default
7e758047 1892}
15c4dc5a 1893
6a1f2d82 1894int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1895 uint8_t parity[MAX_PARITY_SIZE];
534983d7 1896 uint8_t real_cmd[cmd_len+4];
1897 real_cmd[0] = 0x0a; //I-Block
b0127e65 1898 // put block number into the PCB
1899 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 1900 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1901 memcpy(real_cmd+2, cmd, cmd_len);
1902 AppendCrc14443a(real_cmd,cmd_len+2);
1903
9492e0b0 1904 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 1905 size_t len = ReaderReceive(data, parity);
1906 uint8_t *data_bytes = (uint8_t *) data;
b0127e65 1907 if (!len)
1908 return 0; //DATA LINK ERROR
1909 // if we received an I- or R(ACK)-Block with a block number equal to the
1910 // current block number, toggle the current block number
1911 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1912 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1913 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1914 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1915 {
1916 iso14_pcb_blocknum ^= 1;
1917 }
1918
534983d7 1919 return len;
1920}
1921
7e758047 1922//-----------------------------------------------------------------------------
1923// Read an ISO 14443a tag. Send out commands and store answers.
1924//
1925//-----------------------------------------------------------------------------
7bc95e2e 1926void ReaderIso14443a(UsbCommand *c)
7e758047 1927{
534983d7 1928 iso14a_command_t param = c->arg[0];
7bc95e2e 1929 uint8_t *cmd = c->d.asBytes;
534983d7 1930 size_t len = c->arg[1];
5f6d6c90 1931 size_t lenbits = c->arg[2];
9492e0b0 1932 uint32_t arg0 = 0;
1933 byte_t buf[USB_CMD_DATA_SIZE];
6a1f2d82 1934 uint8_t par[MAX_PARITY_SIZE];
902cb3c0 1935
5f6d6c90 1936 if(param & ISO14A_CONNECT) {
1937 iso14a_clear_trace();
1938 }
e691fc45 1939
7bc95e2e 1940 iso14a_set_tracing(TRUE);
e30c654b 1941
79a73ab2 1942 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1943 iso14a_set_trigger(TRUE);
9492e0b0 1944 }
15c4dc5a 1945
534983d7 1946 if(param & ISO14A_CONNECT) {
7bc95e2e 1947 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 1948 if(!(param & ISO14A_NO_SELECT)) {
1949 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1950 arg0 = iso14443a_select_card(NULL,card,NULL);
1951 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1952 }
534983d7 1953 }
e30c654b 1954
534983d7 1955 if(param & ISO14A_SET_TIMEOUT) {
3fe4ff4f 1956 iso14a_set_timeout(c->arg[2]);
534983d7 1957 }
e30c654b 1958
534983d7 1959 if(param & ISO14A_APDU) {
902cb3c0 1960 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 1961 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1962 }
e30c654b 1963
534983d7 1964 if(param & ISO14A_RAW) {
1965 if(param & ISO14A_APPEND_CRC) {
1966 AppendCrc14443a(cmd,len);
1967 len += 2;
c7324bef 1968 if (lenbits) lenbits += 16;
15c4dc5a 1969 }
5f6d6c90 1970 if(lenbits>0) {
6a1f2d82 1971 GetParity(cmd, lenbits/8, par);
1972 ReaderTransmitBitsPar(cmd, lenbits, par, NULL);
5f6d6c90 1973 } else {
1974 ReaderTransmit(cmd,len, NULL);
1975 }
6a1f2d82 1976 arg0 = ReaderReceive(buf, par);
9492e0b0 1977 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1978 }
15c4dc5a 1979
79a73ab2 1980 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1981 iso14a_set_trigger(FALSE);
9492e0b0 1982 }
15c4dc5a 1983
79a73ab2 1984 if(param & ISO14A_NO_DISCONNECT) {
534983d7 1985 return;
9492e0b0 1986 }
15c4dc5a 1987
15c4dc5a 1988 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1989 LEDsoff();
15c4dc5a 1990}
b0127e65 1991
1c611bbd 1992
1c611bbd 1993// Determine the distance between two nonces.
1994// Assume that the difference is small, but we don't know which is first.
1995// Therefore try in alternating directions.
1996int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1997
1998 uint16_t i;
1999 uint32_t nttmp1, nttmp2;
e772353f 2000
1c611bbd 2001 if (nt1 == nt2) return 0;
2002
2003 nttmp1 = nt1;
2004 nttmp2 = nt2;
2005
2006 for (i = 1; i < 32768; i++) {
2007 nttmp1 = prng_successor(nttmp1, 1);
2008 if (nttmp1 == nt2) return i;
2009 nttmp2 = prng_successor(nttmp2, 1);
2010 if (nttmp2 == nt1) return -i;
2011 }
2012
2013 return(-99999); // either nt1 or nt2 are invalid nonces
e772353f 2014}
2015
e772353f 2016
1c611bbd 2017//-----------------------------------------------------------------------------
2018// Recover several bits of the cypher stream. This implements (first stages of)
2019// the algorithm described in "The Dark Side of Security by Obscurity and
2020// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2021// (article by Nicolas T. Courtois, 2009)
2022//-----------------------------------------------------------------------------
2023void ReaderMifare(bool first_try)
2024{
2025 // Mifare AUTH
2026 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2027 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2028 static uint8_t mf_nr_ar3;
e772353f 2029
f71f4deb 2030 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2031 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
7bc95e2e 2032
f71f4deb 2033 // free eventually allocated BigBuf memory. We want all for tracing.
2034 BigBuf_free();
2035
d2f487af 2036 iso14a_clear_trace();
7bc95e2e 2037 iso14a_set_tracing(TRUE);
e772353f 2038
1c611bbd 2039 byte_t nt_diff = 0;
6a1f2d82 2040 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2041 static byte_t par_low = 0;
2042 bool led_on = TRUE;
ca4714cd 2043 uint8_t uid[10] ={0};
1c611bbd 2044 uint32_t cuid;
e772353f 2045
6a1f2d82 2046 uint32_t nt = 0;
2ed270a8 2047 uint32_t previous_nt = 0;
1c611bbd 2048 static uint32_t nt_attacked = 0;
3fe4ff4f 2049 byte_t par_list[8] = {0x00};
2050 byte_t ks_list[8] = {0x00};
e772353f 2051
1c611bbd 2052 static uint32_t sync_time;
2053 static uint32_t sync_cycles;
2054 int catch_up_cycles = 0;
2055 int last_catch_up = 0;
2056 uint16_t consecutive_resyncs = 0;
2057 int isOK = 0;
e772353f 2058
1c611bbd 2059 if (first_try) {
1c611bbd 2060 mf_nr_ar3 = 0;
7bc95e2e 2061 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2062 sync_time = GetCountSspClk() & 0xfffffff8;
1c611bbd 2063 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2064 nt_attacked = 0;
2065 nt = 0;
6a1f2d82 2066 par[0] = 0;
1c611bbd 2067 }
2068 else {
2069 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1c611bbd 2070 mf_nr_ar3++;
2071 mf_nr_ar[3] = mf_nr_ar3;
6a1f2d82 2072 par[0] = par_low;
1c611bbd 2073 }
e30c654b 2074
15c4dc5a 2075 LED_A_ON();
2076 LED_B_OFF();
2077 LED_C_OFF();
1c611bbd 2078
7bc95e2e 2079
1c611bbd 2080 for(uint16_t i = 0; TRUE; i++) {
2081
2082 WDT_HIT();
e30c654b 2083
1c611bbd 2084 // Test if the action was cancelled
2085 if(BUTTON_PRESS()) {
2086 break;
2087 }
2088
2089 LED_C_ON();
e30c654b 2090
1c611bbd 2091 if(!iso14443a_select_card(uid, NULL, &cuid)) {
9492e0b0 2092 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1c611bbd 2093 continue;
2094 }
2095
9492e0b0 2096 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
1c611bbd 2097 catch_up_cycles = 0;
2098
2099 // if we missed the sync time already, advance to the next nonce repeat
7bc95e2e 2100 while(GetCountSspClk() > sync_time) {
9492e0b0 2101 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
1c611bbd 2102 }
e30c654b 2103
9492e0b0 2104 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2105 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2106
1c611bbd 2107 // Receive the (4 Byte) "random" nonce
6a1f2d82 2108 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2109 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
1c611bbd 2110 continue;
2111 }
2112
1c611bbd 2113 previous_nt = nt;
2114 nt = bytes_to_num(receivedAnswer, 4);
2115
2116 // Transmit reader nonce with fake par
9492e0b0 2117 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
1c611bbd 2118
2119 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2120 int nt_distance = dist_nt(previous_nt, nt);
2121 if (nt_distance == 0) {
2122 nt_attacked = nt;
2123 }
2124 else {
2125 if (nt_distance == -99999) { // invalid nonce received, try again
2126 continue;
2127 }
2128 sync_cycles = (sync_cycles - nt_distance);
9492e0b0 2129 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
1c611bbd 2130 continue;
2131 }
2132 }
2133
2134 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2135 catch_up_cycles = -dist_nt(nt_attacked, nt);
2136 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2137 catch_up_cycles = 0;
2138 continue;
2139 }
2140 if (catch_up_cycles == last_catch_up) {
2141 consecutive_resyncs++;
2142 }
2143 else {
2144 last_catch_up = catch_up_cycles;
2145 consecutive_resyncs = 0;
2146 }
2147 if (consecutive_resyncs < 3) {
9492e0b0 2148 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
1c611bbd 2149 }
2150 else {
2151 sync_cycles = sync_cycles + catch_up_cycles;
9492e0b0 2152 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
1c611bbd 2153 }
2154 continue;
2155 }
2156
2157 consecutive_resyncs = 0;
2158
2159 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
6a1f2d82 2160 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2161 {
9492e0b0 2162 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2163
2164 if (nt_diff == 0)
2165 {
6a1f2d82 2166 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2167 }
2168
2169 led_on = !led_on;
2170 if(led_on) LED_B_ON(); else LED_B_OFF();
2171
6a1f2d82 2172 par_list[nt_diff] = SwapBits(par[0], 8);
1c611bbd 2173 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2174
2175 // Test if the information is complete
2176 if (nt_diff == 0x07) {
2177 isOK = 1;
2178 break;
2179 }
2180
2181 nt_diff = (nt_diff + 1) & 0x07;
2182 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2183 par[0] = par_low;
1c611bbd 2184 } else {
2185 if (nt_diff == 0 && first_try)
2186 {
6a1f2d82 2187 par[0]++;
1c611bbd 2188 } else {
6a1f2d82 2189 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2190 }
2191 }
2192 }
2193
1c611bbd 2194
2195 mf_nr_ar[3] &= 0x1F;
2196
2197 byte_t buf[28];
2198 memcpy(buf + 0, uid, 4);
2199 num_to_bytes(nt, 4, buf + 4);
2200 memcpy(buf + 8, par_list, 8);
2201 memcpy(buf + 16, ks_list, 8);
2202 memcpy(buf + 24, mf_nr_ar, 4);
2203
2204 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2205
2206 // Thats it...
2207 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2208 LEDsoff();
7bc95e2e 2209
2210 iso14a_set_tracing(FALSE);
20f9a2a1 2211}
1c611bbd 2212
d2f487af 2213/**
2214 *MIFARE 1K simulate.
2215 *
2216 *@param flags :
2217 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2218 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2219 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2220 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2221 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2222 */
2223void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
20f9a2a1 2224{
50193c1e 2225 int cardSTATE = MFEMUL_NOFIELD;
8556b852 2226 int _7BUID = 0;
9ca155ba 2227 int vHf = 0; // in mV
8f51ddb0 2228 int res;
0a39986e
M
2229 uint32_t selTimer = 0;
2230 uint32_t authTimer = 0;
6a1f2d82 2231 uint16_t len = 0;
8f51ddb0 2232 uint8_t cardWRBL = 0;
9ca155ba
M
2233 uint8_t cardAUTHSC = 0;
2234 uint8_t cardAUTHKEY = 0xff; // no authentication
51969283 2235 uint32_t cardRr = 0;
9ca155ba 2236 uint32_t cuid = 0;
d2f487af 2237 //uint32_t rn_enc = 0;
51969283 2238 uint32_t ans = 0;
0014cb46
M
2239 uint32_t cardINTREG = 0;
2240 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2241 struct Crypto1State mpcs = {0, 0};
2242 struct Crypto1State *pcs;
2243 pcs = &mpcs;
d2f487af 2244 uint32_t numReads = 0;//Counts numer of times reader read a block
f71f4deb 2245 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2246 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2247 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2248 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
9ca155ba 2249
d2f487af 2250 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2251 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2252 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2253 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2254 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
9ca155ba 2255
d2f487af 2256 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2257 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
7bc95e2e 2258
d2f487af 2259 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2260 // This can be used in a reader-only attack.
2261 // (it can also be retrieved via 'hf 14a list', but hey...
2262 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2263 uint8_t ar_nr_collected = 0;
0014cb46 2264
f71f4deb 2265 // free eventually allocated BigBuf memory but keep Emulator Memory
2266 BigBuf_free_keep_EM();
0a39986e 2267 // clear trace
7bc95e2e 2268 iso14a_clear_trace();
2269 iso14a_set_tracing(TRUE);
51969283 2270
7bc95e2e 2271 // Authenticate response - nonce
51969283 2272 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
7bc95e2e 2273
d2f487af 2274 //-- Determine the UID
2275 // Can be set from emulator memory, incoming data
2276 // and can be 7 or 4 bytes long
7bc95e2e 2277 if (flags & FLAG_4B_UID_IN_DATA)
d2f487af 2278 {
2279 // 4B uid comes from data-portion of packet
2280 memcpy(rUIDBCC1,datain,4);
8556b852 2281 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
8556b852 2282
7bc95e2e 2283 } else if (flags & FLAG_7B_UID_IN_DATA) {
d2f487af 2284 // 7B uid comes from data-portion of packet
2285 memcpy(&rUIDBCC1[1],datain,3);
2286 memcpy(rUIDBCC2, datain+3, 4);
2287 _7BUID = true;
7bc95e2e 2288 } else {
d2f487af 2289 // get UID from emul memory
2290 emlGetMemBt(receivedCmd, 7, 1);
2291 _7BUID = !(receivedCmd[0] == 0x00);
2292 if (!_7BUID) { // ---------- 4BUID
2293 emlGetMemBt(rUIDBCC1, 0, 4);
2294 } else { // ---------- 7BUID
2295 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2296 emlGetMemBt(rUIDBCC2, 3, 4);
2297 }
2298 }
7bc95e2e 2299
d2f487af 2300 /*
2301 * Regardless of what method was used to set the UID, set fifth byte and modify
2302 * the ATQA for 4 or 7-byte UID
2303 */
d2f487af 2304 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
7bc95e2e 2305 if (_7BUID) {
d2f487af 2306 rATQA[0] = 0x44;
8556b852 2307 rUIDBCC1[0] = 0x88;
8556b852
M
2308 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2309 }
2310
9ca155ba 2311 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 2312 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
9ca155ba 2313
9ca155ba 2314
d2f487af 2315 if (MF_DBGLEVEL >= 1) {
2316 if (!_7BUID) {
b03c0f2d 2317 Dbprintf("4B UID: %02x%02x%02x%02x",
2318 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
7bc95e2e 2319 } else {
b03c0f2d 2320 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2321 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2322 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
d2f487af 2323 }
2324 }
7bc95e2e 2325
2326 bool finished = FALSE;
d2f487af 2327 while (!BUTTON_PRESS() && !finished) {
9ca155ba 2328 WDT_HIT();
9ca155ba
M
2329
2330 // find reader field
2331 // Vref = 3300mV, and an 10:1 voltage divider on the input
2332 // can measure voltages up to 33000 mV
2333 if (cardSTATE == MFEMUL_NOFIELD) {
2334 vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;
2335 if (vHf > MF_MINFIELDV) {
0014cb46 2336 cardSTATE_TO_IDLE();
9ca155ba
M
2337 LED_A_ON();
2338 }
2339 }
d2f487af 2340 if(cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2341
d2f487af 2342 //Now, get data
2343
6a1f2d82 2344 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2345 if (res == 2) { //Field is off!
2346 cardSTATE = MFEMUL_NOFIELD;
2347 LEDsoff();
2348 continue;
7bc95e2e 2349 } else if (res == 1) {
2350 break; //return value 1 means button press
2351 }
2352
d2f487af 2353 // REQ or WUP request in ANY state and WUP in HALTED state
2354 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2355 selTimer = GetTickCount();
2356 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2357 cardSTATE = MFEMUL_SELECT1;
2358
2359 // init crypto block
2360 LED_B_OFF();
2361 LED_C_OFF();
2362 crypto1_destroy(pcs);
2363 cardAUTHKEY = 0xff;
2364 continue;
0a39986e 2365 }
7bc95e2e 2366
50193c1e 2367 switch (cardSTATE) {
d2f487af 2368 case MFEMUL_NOFIELD:
2369 case MFEMUL_HALTED:
50193c1e 2370 case MFEMUL_IDLE:{
6a1f2d82 2371 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2372 break;
2373 }
2374 case MFEMUL_SELECT1:{
9ca155ba
M
2375 // select all
2376 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
d2f487af 2377 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2378 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2379 break;
9ca155ba
M
2380 }
2381
d2f487af 2382 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2383 {
2384 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2385 }
9ca155ba 2386 // select card
0a39986e
M
2387 if (len == 9 &&
2388 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
bfb6a143 2389 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
9ca155ba 2390 cuid = bytes_to_num(rUIDBCC1, 4);
8556b852
M
2391 if (!_7BUID) {
2392 cardSTATE = MFEMUL_WORK;
0014cb46
M
2393 LED_B_ON();
2394 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2395 break;
8556b852
M
2396 } else {
2397 cardSTATE = MFEMUL_SELECT2;
8556b852 2398 }
9ca155ba 2399 }
50193c1e
M
2400 break;
2401 }
d2f487af 2402 case MFEMUL_AUTH1:{
2403 if( len != 8)
2404 {
2405 cardSTATE_TO_IDLE();
6a1f2d82 2406 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2407 break;
2408 }
2409 uint32_t ar = bytes_to_num(receivedCmd, 4);
6a1f2d82 2410 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2411
2412 //Collect AR/NR
2413 if(ar_nr_collected < 2){
273b57a7 2414 if(ar_nr_responses[2] != ar)
2415 {// Avoid duplicates... probably not necessary, ar should vary.
d2f487af 2416 ar_nr_responses[ar_nr_collected*4] = cuid;
2417 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2418 ar_nr_responses[ar_nr_collected*4+2] = ar;
2419 ar_nr_responses[ar_nr_collected*4+3] = nr;
273b57a7 2420 ar_nr_collected++;
d2f487af 2421 }
2422 }
2423
2424 // --- crypto
2425 crypto1_word(pcs, ar , 1);
2426 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2427
2428 // test if auth OK
2429 if (cardRr != prng_successor(nonce, 64)){
b03c0f2d 2430 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2431 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2432 cardRr, prng_successor(nonce, 64));
7bc95e2e 2433 // Shouldn't we respond anything here?
d2f487af 2434 // Right now, we don't nack or anything, which causes the
2435 // reader to do a WUPA after a while. /Martin
b03c0f2d 2436 // -- which is the correct response. /piwi
d2f487af 2437 cardSTATE_TO_IDLE();
6a1f2d82 2438 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2439 break;
2440 }
2441
2442 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2443
2444 num_to_bytes(ans, 4, rAUTH_AT);
2445 // --- crypto
2446 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2447 LED_C_ON();
2448 cardSTATE = MFEMUL_WORK;
b03c0f2d 2449 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2450 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2451 GetTickCount() - authTimer);
d2f487af 2452 break;
2453 }
50193c1e 2454 case MFEMUL_SELECT2:{
7bc95e2e 2455 if (!len) {
6a1f2d82 2456 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2457 break;
2458 }
8556b852 2459 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
9ca155ba 2460 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
8556b852
M
2461 break;
2462 }
9ca155ba 2463
8556b852
M
2464 // select 2 card
2465 if (len == 9 &&
2466 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2467 EmSendCmd(rSAK, sizeof(rSAK));
8556b852
M
2468 cuid = bytes_to_num(rUIDBCC2, 4);
2469 cardSTATE = MFEMUL_WORK;
2470 LED_B_ON();
0014cb46 2471 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
8556b852
M
2472 break;
2473 }
0014cb46
M
2474
2475 // i guess there is a command). go into the work state.
7bc95e2e 2476 if (len != 4) {
6a1f2d82 2477 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2478 break;
2479 }
0014cb46 2480 cardSTATE = MFEMUL_WORK;
d2f487af 2481 //goto lbWORK;
2482 //intentional fall-through to the next case-stmt
50193c1e 2483 }
51969283 2484
7bc95e2e 2485 case MFEMUL_WORK:{
2486 if (len == 0) {
6a1f2d82 2487 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2488 break;
2489 }
2490
d2f487af 2491 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2492
7bc95e2e 2493 if(encrypted_data) {
51969283
M
2494 // decrypt seqence
2495 mf_crypto1_decrypt(pcs, receivedCmd, len);
d2f487af 2496 }
7bc95e2e 2497
d2f487af 2498 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2499 authTimer = GetTickCount();
2500 cardAUTHSC = receivedCmd[1] / 4; // received block num
2501 cardAUTHKEY = receivedCmd[0] - 0x60;
2502 crypto1_destroy(pcs);//Added by martin
2503 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2504
d2f487af 2505 if (!encrypted_data) { // first authentication
b03c0f2d 2506 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
51969283 2507
d2f487af 2508 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2509 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
7bc95e2e 2510 } else { // nested authentication
b03c0f2d 2511 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
7bc95e2e 2512 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2513 num_to_bytes(ans, 4, rAUTH_AT);
2514 }
2515 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2516 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2517 cardSTATE = MFEMUL_AUTH1;
2518 break;
51969283 2519 }
7bc95e2e 2520
8f51ddb0
M
2521 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2522 // BUT... ACK --> NACK
2523 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2524 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2525 break;
2526 }
2527
2528 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2529 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2530 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2531 break;
0a39986e
M
2532 }
2533
7bc95e2e 2534 if(len != 4) {
6a1f2d82 2535 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2536 break;
2537 }
d2f487af 2538
2539 if(receivedCmd[0] == 0x30 // read block
2540 || receivedCmd[0] == 0xA0 // write block
b03c0f2d 2541 || receivedCmd[0] == 0xC0 // inc
2542 || receivedCmd[0] == 0xC1 // dec
2543 || receivedCmd[0] == 0xC2 // restore
7bc95e2e 2544 || receivedCmd[0] == 0xB0) { // transfer
2545 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2546 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2547 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2548 break;
2549 }
2550
7bc95e2e 2551 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2552 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
d2f487af 2553 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2554 break;
2555 }
d2f487af 2556 }
2557 // read block
2558 if (receivedCmd[0] == 0x30) {
b03c0f2d 2559 if (MF_DBGLEVEL >= 4) {
d2f487af 2560 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2561 }
8f51ddb0
M
2562 emlGetMem(response, receivedCmd[1], 1);
2563 AppendCrc14443a(response, 16);
6a1f2d82 2564 mf_crypto1_encrypt(pcs, response, 18, response_par);
2565 EmSendCmdPar(response, 18, response_par);
d2f487af 2566 numReads++;
7bc95e2e 2567 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
d2f487af 2568 Dbprintf("%d reads done, exiting", numReads);
2569 finished = true;
2570 }
0a39986e
M
2571 break;
2572 }
0a39986e 2573 // write block
d2f487af 2574 if (receivedCmd[0] == 0xA0) {
b03c0f2d 2575 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
8f51ddb0 2576 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2577 cardSTATE = MFEMUL_WRITEBL2;
2578 cardWRBL = receivedCmd[1];
0a39986e 2579 break;
7bc95e2e 2580 }
0014cb46 2581 // increment, decrement, restore
d2f487af 2582 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
b03c0f2d 2583 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2584 if (emlCheckValBl(receivedCmd[1])) {
2585 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2586 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2587 break;
2588 }
2589 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2590 if (receivedCmd[0] == 0xC1)
2591 cardSTATE = MFEMUL_INTREG_INC;
2592 if (receivedCmd[0] == 0xC0)
2593 cardSTATE = MFEMUL_INTREG_DEC;
2594 if (receivedCmd[0] == 0xC2)
2595 cardSTATE = MFEMUL_INTREG_REST;
2596 cardWRBL = receivedCmd[1];
0014cb46
M
2597 break;
2598 }
0014cb46 2599 // transfer
d2f487af 2600 if (receivedCmd[0] == 0xB0) {
b03c0f2d 2601 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
0014cb46
M
2602 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2603 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2604 else
2605 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2606 break;
2607 }
9ca155ba 2608 // halt
d2f487af 2609 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
9ca155ba 2610 LED_B_OFF();
0a39986e 2611 LED_C_OFF();
0014cb46
M
2612 cardSTATE = MFEMUL_HALTED;
2613 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2614 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2615 break;
9ca155ba 2616 }
d2f487af 2617 // RATS
2618 if (receivedCmd[0] == 0xe0) {//RATS
8f51ddb0
M
2619 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2620 break;
2621 }
d2f487af 2622 // command not allowed
2623 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2624 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2625 break;
8f51ddb0
M
2626 }
2627 case MFEMUL_WRITEBL2:{
2628 if (len == 18){
2629 mf_crypto1_decrypt(pcs, receivedCmd, len);
2630 emlSetMem(receivedCmd, cardWRBL, 1);
2631 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2632 cardSTATE = MFEMUL_WORK;
51969283 2633 } else {
0014cb46 2634 cardSTATE_TO_IDLE();
6a1f2d82 2635 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2636 }
8f51ddb0 2637 break;
50193c1e 2638 }
0014cb46
M
2639
2640 case MFEMUL_INTREG_INC:{
2641 mf_crypto1_decrypt(pcs, receivedCmd, len);
2642 memcpy(&ans, receivedCmd, 4);
2643 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2644 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2645 cardSTATE_TO_IDLE();
2646 break;
7bc95e2e 2647 }
6a1f2d82 2648 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2649 cardINTREG = cardINTREG + ans;
2650 cardSTATE = MFEMUL_WORK;
2651 break;
2652 }
2653 case MFEMUL_INTREG_DEC:{
2654 mf_crypto1_decrypt(pcs, receivedCmd, len);
2655 memcpy(&ans, receivedCmd, 4);
2656 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2657 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2658 cardSTATE_TO_IDLE();
2659 break;
2660 }
6a1f2d82 2661 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2662 cardINTREG = cardINTREG - ans;
2663 cardSTATE = MFEMUL_WORK;
2664 break;
2665 }
2666 case MFEMUL_INTREG_REST:{
2667 mf_crypto1_decrypt(pcs, receivedCmd, len);
2668 memcpy(&ans, receivedCmd, 4);
2669 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2670 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2671 cardSTATE_TO_IDLE();
2672 break;
2673 }
6a1f2d82 2674 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2675 cardSTATE = MFEMUL_WORK;
2676 break;
2677 }
50193c1e 2678 }
50193c1e
M
2679 }
2680
9ca155ba
M
2681 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2682 LEDsoff();
2683
d2f487af 2684 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2685 {
2686 //May just aswell send the collected ar_nr in the response aswell
2687 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2688 }
d714d3ef 2689
d2f487af 2690 if(flags & FLAG_NR_AR_ATTACK)
2691 {
7bc95e2e 2692 if(ar_nr_collected > 1) {
d2f487af 2693 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
d714d3ef 2694 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
d2f487af 2695 ar_nr_responses[0], // UID
2696 ar_nr_responses[1], //NT
2697 ar_nr_responses[2], //AR1
2698 ar_nr_responses[3], //NR1
2699 ar_nr_responses[6], //AR2
2700 ar_nr_responses[7] //NR2
2701 );
7bc95e2e 2702 } else {
d2f487af 2703 Dbprintf("Failed to obtain two AR/NR pairs!");
7bc95e2e 2704 if(ar_nr_collected >0) {
d714d3ef 2705 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
d2f487af 2706 ar_nr_responses[0], // UID
2707 ar_nr_responses[1], //NT
2708 ar_nr_responses[2], //AR1
2709 ar_nr_responses[3] //NR1
2710 );
2711 }
2712 }
2713 }
0014cb46 2714 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, traceLen);
15c4dc5a 2715}
b62a5a84 2716
d2f487af 2717
2718
b62a5a84
M
2719//-----------------------------------------------------------------------------
2720// MIFARE sniffer.
2721//
2722//-----------------------------------------------------------------------------
5cd9ec01
M
2723void RAMFUNC SniffMifare(uint8_t param) {
2724 // param:
2725 // bit 0 - trigger from first card answer
2726 // bit 1 - trigger from first reader 7-bit request
39864b0b
M
2727
2728 // C(red) A(yellow) B(green)
b62a5a84
M
2729 LEDsoff();
2730 // init trace buffer
991f13f2 2731 iso14a_clear_trace();
2732 iso14a_set_tracing(TRUE);
b62a5a84 2733
b62a5a84
M
2734 // The command (reader -> tag) that we're receiving.
2735 // The length of a received command will in most cases be no more than 18 bytes.
2736 // So 32 should be enough!
f71f4deb 2737 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2738 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
b62a5a84 2739 // The response (tag -> reader) that we're receiving.
f71f4deb 2740 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2741 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
b62a5a84
M
2742
2743 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2744 // into trace, along with its length and other annotations.
2745 //uint8_t *trace = (uint8_t *)BigBuf;
2746
f71f4deb 2747 // free eventually allocated BigBuf memory
2748 BigBuf_free();
2749 // allocate the DMA buffer, used to stream samples from the FPGA
2750 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 2751 uint8_t *data = dmaBuf;
2752 uint8_t previous_data = 0;
5cd9ec01
M
2753 int maxDataLen = 0;
2754 int dataLen = 0;
7bc95e2e 2755 bool ReaderIsActive = FALSE;
2756 bool TagIsActive = FALSE;
2757
2758 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
b62a5a84
M
2759
2760 // Set up the demodulator for tag -> reader responses.
6a1f2d82 2761 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
2762
2763 // Set up the demodulator for the reader -> tag commands
6a1f2d82 2764 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
2765
2766 // Setup for the DMA.
7bc95e2e 2767 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 2768
b62a5a84 2769 LED_D_OFF();
39864b0b
M
2770
2771 // init sniffer
2772 MfSniffInit();
b62a5a84 2773
b62a5a84 2774 // And now we loop, receiving samples.
7bc95e2e 2775 for(uint32_t sniffCounter = 0; TRUE; ) {
2776
5cd9ec01
M
2777 if(BUTTON_PRESS()) {
2778 DbpString("cancelled by button");
7bc95e2e 2779 break;
5cd9ec01
M
2780 }
2781
b62a5a84
M
2782 LED_A_ON();
2783 WDT_HIT();
39864b0b 2784
7bc95e2e 2785 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2786 // check if a transaction is completed (timeout after 2000ms).
2787 // if yes, stop the DMA transfer and send what we have so far to the client
2788 if (MfSniffSend(2000)) {
2789 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2790 sniffCounter = 0;
2791 data = dmaBuf;
2792 maxDataLen = 0;
2793 ReaderIsActive = FALSE;
2794 TagIsActive = FALSE;
2795 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 2796 }
39864b0b 2797 }
7bc95e2e 2798
2799 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2800 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2801 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2802 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2803 } else {
2804 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
5cd9ec01
M
2805 }
2806 // test for length of buffer
7bc95e2e 2807 if(dataLen > maxDataLen) { // we are more behind than ever...
2808 maxDataLen = dataLen;
f71f4deb 2809 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 2810 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 2811 break;
b62a5a84
M
2812 }
2813 }
5cd9ec01 2814 if(dataLen < 1) continue;
b62a5a84 2815
7bc95e2e 2816 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
2817 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2818 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2819 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
55acbb2a 2820 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
2821 }
2822 // secondary buffer sets as primary, secondary buffer was stopped
2823 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2824 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
2825 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2826 }
5cd9ec01
M
2827
2828 LED_A_OFF();
b62a5a84 2829
7bc95e2e 2830 if (sniffCounter & 0x01) {
b62a5a84 2831
7bc95e2e 2832 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2833 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2834 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2835 LED_C_INV();
6a1f2d82 2836 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 2837
7bc95e2e 2838 /* And ready to receive another command. */
2839 UartReset();
2840
2841 /* And also reset the demod code */
2842 DemodReset();
2843 }
2844 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2845 }
2846
2847 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2848 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2849 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2850 LED_C_INV();
b62a5a84 2851
6a1f2d82 2852 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 2853
7bc95e2e 2854 // And ready to receive another response.
2855 DemodReset();
2856 }
2857 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2858 }
b62a5a84
M
2859 }
2860
7bc95e2e 2861 previous_data = *data;
2862 sniffCounter++;
5cd9ec01 2863 data++;
d714d3ef 2864 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01 2865 data = dmaBuf;
b62a5a84 2866 }
7bc95e2e 2867
b62a5a84
M
2868 } // main cycle
2869
2870 DbpString("COMMAND FINISHED");
2871
55acbb2a 2872 FpgaDisableSscDma();
39864b0b
M
2873 MfSniffEnd();
2874
7bc95e2e 2875 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
b62a5a84 2876 LEDsoff();
3803d529 2877}
Impressum, Datenschutz