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15c4dc5a 1//-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
e30c654b 13#include "proxmark3.h"
15c4dc5a 14#include "apps.h"
f7e3ed82 15#include "util.h"
9ab7a6c7 16#include "string.h"
902cb3c0 17#include "cmd.h"
9ab7a6c7 18
15c4dc5a 19#include "iso14443crc.h"
534983d7 20#include "iso14443a.h"
20f9a2a1
M
21#include "crapto1.h"
22#include "mifareutil.h"
3000dc4e 23#include "BigBuf.h"
534983d7 24static uint32_t iso14a_timeout;
1e262141 25int rsamples = 0;
1e262141 26uint8_t trigger = 0;
b0127e65 27// the block number for the ISO14443-4 PCB
28static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 29
7bc95e2e 30//
31// ISO14443 timing:
32//
33// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
34#define REQUEST_GUARD_TIME (7000/16 + 1)
35// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
36#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
37// bool LastCommandWasRequest = FALSE;
38
39//
40// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
41//
d714d3ef 42// When the PM acts as reader and is receiving tag data, it takes
43// 3 ticks delay in the AD converter
44// 16 ticks until the modulation detector completes and sets curbit
45// 8 ticks until bit_to_arm is assigned from curbit
46// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 47// 4*16 ticks until we measure the time
48// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 49#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 50
51// When the PM acts as a reader and is sending, it takes
52// 4*16 ticks until we can write data to the sending hold register
53// 8*16 ticks until the SHR is transferred to the Sending Shift Register
54// 8 ticks until the first transfer starts
55// 8 ticks later the FPGA samples the data
56// 1 tick to assign mod_sig_coil
57#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
58
59// When the PM acts as tag and is receiving it takes
d714d3ef 60// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 61// 3 ticks for the A/D conversion,
62// 8 ticks on average until the start of the SSC transfer,
63// 8 ticks until the SSC samples the first data
64// 7*16 ticks to complete the transfer from FPGA to ARM
65// 8 ticks until the next ssp_clk rising edge
d714d3ef 66// 4*16 ticks until we measure the time
7bc95e2e 67// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 68#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 69
70// The FPGA will report its internal sending delay in
71uint16_t FpgaSendQueueDelay;
72// the 5 first bits are the number of bits buffered in mod_sig_buf
73// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
74#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
75
76// When the PM acts as tag and is sending, it takes
d714d3ef 77// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 78// 8*16 ticks until the SHR is transferred to the Sending Shift Register
79// 8 ticks until the first transfer starts
80// 8 ticks later the FPGA samples the data
81// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
82// + 1 tick to assign mod_sig_coil
d714d3ef 83#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 84
85// When the PM acts as sniffer and is receiving tag data, it takes
86// 3 ticks A/D conversion
d714d3ef 87// 14 ticks to complete the modulation detection
88// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 89// + the delays in transferring data - which is the same for
90// sniffing reader and tag data and therefore not relevant
d714d3ef 91#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 92
d714d3ef 93// When the PM acts as sniffer and is receiving reader data, it takes
94// 2 ticks delay in analogue RF receiver (for the falling edge of the
95// start bit, which marks the start of the communication)
7bc95e2e 96// 3 ticks A/D conversion
d714d3ef 97// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 98// + the delays in transferring data - which is the same for
99// sniffing reader and tag data and therefore not relevant
d714d3ef 100#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 101
102//variables used for timing purposes:
103//these are in ssp_clk cycles:
6a1f2d82 104static uint32_t NextTransferTime;
105static uint32_t LastTimeProxToAirStart;
106static uint32_t LastProxToAirDuration;
7bc95e2e 107
108
109
8f51ddb0 110// CARD TO READER - manchester
72934aa3 111// Sequence D: 11110000 modulation with subcarrier during first half
112// Sequence E: 00001111 modulation with subcarrier during second half
113// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 114// READER TO CARD - miller
72934aa3 115// Sequence X: 00001100 drop after half a period
116// Sequence Y: 00000000 no drop
117// Sequence Z: 11000000 drop at start
118#define SEC_D 0xf0
119#define SEC_E 0x0f
120#define SEC_F 0x00
121#define SEC_X 0x0c
122#define SEC_Y 0x00
123#define SEC_Z 0xc0
15c4dc5a 124
1e262141 125const uint8_t OddByteParity[256] = {
15c4dc5a 126 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
127 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
142};
143
902cb3c0 144void iso14a_set_trigger(bool enable) {
534983d7 145 trigger = enable;
146}
147
d19929cb 148
d19929cb 149
b0127e65 150void iso14a_set_timeout(uint32_t timeout) {
151 iso14a_timeout = timeout;
152}
8556b852 153
15c4dc5a 154//-----------------------------------------------------------------------------
155// Generate the parity value for a byte sequence
e30c654b 156//
15c4dc5a 157//-----------------------------------------------------------------------------
20f9a2a1
M
158byte_t oddparity (const byte_t bt)
159{
5f6d6c90 160 return OddByteParity[bt];
20f9a2a1
M
161}
162
6a1f2d82 163void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
15c4dc5a 164{
6a1f2d82 165 uint16_t paritybit_cnt = 0;
166 uint16_t paritybyte_cnt = 0;
167 uint8_t parityBits = 0;
168
169 for (uint16_t i = 0; i < iLen; i++) {
170 // Generate the parity bits
171 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
172 if (paritybit_cnt == 7) {
173 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
174 parityBits = 0; // and advance to next Parity Byte
175 paritybyte_cnt++;
176 paritybit_cnt = 0;
177 } else {
178 paritybit_cnt++;
179 }
5f6d6c90 180 }
6a1f2d82 181
182 // save remaining parity bits
183 par[paritybyte_cnt] = parityBits;
184
15c4dc5a 185}
186
534983d7 187void AppendCrc14443a(uint8_t* data, int len)
15c4dc5a 188{
5f6d6c90 189 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 190}
191
7bc95e2e 192//=============================================================================
193// ISO 14443 Type A - Miller decoder
194//=============================================================================
195// Basics:
196// This decoder is used when the PM3 acts as a tag.
197// The reader will generate "pauses" by temporarily switching of the field.
198// At the PM3 antenna we will therefore measure a modulated antenna voltage.
199// The FPGA does a comparison with a threshold and would deliver e.g.:
200// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
201// The Miller decoder needs to identify the following sequences:
202// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
203// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
204// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
205// Note 1: the bitstream may start at any time. We therefore need to sync.
206// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 207//-----------------------------------------------------------------------------
b62a5a84 208static tUart Uart;
15c4dc5a 209
d7aa3739 210// Lookup-Table to decide if 4 raw bits are a modulation.
211// We accept two or three consecutive "0" in any position with the rest "1"
212const bool Mod_Miller_LUT[] = {
213 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
214 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
215};
216#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
217#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
218
7bc95e2e 219void UartReset()
15c4dc5a 220{
7bc95e2e 221 Uart.state = STATE_UNSYNCD;
222 Uart.bitCount = 0;
223 Uart.len = 0; // number of decoded data bytes
6a1f2d82 224 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 225 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 226 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 227 Uart.twoBits = 0x0000; // buffer for 2 Bits
228 Uart.highCnt = 0;
229 Uart.startTime = 0;
230 Uart.endTime = 0;
231}
15c4dc5a 232
6a1f2d82 233void UartInit(uint8_t *data, uint8_t *parity)
234{
235 Uart.output = data;
236 Uart.parity = parity;
237 UartReset();
238}
d714d3ef 239
7bc95e2e 240// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
241static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
242{
15c4dc5a 243
7bc95e2e 244 Uart.twoBits = (Uart.twoBits << 8) | bit;
245
0c8d25eb 246 if (Uart.state == STATE_UNSYNCD) { // not yet synced
3fe4ff4f 247
0c8d25eb 248 if (Uart.highCnt < 2) { // wait for a stable unmodulated signal
7bc95e2e 249 if (Uart.twoBits == 0xffff) {
250 Uart.highCnt++;
251 } else {
252 Uart.highCnt = 0;
15c4dc5a 253 }
7bc95e2e 254 } else {
0c8d25eb 255 Uart.syncBit = 0xFFFF; // not set
256 // we look for a ...1111111100x11111xxxxxx pattern (the start bit)
257 if ((Uart.twoBits & 0xDF00) == 0x1F00) Uart.syncBit = 8; // mask is 11x11111 xxxxxxxx,
258 // check for 00x11111 xxxxxxxx
259 else if ((Uart.twoBits & 0xEF80) == 0x8F80) Uart.syncBit = 7; // both masks shifted right one bit, left padded with '1'
260 else if ((Uart.twoBits & 0xF7C0) == 0xC7C0) Uart.syncBit = 6; // ...
261 else if ((Uart.twoBits & 0xFBE0) == 0xE3E0) Uart.syncBit = 5;
262 else if ((Uart.twoBits & 0xFDF0) == 0xF1F0) Uart.syncBit = 4;
263 else if ((Uart.twoBits & 0xFEF8) == 0xF8F8) Uart.syncBit = 3;
264 else if ((Uart.twoBits & 0xFF7C) == 0xFC7C) Uart.syncBit = 2;
265 else if ((Uart.twoBits & 0xFFBE) == 0xFE3E) Uart.syncBit = 1;
266 if (Uart.syncBit != 0xFFFF) { // found a sync bit
7bc95e2e 267 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
268 Uart.startTime -= Uart.syncBit;
d7aa3739 269 Uart.endTime = Uart.startTime;
7bc95e2e 270 Uart.state = STATE_START_OF_COMMUNICATION;
15c4dc5a 271 }
7bc95e2e 272 }
15c4dc5a 273
7bc95e2e 274 } else {
15c4dc5a 275
d7aa3739 276 if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
277 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
278 UartReset();
d7aa3739 279 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 280 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
281 UartReset();
7bc95e2e 282 } else {
283 Uart.bitCount++;
284 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
285 Uart.state = STATE_MILLER_Z;
286 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
287 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
288 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
289 Uart.parityBits <<= 1; // make room for the parity bit
290 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
291 Uart.bitCount = 0;
292 Uart.shiftReg = 0;
6a1f2d82 293 if((Uart.len&0x0007) == 0) { // every 8 data bytes
294 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
295 Uart.parityBits = 0;
296 }
15c4dc5a 297 }
7bc95e2e 298 }
d7aa3739 299 }
300 } else {
301 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 302 Uart.bitCount++;
303 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
304 Uart.state = STATE_MILLER_X;
305 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
306 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
307 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
308 Uart.parityBits <<= 1; // make room for the new parity bit
309 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
310 Uart.bitCount = 0;
311 Uart.shiftReg = 0;
6a1f2d82 312 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
313 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
314 Uart.parityBits = 0;
315 }
7bc95e2e 316 }
d7aa3739 317 } else { // no modulation in both halves - Sequence Y
7bc95e2e 318 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 319 Uart.state = STATE_UNSYNCD;
6a1f2d82 320 Uart.bitCount--; // last "0" was part of EOC sequence
321 Uart.shiftReg <<= 1; // drop it
322 if(Uart.bitCount > 0) { // if we decoded some bits
323 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
324 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
325 Uart.parityBits <<= 1; // add a (void) parity bit
326 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
327 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
328 return TRUE;
329 } else if (Uart.len & 0x0007) { // there are some parity bits to store
330 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
331 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 332 }
333 if (Uart.len) {
6a1f2d82 334 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 335 } else {
0c8d25eb 336 UartReset(); // Nothing received - start over
337 Uart.highCnt = 1;
7bc95e2e 338 }
15c4dc5a 339 }
7bc95e2e 340 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
341 UartReset();
0c8d25eb 342 Uart.highCnt = 1;
7bc95e2e 343 } else { // a logic "0"
344 Uart.bitCount++;
345 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
346 Uart.state = STATE_MILLER_Y;
347 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
348 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
349 Uart.parityBits <<= 1; // make room for the parity bit
350 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
351 Uart.bitCount = 0;
352 Uart.shiftReg = 0;
6a1f2d82 353 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
354 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
355 Uart.parityBits = 0;
356 }
15c4dc5a 357 }
358 }
d7aa3739 359 }
15c4dc5a 360 }
7bc95e2e 361
362 }
15c4dc5a 363
7bc95e2e 364 return FALSE; // not finished yet, need more data
15c4dc5a 365}
366
7bc95e2e 367
368
15c4dc5a 369//=============================================================================
e691fc45 370// ISO 14443 Type A - Manchester decoder
15c4dc5a 371//=============================================================================
e691fc45 372// Basics:
7bc95e2e 373// This decoder is used when the PM3 acts as a reader.
e691fc45 374// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
375// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
376// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
377// The Manchester decoder needs to identify the following sequences:
378// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
379// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
380// 8 ticks unmodulated: Sequence F = end of communication
381// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 382// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 383// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 384static tDemod Demod;
15c4dc5a 385
d7aa3739 386// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 387// We accept three or four "1" in any position
7bc95e2e 388const bool Mod_Manchester_LUT[] = {
d7aa3739 389 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 390 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 391};
392
393#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
394#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 395
2f2d9fc5 396
7bc95e2e 397void DemodReset()
e691fc45 398{
7bc95e2e 399 Demod.state = DEMOD_UNSYNCD;
400 Demod.len = 0; // number of decoded data bytes
6a1f2d82 401 Demod.parityLen = 0;
7bc95e2e 402 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
403 Demod.parityBits = 0; //
404 Demod.collisionPos = 0; // Position of collision bit
405 Demod.twoBits = 0xffff; // buffer for 2 Bits
406 Demod.highCnt = 0;
407 Demod.startTime = 0;
408 Demod.endTime = 0;
e691fc45 409}
15c4dc5a 410
6a1f2d82 411void DemodInit(uint8_t *data, uint8_t *parity)
412{
413 Demod.output = data;
414 Demod.parity = parity;
415 DemodReset();
416}
417
7bc95e2e 418// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
419static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
e691fc45 420{
7bc95e2e 421
422 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 423
7bc95e2e 424 if (Demod.state == DEMOD_UNSYNCD) {
425
426 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
427 if (Demod.twoBits == 0x0000) {
428 Demod.highCnt++;
429 } else {
430 Demod.highCnt = 0;
431 }
432 } else {
433 Demod.syncBit = 0xFFFF; // not set
434 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
435 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
436 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
437 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
438 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
439 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
440 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
441 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 442 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 443 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
444 Demod.startTime -= Demod.syncBit;
445 Demod.bitCount = offset; // number of decoded data bits
e691fc45 446 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 447 }
7bc95e2e 448 }
15c4dc5a 449
7bc95e2e 450 } else {
15c4dc5a 451
7bc95e2e 452 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
453 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 454 if (!Demod.collisionPos) {
455 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
456 }
457 } // modulation in first half only - Sequence D = 1
7bc95e2e 458 Demod.bitCount++;
459 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
460 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 461 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 462 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 463 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
464 Demod.bitCount = 0;
465 Demod.shiftReg = 0;
6a1f2d82 466 if((Demod.len&0x0007) == 0) { // every 8 data bytes
467 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
468 Demod.parityBits = 0;
469 }
15c4dc5a 470 }
7bc95e2e 471 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
472 } else { // no modulation in first half
473 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 474 Demod.bitCount++;
7bc95e2e 475 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 476 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 477 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 478 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 479 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
480 Demod.bitCount = 0;
481 Demod.shiftReg = 0;
6a1f2d82 482 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
483 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
484 Demod.parityBits = 0;
485 }
15c4dc5a 486 }
7bc95e2e 487 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 488 } else { // no modulation in both halves - End of communication
6a1f2d82 489 if(Demod.bitCount > 0) { // there are some remaining data bits
490 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
491 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
492 Demod.parityBits <<= 1; // add a (void) parity bit
493 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
494 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
495 return TRUE;
496 } else if (Demod.len & 0x0007) { // there are some parity bits to store
497 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
498 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 499 }
500 if (Demod.len) {
d7aa3739 501 return TRUE; // we are finished with decoding the raw data sequence
502 } else { // nothing received. Start over
503 DemodReset();
e691fc45 504 }
15c4dc5a 505 }
7bc95e2e 506 }
e691fc45 507
508 }
15c4dc5a 509
e691fc45 510 return FALSE; // not finished yet, need more data
15c4dc5a 511}
512
513//=============================================================================
514// Finally, a `sniffer' for ISO 14443 Type A
515// Both sides of communication!
516//=============================================================================
517
518//-----------------------------------------------------------------------------
519// Record the sequence of commands sent by the reader to the tag, with
520// triggering so that we start recording at the point that the tag is moved
521// near the reader.
522//-----------------------------------------------------------------------------
5cd9ec01
M
523void RAMFUNC SnoopIso14443a(uint8_t param) {
524 // param:
525 // bit 0 - trigger from first card answer
526 // bit 1 - trigger from first reader 7-bit request
527
528 LEDsoff();
5cd9ec01
M
529
530 // We won't start recording the frames that we acquire until we trigger;
531 // a good trigger condition to get started is probably when we see a
532 // response from the tag.
533 // triggered == FALSE -- to wait first for card
7bc95e2e 534 bool triggered = !(param & 0x03);
535
f71f4deb 536 // Allocate memory from BigBuf for some buffers
537 // free all previous allocations first
538 BigBuf_free();
539
5cd9ec01 540 // The command (reader -> tag) that we're receiving.
f71f4deb 541 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
542 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 543
5cd9ec01 544 // The response (tag -> reader) that we're receiving.
f71f4deb 545 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
546 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
547
548 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 549 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
550
551 // init trace buffer
3000dc4e
MHS
552 clear_trace();
553 set_tracing(TRUE);
f71f4deb 554
7bc95e2e 555 uint8_t *data = dmaBuf;
556 uint8_t previous_data = 0;
5cd9ec01
M
557 int maxDataLen = 0;
558 int dataLen = 0;
7bc95e2e 559 bool TagIsActive = FALSE;
560 bool ReaderIsActive = FALSE;
561
562 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
15c4dc5a 563
5cd9ec01 564 // Set up the demodulator for tag -> reader responses.
6a1f2d82 565 DemodInit(receivedResponse, receivedResponsePar);
566
5cd9ec01 567 // Set up the demodulator for the reader -> tag commands
6a1f2d82 568 UartInit(receivedCmd, receivedCmdPar);
569
7bc95e2e 570 // Setup and start DMA.
5cd9ec01 571 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 572
5cd9ec01 573 // And now we loop, receiving samples.
7bc95e2e 574 for(uint32_t rsamples = 0; TRUE; ) {
575
5cd9ec01
M
576 if(BUTTON_PRESS()) {
577 DbpString("cancelled by button");
7bc95e2e 578 break;
5cd9ec01 579 }
15c4dc5a 580
5cd9ec01
M
581 LED_A_ON();
582 WDT_HIT();
15c4dc5a 583
5cd9ec01
M
584 int register readBufDataP = data - dmaBuf;
585 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
586 if (readBufDataP <= dmaBufDataP){
587 dataLen = dmaBufDataP - readBufDataP;
588 } else {
7bc95e2e 589 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
590 }
591 // test for length of buffer
592 if(dataLen > maxDataLen) {
593 maxDataLen = dataLen;
f71f4deb 594 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 595 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
596 break;
5cd9ec01
M
597 }
598 }
599 if(dataLen < 1) continue;
600
601 // primary buffer was stopped( <-- we lost data!
602 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
603 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
604 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 605 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
606 }
607 // secondary buffer sets as primary, secondary buffer was stopped
608 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
609 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
610 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
611 }
612
613 LED_A_OFF();
7bc95e2e 614
615 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 616
7bc95e2e 617 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
618 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
619 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
620 LED_C_ON();
5cd9ec01 621
7bc95e2e 622 // check - if there is a short 7bit request from reader
623 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 624
7bc95e2e 625 if(triggered) {
6a1f2d82 626 if (!LogTrace(receivedCmd,
627 Uart.len,
628 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
629 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
630 Uart.parity,
631 TRUE)) break;
7bc95e2e 632 }
633 /* And ready to receive another command. */
634 UartReset();
635 /* And also reset the demod code, which might have been */
636 /* false-triggered by the commands from the reader. */
637 DemodReset();
638 LED_B_OFF();
639 }
640 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 641 }
3be2a5ae 642
7bc95e2e 643 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
644 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
645 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
646 LED_B_ON();
5cd9ec01 647
6a1f2d82 648 if (!LogTrace(receivedResponse,
649 Demod.len,
650 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
651 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
652 Demod.parity,
653 FALSE)) break;
5cd9ec01 654
7bc95e2e 655 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 656
7bc95e2e 657 // And ready to receive another response.
658 DemodReset();
659 LED_C_OFF();
660 }
661 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
662 }
5cd9ec01
M
663 }
664
7bc95e2e 665 previous_data = *data;
666 rsamples++;
5cd9ec01 667 data++;
d714d3ef 668 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
669 data = dmaBuf;
670 }
671 } // main cycle
672
673 DbpString("COMMAND FINISHED");
15c4dc5a 674
7bc95e2e 675 FpgaDisableSscDma();
676 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
3000dc4e 677 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
5cd9ec01 678 LEDsoff();
15c4dc5a 679}
680
15c4dc5a 681//-----------------------------------------------------------------------------
682// Prepare tag messages
683//-----------------------------------------------------------------------------
6a1f2d82 684static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
15c4dc5a 685{
8f51ddb0 686 ToSendReset();
15c4dc5a 687
688 // Correction bit, might be removed when not needed
689 ToSendStuffBit(0);
690 ToSendStuffBit(0);
691 ToSendStuffBit(0);
692 ToSendStuffBit(0);
693 ToSendStuffBit(1); // 1
694 ToSendStuffBit(0);
695 ToSendStuffBit(0);
696 ToSendStuffBit(0);
8f51ddb0 697
15c4dc5a 698 // Send startbit
72934aa3 699 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 700 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 701
6a1f2d82 702 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 703 uint8_t b = cmd[i];
15c4dc5a 704
705 // Data bits
6a1f2d82 706 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 707 if(b & 1) {
72934aa3 708 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 709 } else {
72934aa3 710 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
711 }
712 b >>= 1;
713 }
15c4dc5a 714
0014cb46 715 // Get the parity bit
6a1f2d82 716 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 717 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 718 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 719 } else {
72934aa3 720 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 721 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 722 }
8f51ddb0 723 }
15c4dc5a 724
8f51ddb0
M
725 // Send stopbit
726 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 727
8f51ddb0
M
728 // Convert from last byte pos to length
729 ToSendMax++;
8f51ddb0
M
730}
731
6a1f2d82 732static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
733{
734 uint8_t par[MAX_PARITY_SIZE];
735
736 GetParity(cmd, len, par);
737 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 738}
739
15c4dc5a 740
8f51ddb0
M
741static void Code4bitAnswerAsTag(uint8_t cmd)
742{
743 int i;
744
5f6d6c90 745 ToSendReset();
8f51ddb0
M
746
747 // Correction bit, might be removed when not needed
748 ToSendStuffBit(0);
749 ToSendStuffBit(0);
750 ToSendStuffBit(0);
751 ToSendStuffBit(0);
752 ToSendStuffBit(1); // 1
753 ToSendStuffBit(0);
754 ToSendStuffBit(0);
755 ToSendStuffBit(0);
756
757 // Send startbit
758 ToSend[++ToSendMax] = SEC_D;
759
760 uint8_t b = cmd;
761 for(i = 0; i < 4; i++) {
762 if(b & 1) {
763 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 764 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
765 } else {
766 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 767 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
768 }
769 b >>= 1;
770 }
771
772 // Send stopbit
773 ToSend[++ToSendMax] = SEC_F;
774
5f6d6c90 775 // Convert from last byte pos to length
776 ToSendMax++;
15c4dc5a 777}
778
779//-----------------------------------------------------------------------------
780// Wait for commands from reader
781// Stop when button is pressed
782// Or return TRUE when command is captured
783//-----------------------------------------------------------------------------
6a1f2d82 784static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
15c4dc5a 785{
786 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
787 // only, since we are receiving, not transmitting).
788 // Signal field is off with the appropriate LED
789 LED_D_OFF();
790 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
791
792 // Now run a `software UART' on the stream of incoming samples.
6a1f2d82 793 UartInit(received, parity);
7bc95e2e 794
795 // clear RXRDY:
796 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 797
798 for(;;) {
799 WDT_HIT();
800
801 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 802
15c4dc5a 803 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 804 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
805 if(MillerDecoding(b, 0)) {
806 *len = Uart.len;
15c4dc5a 807 return TRUE;
808 }
7bc95e2e 809 }
15c4dc5a 810 }
811}
28afbd2b 812
6a1f2d82 813static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
7bc95e2e 814int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
28afbd2b 815int EmSend4bit(uint8_t resp);
6a1f2d82 816int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
817int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
818int EmSendCmd(uint8_t *resp, uint16_t respLen);
819int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
820bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
821 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
15c4dc5a 822
117d9ec2 823static uint8_t* free_buffer_pointer;
ce02f6f9 824
825typedef struct {
826 uint8_t* response;
827 size_t response_n;
828 uint8_t* modulation;
829 size_t modulation_n;
7bc95e2e 830 uint32_t ProxToAirDuration;
ce02f6f9 831} tag_response_info_t;
832
ce02f6f9 833bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 834 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 835 // This will need the following byte array for a modulation sequence
836 // 144 data bits (18 * 8)
837 // 18 parity bits
838 // 2 Start and stop
839 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
840 // 1 just for the case
841 // ----------- +
842 // 166 bytes, since every bit that needs to be send costs us a byte
843 //
f71f4deb 844
845
ce02f6f9 846 // Prepare the tag modulation bits from the message
847 CodeIso14443aAsTag(response_info->response,response_info->response_n);
848
849 // Make sure we do not exceed the free buffer space
850 if (ToSendMax > max_buffer_size) {
851 Dbprintf("Out of memory, when modulating bits for tag answer:");
852 Dbhexdump(response_info->response_n,response_info->response,false);
853 return false;
854 }
855
856 // Copy the byte array, used for this modulation to the buffer position
857 memcpy(response_info->modulation,ToSend,ToSendMax);
858
7bc95e2e 859 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
ce02f6f9 860 response_info->modulation_n = ToSendMax;
7bc95e2e 861 response_info->ProxToAirDuration = LastProxToAirDuration;
ce02f6f9 862
863 return true;
864}
865
f71f4deb 866
867// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
868// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
869// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
870// -> need 273 bytes buffer
871#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
872
ce02f6f9 873bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
874 // Retrieve and store the current buffer index
875 response_info->modulation = free_buffer_pointer;
876
877 // Determine the maximum size we can use from our buffer
f71f4deb 878 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
ce02f6f9 879
880 // Forward the prepare tag modulation function to the inner function
f71f4deb 881 if (prepare_tag_modulation(response_info, max_buffer_size)) {
ce02f6f9 882 // Update the free buffer offset
883 free_buffer_pointer += ToSendMax;
884 return true;
885 } else {
886 return false;
887 }
888}
889
15c4dc5a 890//-----------------------------------------------------------------------------
891// Main loop of simulated tag: receive commands from reader, decide what
892// response to send, and send it.
893//-----------------------------------------------------------------------------
28afbd2b 894void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
15c4dc5a 895{
81cd0474 896 uint8_t sak;
897
898 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
899 uint8_t response1[2];
900
901 switch (tagType) {
902 case 1: { // MIFARE Classic
903 // Says: I am Mifare 1k - original line
904 response1[0] = 0x04;
905 response1[1] = 0x00;
906 sak = 0x08;
907 } break;
908 case 2: { // MIFARE Ultralight
909 // Says: I am a stupid memory tag, no crypto
910 response1[0] = 0x04;
911 response1[1] = 0x00;
912 sak = 0x00;
913 } break;
914 case 3: { // MIFARE DESFire
915 // Says: I am a DESFire tag, ph33r me
916 response1[0] = 0x04;
917 response1[1] = 0x03;
918 sak = 0x20;
919 } break;
920 case 4: { // ISO/IEC 14443-4
921 // Says: I am a javacard (JCOP)
922 response1[0] = 0x04;
923 response1[1] = 0x00;
924 sak = 0x28;
925 } break;
3fe4ff4f 926 case 5: { // MIFARE TNP3XXX
927 // Says: I am a toy
928 response1[0] = 0x01;
929 response1[1] = 0x0f;
930 sak = 0x01;
931 } break;
81cd0474 932 default: {
933 Dbprintf("Error: unkown tagtype (%d)",tagType);
934 return;
935 } break;
936 }
937
938 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 939 uint8_t response2[5] = {0x00};
81cd0474 940
941 // Check if the uid uses the (optional) part
c8b6da22 942 uint8_t response2a[5] = {0x00};
943
81cd0474 944 if (uid_2nd) {
945 response2[0] = 0x88;
946 num_to_bytes(uid_1st,3,response2+1);
947 num_to_bytes(uid_2nd,4,response2a);
948 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
949
950 // Configure the ATQA and SAK accordingly
951 response1[0] |= 0x40;
952 sak |= 0x04;
953 } else {
954 num_to_bytes(uid_1st,4,response2);
955 // Configure the ATQA and SAK accordingly
956 response1[0] &= 0xBF;
957 sak &= 0xFB;
958 }
959
960 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
961 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
962
963 // Prepare the mandatory SAK (for 4 and 7 byte UID)
c8b6da22 964 uint8_t response3[3] = {0x00};
81cd0474 965 response3[0] = sak;
966 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
967
968 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 969 uint8_t response3a[3] = {0x00};
81cd0474 970 response3a[0] = sak & 0xFB;
971 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
972
254b70a4 973 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
6a1f2d82 974 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
975 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
976 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
977 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
978 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 979 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
980
7bc95e2e 981 #define TAG_RESPONSE_COUNT 7
982 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
983 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
984 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
985 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
986 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
987 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
988 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
989 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
990 };
991
992 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
993 // Such a response is less time critical, so we can prepare them on the fly
994 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
995 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
996 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
997 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
998 tag_response_info_t dynamic_response_info = {
999 .response = dynamic_response_buffer,
1000 .response_n = 0,
1001 .modulation = dynamic_modulation_buffer,
1002 .modulation_n = 0
1003 };
ce02f6f9 1004
f71f4deb 1005 BigBuf_free_keep_EM();
1006
1007 // allocate buffers:
1008 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1009 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1010 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1011
1012 // clear trace
3000dc4e
MHS
1013 clear_trace();
1014 set_tracing(TRUE);
f71f4deb 1015
7bc95e2e 1016 // Prepare the responses of the anticollision phase
ce02f6f9 1017 // there will be not enough time to do this at the moment the reader sends it REQA
7bc95e2e 1018 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1019 prepare_allocated_tag_modulation(&responses[i]);
1020 }
15c4dc5a 1021
7bc95e2e 1022 int len = 0;
15c4dc5a 1023
1024 // To control where we are in the protocol
1025 int order = 0;
1026 int lastorder;
1027
1028 // Just to allow some checks
1029 int happened = 0;
1030 int happened2 = 0;
81cd0474 1031 int cmdsRecvd = 0;
15c4dc5a 1032
254b70a4 1033 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 1034 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
15c4dc5a 1035
254b70a4 1036 cmdsRecvd = 0;
7bc95e2e 1037 tag_response_info_t* p_response;
15c4dc5a 1038
254b70a4 1039 LED_A_ON();
1040 for(;;) {
7bc95e2e 1041 // Clean receive command buffer
1042
6a1f2d82 1043 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1044 DbpString("Button press");
254b70a4 1045 break;
1046 }
7bc95e2e 1047
1048 p_response = NULL;
1049
254b70a4 1050 // Okay, look at the command now.
1051 lastorder = order;
1052 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1053 p_response = &responses[0]; order = 1;
254b70a4 1054 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1055 p_response = &responses[0]; order = 6;
254b70a4 1056 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1057 p_response = &responses[1]; order = 2;
6a1f2d82 1058 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1059 p_response = &responses[2]; order = 20;
254b70a4 1060 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1061 p_response = &responses[3]; order = 3;
254b70a4 1062 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1063 p_response = &responses[4]; order = 30;
254b70a4 1064 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
6a1f2d82 1065 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
7bc95e2e 1066 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
5f6d6c90 1067 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
7bc95e2e 1068 p_response = NULL;
254b70a4 1069 } else if(receivedCmd[0] == 0x50) { // Received a HALT
3fe4ff4f 1070
7bc95e2e 1071 if (tracing) {
6a1f2d82 1072 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1073 }
1074 p_response = NULL;
254b70a4 1075 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
ce02f6f9 1076 p_response = &responses[5]; order = 7;
254b70a4 1077 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
7bc95e2e 1078 if (tagType == 1 || tagType == 2) { // RATS not supported
1079 EmSend4bit(CARD_NACK_NA);
1080 p_response = NULL;
1081 } else {
1082 p_response = &responses[6]; order = 70;
1083 }
6a1f2d82 1084 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
7bc95e2e 1085 if (tracing) {
6a1f2d82 1086 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1087 }
1088 uint32_t nr = bytes_to_num(receivedCmd,4);
1089 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1090 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1091 } else {
1092 // Check for ISO 14443A-4 compliant commands, look at left nibble
1093 switch (receivedCmd[0]) {
1094
1095 case 0x0B:
1096 case 0x0A: { // IBlock (command)
1097 dynamic_response_info.response[0] = receivedCmd[0];
1098 dynamic_response_info.response[1] = 0x00;
1099 dynamic_response_info.response[2] = 0x90;
1100 dynamic_response_info.response[3] = 0x00;
1101 dynamic_response_info.response_n = 4;
1102 } break;
1103
1104 case 0x1A:
1105 case 0x1B: { // Chaining command
1106 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1107 dynamic_response_info.response_n = 2;
1108 } break;
1109
1110 case 0xaa:
1111 case 0xbb: {
1112 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1113 dynamic_response_info.response_n = 2;
1114 } break;
1115
1116 case 0xBA: { //
1117 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1118 dynamic_response_info.response_n = 2;
1119 } break;
1120
1121 case 0xCA:
1122 case 0xC2: { // Readers sends deselect command
1123 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1124 dynamic_response_info.response_n = 2;
1125 } break;
1126
1127 default: {
1128 // Never seen this command before
1129 if (tracing) {
6a1f2d82 1130 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1131 }
1132 Dbprintf("Received unknown command (len=%d):",len);
1133 Dbhexdump(len,receivedCmd,false);
1134 // Do not respond
1135 dynamic_response_info.response_n = 0;
1136 } break;
1137 }
ce02f6f9 1138
7bc95e2e 1139 if (dynamic_response_info.response_n > 0) {
1140 // Copy the CID from the reader query
1141 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1142
7bc95e2e 1143 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1144 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1145 dynamic_response_info.response_n += 2;
ce02f6f9 1146
7bc95e2e 1147 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1148 Dbprintf("Error preparing tag response");
1149 if (tracing) {
6a1f2d82 1150 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1151 }
1152 break;
1153 }
1154 p_response = &dynamic_response_info;
1155 }
81cd0474 1156 }
15c4dc5a 1157
1158 // Count number of wakeups received after a halt
1159 if(order == 6 && lastorder == 5) { happened++; }
1160
1161 // Count number of other messages after a halt
1162 if(order != 6 && lastorder == 5) { happened2++; }
1163
15c4dc5a 1164 if(cmdsRecvd > 999) {
1165 DbpString("1000 commands later...");
254b70a4 1166 break;
15c4dc5a 1167 }
ce02f6f9 1168 cmdsRecvd++;
1169
1170 if (p_response != NULL) {
7bc95e2e 1171 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1172 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1173 uint8_t par[MAX_PARITY_SIZE];
1174 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1175
7bc95e2e 1176 EmLogTrace(Uart.output,
1177 Uart.len,
1178 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1179 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1180 Uart.parity,
7bc95e2e 1181 p_response->response,
1182 p_response->response_n,
1183 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1184 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1185 par);
7bc95e2e 1186 }
1187
1188 if (!tracing) {
1189 Dbprintf("Trace Full. Simulation stopped.");
1190 break;
1191 }
1192 }
15c4dc5a 1193
1194 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1195 LED_A_OFF();
f71f4deb 1196 BigBuf_free_keep_EM();
15c4dc5a 1197}
1198
9492e0b0 1199
1200// prepare a delayed transfer. This simply shifts ToSend[] by a number
1201// of bits specified in the delay parameter.
1202void PrepareDelayedTransfer(uint16_t delay)
1203{
1204 uint8_t bitmask = 0;
1205 uint8_t bits_to_shift = 0;
1206 uint8_t bits_shifted = 0;
1207
1208 delay &= 0x07;
1209 if (delay) {
1210 for (uint16_t i = 0; i < delay; i++) {
1211 bitmask |= (0x01 << i);
1212 }
7bc95e2e 1213 ToSend[ToSendMax++] = 0x00;
9492e0b0 1214 for (uint16_t i = 0; i < ToSendMax; i++) {
1215 bits_to_shift = ToSend[i] & bitmask;
1216 ToSend[i] = ToSend[i] >> delay;
1217 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1218 bits_shifted = bits_to_shift;
1219 }
1220 }
1221}
1222
7bc95e2e 1223
1224//-------------------------------------------------------------------------------------
15c4dc5a 1225// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1226// Parameter timing:
7bc95e2e 1227// if NULL: transfer at next possible time, taking into account
1228// request guard time and frame delay time
1229// if == 0: transfer immediately and return time of transfer
9492e0b0 1230// if != 0: delay transfer until time specified
7bc95e2e 1231//-------------------------------------------------------------------------------------
6a1f2d82 1232static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1233{
7bc95e2e 1234
9492e0b0 1235 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1236
7bc95e2e 1237 uint32_t ThisTransferTime = 0;
e30c654b 1238
9492e0b0 1239 if (timing) {
1240 if(*timing == 0) { // Measure time
7bc95e2e 1241 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
9492e0b0 1242 } else {
1243 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1244 }
7bc95e2e 1245 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1246 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1247 LastTimeProxToAirStart = *timing;
1248 } else {
1249 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1250 while(GetCountSspClk() < ThisTransferTime);
1251 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1252 }
1253
7bc95e2e 1254 // clear TXRDY
1255 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1256
7bc95e2e 1257 uint16_t c = 0;
9492e0b0 1258 for(;;) {
1259 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1260 AT91C_BASE_SSC->SSC_THR = cmd[c];
1261 c++;
1262 if(c >= len) {
1263 break;
1264 }
1265 }
1266 }
7bc95e2e 1267
1268 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1269}
1270
7bc95e2e 1271
15c4dc5a 1272//-----------------------------------------------------------------------------
195af472 1273// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1274//-----------------------------------------------------------------------------
6a1f2d82 1275void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1276{
7bc95e2e 1277 int i, j;
1278 int last;
1279 uint8_t b;
e30c654b 1280
7bc95e2e 1281 ToSendReset();
e30c654b 1282
7bc95e2e 1283 // Start of Communication (Seq. Z)
1284 ToSend[++ToSendMax] = SEC_Z;
1285 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1286 last = 0;
1287
1288 size_t bytecount = nbytes(bits);
1289 // Generate send structure for the data bits
1290 for (i = 0; i < bytecount; i++) {
1291 // Get the current byte to send
1292 b = cmd[i];
1293 size_t bitsleft = MIN((bits-(i*8)),8);
1294
1295 for (j = 0; j < bitsleft; j++) {
1296 if (b & 1) {
1297 // Sequence X
1298 ToSend[++ToSendMax] = SEC_X;
1299 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1300 last = 1;
1301 } else {
1302 if (last == 0) {
1303 // Sequence Z
1304 ToSend[++ToSendMax] = SEC_Z;
1305 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1306 } else {
1307 // Sequence Y
1308 ToSend[++ToSendMax] = SEC_Y;
1309 last = 0;
1310 }
1311 }
1312 b >>= 1;
1313 }
1314
6a1f2d82 1315 // Only transmit parity bit if we transmitted a complete byte
7bc95e2e 1316 if (j == 8) {
1317 // Get the parity bit
6a1f2d82 1318 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1319 // Sequence X
1320 ToSend[++ToSendMax] = SEC_X;
1321 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1322 last = 1;
1323 } else {
1324 if (last == 0) {
1325 // Sequence Z
1326 ToSend[++ToSendMax] = SEC_Z;
1327 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1328 } else {
1329 // Sequence Y
1330 ToSend[++ToSendMax] = SEC_Y;
1331 last = 0;
1332 }
1333 }
1334 }
1335 }
e30c654b 1336
7bc95e2e 1337 // End of Communication: Logic 0 followed by Sequence Y
1338 if (last == 0) {
1339 // Sequence Z
1340 ToSend[++ToSendMax] = SEC_Z;
1341 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1342 } else {
1343 // Sequence Y
1344 ToSend[++ToSendMax] = SEC_Y;
1345 last = 0;
1346 }
1347 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1348
7bc95e2e 1349 // Convert to length of command:
1350 ToSendMax++;
15c4dc5a 1351}
1352
195af472 1353//-----------------------------------------------------------------------------
1354// Prepare reader command to send to FPGA
1355//-----------------------------------------------------------------------------
6a1f2d82 1356void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
195af472 1357{
6a1f2d82 1358 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1359}
1360
0c8d25eb 1361
9ca155ba
M
1362//-----------------------------------------------------------------------------
1363// Wait for commands from reader
1364// Stop when button is pressed (return 1) or field was gone (return 2)
1365// Or return 0 when command is captured
1366//-----------------------------------------------------------------------------
6a1f2d82 1367static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
9ca155ba
M
1368{
1369 *len = 0;
1370
1371 uint32_t timer = 0, vtime = 0;
1372 int analogCnt = 0;
1373 int analogAVG = 0;
1374
1375 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1376 // only, since we are receiving, not transmitting).
1377 // Signal field is off with the appropriate LED
1378 LED_D_OFF();
1379 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1380
1381 // Set ADC to read field strength
1382 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1383 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1384 ADC_MODE_PRESCALE(63) |
1385 ADC_MODE_STARTUP_TIME(1) |
1386 ADC_MODE_SAMPLE_HOLD_TIME(15);
9ca155ba
M
1387 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1388 // start ADC
1389 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1390
1391 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1392 UartInit(received, parity);
7bc95e2e 1393
1394 // Clear RXRDY:
1395 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1396
9ca155ba
M
1397 for(;;) {
1398 WDT_HIT();
1399
1400 if (BUTTON_PRESS()) return 1;
1401
1402 // test if the field exists
1403 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1404 analogCnt++;
1405 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1406 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1407 if (analogCnt >= 32) {
0c8d25eb 1408 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
9ca155ba
M
1409 vtime = GetTickCount();
1410 if (!timer) timer = vtime;
1411 // 50ms no field --> card to idle state
1412 if (vtime - timer > 50) return 2;
1413 } else
1414 if (timer) timer = 0;
1415 analogCnt = 0;
1416 analogAVG = 0;
1417 }
1418 }
7bc95e2e 1419
9ca155ba 1420 // receive and test the miller decoding
7bc95e2e 1421 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1422 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1423 if(MillerDecoding(b, 0)) {
1424 *len = Uart.len;
9ca155ba
M
1425 return 0;
1426 }
7bc95e2e 1427 }
1428
9ca155ba
M
1429 }
1430}
1431
9ca155ba 1432
6a1f2d82 1433static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
7bc95e2e 1434{
1435 uint8_t b;
1436 uint16_t i = 0;
1437 uint32_t ThisTransferTime;
1438
9ca155ba
M
1439 // Modulate Manchester
1440 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1441
1442 // include correction bit if necessary
1443 if (Uart.parityBits & 0x01) {
1444 correctionNeeded = TRUE;
1445 }
1446 if(correctionNeeded) {
9ca155ba
M
1447 // 1236, so correction bit needed
1448 i = 0;
7bc95e2e 1449 } else {
1450 i = 1;
9ca155ba 1451 }
7bc95e2e 1452
d714d3ef 1453 // clear receiving shift register and holding register
7bc95e2e 1454 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1455 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1456 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1457 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1458
7bc95e2e 1459 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1460 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1461 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1462 if (AT91C_BASE_SSC->SSC_RHR) break;
1463 }
1464
1465 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1466
1467 // Clear TXRDY:
1468 AT91C_BASE_SSC->SSC_THR = SEC_F;
1469
9ca155ba 1470 // send cycle
bb42a03e 1471 for(; i < respLen; ) {
9ca155ba 1472 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1473 AT91C_BASE_SSC->SSC_THR = resp[i++];
1474 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1475 }
7bc95e2e 1476
9ca155ba
M
1477 if(BUTTON_PRESS()) {
1478 break;
1479 }
1480 }
1481
7bc95e2e 1482 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
0c8d25eb 1483 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1484 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
7bc95e2e 1485 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1486 AT91C_BASE_SSC->SSC_THR = SEC_F;
1487 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1488 i++;
1489 }
1490 }
0c8d25eb 1491
7bc95e2e 1492 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1493
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1494 return 0;
1495}
1496
7bc95e2e 1497int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1498 Code4bitAnswerAsTag(resp);
0a39986e 1499 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1500 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1501 uint8_t par[1];
1502 GetParity(&resp, 1, par);
7bc95e2e 1503 EmLogTrace(Uart.output,
1504 Uart.len,
1505 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1506 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1507 Uart.parity,
7bc95e2e 1508 &resp,
1509 1,
1510 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1511 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1512 par);
0a39986e 1513 return res;
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M
1514}
1515
8f51ddb0 1516int EmSend4bit(uint8_t resp){
7bc95e2e 1517 return EmSend4bitEx(resp, false);
8f51ddb0
M
1518}
1519
6a1f2d82 1520int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1521 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1522 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1523 // do the tracing for the previous reader request and this tag answer:
1524 EmLogTrace(Uart.output,
1525 Uart.len,
1526 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1527 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1528 Uart.parity,
7bc95e2e 1529 resp,
1530 respLen,
1531 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1532 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1533 par);
8f51ddb0
M
1534 return res;
1535}
1536
6a1f2d82 1537int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1538 uint8_t par[MAX_PARITY_SIZE];
1539 GetParity(resp, respLen, par);
1540 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
8f51ddb0
M
1541}
1542
6a1f2d82 1543int EmSendCmd(uint8_t *resp, uint16_t respLen){
1544 uint8_t par[MAX_PARITY_SIZE];
1545 GetParity(resp, respLen, par);
1546 return EmSendCmdExPar(resp, respLen, false, par);
8f51ddb0
M
1547}
1548
6a1f2d82 1549int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1550 return EmSendCmdExPar(resp, respLen, false, par);
1551}
1552
6a1f2d82 1553bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1554 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1555{
1556 if (tracing) {
1557 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1558 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1559 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1560 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1561 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1562 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1563 reader_EndTime = tag_StartTime - exact_fdt;
1564 reader_StartTime = reader_EndTime - reader_modlen;
6a1f2d82 1565 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
7bc95e2e 1566 return FALSE;
6a1f2d82 1567 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
7bc95e2e 1568 } else {
1569 return TRUE;
1570 }
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1571}
1572
15c4dc5a 1573//-----------------------------------------------------------------------------
1574// Wait a certain time for tag response
1575// If a response is captured return TRUE
e691fc45 1576// If it takes too long return FALSE
15c4dc5a 1577//-----------------------------------------------------------------------------
6a1f2d82 1578static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1579{
52bfb955 1580 uint32_t c;
e691fc45 1581
15c4dc5a 1582 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1583 // only, since we are receiving, not transmitting).
1584 // Signal field is on with the appropriate LED
1585 LED_D_ON();
1586 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1587
534983d7 1588 // Now get the answer from the card
6a1f2d82 1589 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1590
7bc95e2e 1591 // clear RXRDY:
1592 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1593
15c4dc5a 1594 c = 0;
1595 for(;;) {
534983d7 1596 WDT_HIT();
15c4dc5a 1597
534983d7 1598 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1599 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1600 if(ManchesterDecoding(b, offset, 0)) {
1601 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1602 return TRUE;
6a1f2d82 1603 } else if (c++ > iso14a_timeout) {
7bc95e2e 1604 return FALSE;
15c4dc5a 1605 }
534983d7 1606 }
1607 }
15c4dc5a 1608}
1609
6a1f2d82 1610void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1611{
6a1f2d82 1612 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1613
7bc95e2e 1614 // Send command to tag
1615 TransmitFor14443a(ToSend, ToSendMax, timing);
1616 if(trigger)
1617 LED_A_ON();
dfc3c505 1618
7bc95e2e 1619 // Log reader command in trace buffer
1620 if (tracing) {
6a1f2d82 1621 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
7bc95e2e 1622 }
15c4dc5a 1623}
1624
6a1f2d82 1625void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1626{
6a1f2d82 1627 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1628}
15c4dc5a 1629
6a1f2d82 1630void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1631{
1632 // Generate parity and redirect
6a1f2d82 1633 uint8_t par[MAX_PARITY_SIZE];
1634 GetParity(frame, len/8, par);
1635 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1636}
1637
6a1f2d82 1638void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1639{
1640 // Generate parity and redirect
6a1f2d82 1641 uint8_t par[MAX_PARITY_SIZE];
1642 GetParity(frame, len, par);
1643 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1644}
1645
6a1f2d82 1646int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1647{
6a1f2d82 1648 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
7bc95e2e 1649 if (tracing) {
6a1f2d82 1650 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1651 }
e691fc45 1652 return Demod.len;
1653}
1654
6a1f2d82 1655int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
15c4dc5a 1656{
6a1f2d82 1657 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
7bc95e2e 1658 if (tracing) {
6a1f2d82 1659 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1660 }
e691fc45 1661 return Demod.len;
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1662}
1663
e691fc45 1664/* performs iso14443a anticollision procedure
534983d7 1665 * fills the uid pointer unless NULL
1666 * fills resp_data unless NULL */
6a1f2d82 1667int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1668 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1669 uint8_t sel_all[] = { 0x93,0x20 };
1670 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1671 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
f71f4deb 1672 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1673 uint8_t resp_par[MAX_PARITY_SIZE];
6a1f2d82 1674 byte_t uid_resp[4];
1675 size_t uid_resp_len;
1676
1677 uint8_t sak = 0x04; // cascade uid
1678 int cascade_level = 0;
1679 int len;
1680
1681 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
9492e0b0 1682 ReaderTransmitBitsPar(wupa,7,0, NULL);
7bc95e2e 1683
6a1f2d82 1684 // Receive the ATQA
1685 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1686
1687 if(p_hi14a_card) {
1688 memcpy(p_hi14a_card->atqa, resp, 2);
1689 p_hi14a_card->uidlen = 0;
1690 memset(p_hi14a_card->uid,0,10);
1691 }
5f6d6c90 1692
6a1f2d82 1693 // clear uid
1694 if (uid_ptr) {
1695 memset(uid_ptr,0,10);
1696 }
79a73ab2 1697
6a1f2d82 1698 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1699 // which case we need to make a cascade 2 request and select - this is a long UID
1700 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1701 for(; sak & 0x04; cascade_level++) {
1702 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1703 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1704
1705 // SELECT_ALL
1706 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1707 if (!ReaderReceive(resp, resp_par)) return 0;
1708
1709 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1710 memset(uid_resp, 0, 4);
1711 uint16_t uid_resp_bits = 0;
1712 uint16_t collision_answer_offset = 0;
1713 // anti-collision-loop:
1714 while (Demod.collisionPos) {
1715 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1716 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1717 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
758f1fd1 1718 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1719 }
1720 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1721 uid_resp_bits++;
1722 // construct anticollosion command:
1723 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1724 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1725 sel_uid[2+i] = uid_resp[i];
1726 }
1727 collision_answer_offset = uid_resp_bits%8;
1728 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1729 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
e691fc45 1730 }
6a1f2d82 1731 // finally, add the last bits and BCC of the UID
1732 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1733 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1734 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
e691fc45 1735 }
e691fc45 1736
6a1f2d82 1737 } else { // no collision, use the response to SELECT_ALL as current uid
1738 memcpy(uid_resp, resp, 4);
1739 }
1740 uid_resp_len = 4;
5f6d6c90 1741
6a1f2d82 1742 // calculate crypto UID. Always use last 4 Bytes.
1743 if(cuid_ptr) {
1744 *cuid_ptr = bytes_to_num(uid_resp, 4);
1745 }
e30c654b 1746
6a1f2d82 1747 // Construct SELECT UID command
1748 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1749 memcpy(sel_uid+2, uid_resp, 4); // the UID
1750 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1751 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1752 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1753
1754 // Receive the SAK
1755 if (!ReaderReceive(resp, resp_par)) return 0;
1756 sak = resp[0];
1757
52ab55ab 1758 // Test if more parts of the uid are coming
6a1f2d82 1759 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1760 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1761 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1762 uid_resp[0] = uid_resp[1];
1763 uid_resp[1] = uid_resp[2];
1764 uid_resp[2] = uid_resp[3];
1765
1766 uid_resp_len = 3;
1767 }
5f6d6c90 1768
6a1f2d82 1769 if(uid_ptr) {
1770 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1771 }
5f6d6c90 1772
6a1f2d82 1773 if(p_hi14a_card) {
1774 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1775 p_hi14a_card->uidlen += uid_resp_len;
1776 }
1777 }
79a73ab2 1778
6a1f2d82 1779 if(p_hi14a_card) {
1780 p_hi14a_card->sak = sak;
1781 p_hi14a_card->ats_len = 0;
1782 }
534983d7 1783
3fe4ff4f 1784 // non iso14443a compliant tag
1785 if( (sak & 0x20) == 0) return 2;
534983d7 1786
6a1f2d82 1787 // Request for answer to select
1788 AppendCrc14443a(rats, 2);
1789 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1790
6a1f2d82 1791 if (!(len = ReaderReceive(resp, resp_par))) return 0;
5191b3d1 1792
3fe4ff4f 1793
6a1f2d82 1794 if(p_hi14a_card) {
1795 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1796 p_hi14a_card->ats_len = len;
1797 }
5f6d6c90 1798
6a1f2d82 1799 // reset the PCB block number
1800 iso14_pcb_blocknum = 0;
6a1f2d82 1801 return 1;
7e758047 1802}
15c4dc5a 1803
7bc95e2e 1804void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1805 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1806 // Set up the synchronous serial port
1807 FpgaSetupSsc();
7bc95e2e 1808 // connect Demodulated Signal to ADC:
7e758047 1809 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
e30c654b 1810
7e758047 1811 // Signal field is on with the appropriate LED
7bc95e2e 1812 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1813 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1814 LED_D_ON();
1815 } else {
1816 LED_D_OFF();
1817 }
1818 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
534983d7 1819
7bc95e2e 1820 // Start the timer
1821 StartCountSspClk();
1822
1823 DemodReset();
1824 UartReset();
1825 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1826 iso14a_set_timeout(1050); // 10ms default
7e758047 1827}
15c4dc5a 1828
6a1f2d82 1829int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1830 uint8_t parity[MAX_PARITY_SIZE];
534983d7 1831 uint8_t real_cmd[cmd_len+4];
1832 real_cmd[0] = 0x0a; //I-Block
b0127e65 1833 // put block number into the PCB
1834 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 1835 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1836 memcpy(real_cmd+2, cmd, cmd_len);
1837 AppendCrc14443a(real_cmd,cmd_len+2);
1838
9492e0b0 1839 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 1840 size_t len = ReaderReceive(data, parity);
1841 uint8_t *data_bytes = (uint8_t *) data;
b0127e65 1842 if (!len)
1843 return 0; //DATA LINK ERROR
1844 // if we received an I- or R(ACK)-Block with a block number equal to the
1845 // current block number, toggle the current block number
1846 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1847 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1848 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1849 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1850 {
1851 iso14_pcb_blocknum ^= 1;
1852 }
1853
534983d7 1854 return len;
1855}
1856
7e758047 1857//-----------------------------------------------------------------------------
1858// Read an ISO 14443a tag. Send out commands and store answers.
1859//
1860//-----------------------------------------------------------------------------
7bc95e2e 1861void ReaderIso14443a(UsbCommand *c)
7e758047 1862{
534983d7 1863 iso14a_command_t param = c->arg[0];
7bc95e2e 1864 uint8_t *cmd = c->d.asBytes;
534983d7 1865 size_t len = c->arg[1];
5f6d6c90 1866 size_t lenbits = c->arg[2];
9492e0b0 1867 uint32_t arg0 = 0;
1868 byte_t buf[USB_CMD_DATA_SIZE];
6a1f2d82 1869 uint8_t par[MAX_PARITY_SIZE];
902cb3c0 1870
5f6d6c90 1871 if(param & ISO14A_CONNECT) {
3000dc4e 1872 clear_trace();
5f6d6c90 1873 }
e691fc45 1874
3000dc4e 1875 set_tracing(TRUE);
e30c654b 1876
79a73ab2 1877 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1878 iso14a_set_trigger(TRUE);
9492e0b0 1879 }
15c4dc5a 1880
534983d7 1881 if(param & ISO14A_CONNECT) {
7bc95e2e 1882 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 1883 if(!(param & ISO14A_NO_SELECT)) {
1884 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1885 arg0 = iso14443a_select_card(NULL,card,NULL);
1886 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1887 }
534983d7 1888 }
e30c654b 1889
534983d7 1890 if(param & ISO14A_SET_TIMEOUT) {
3fe4ff4f 1891 iso14a_set_timeout(c->arg[2]);
534983d7 1892 }
e30c654b 1893
534983d7 1894 if(param & ISO14A_APDU) {
902cb3c0 1895 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 1896 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1897 }
e30c654b 1898
534983d7 1899 if(param & ISO14A_RAW) {
1900 if(param & ISO14A_APPEND_CRC) {
1901 AppendCrc14443a(cmd,len);
1902 len += 2;
c7324bef 1903 if (lenbits) lenbits += 16;
15c4dc5a 1904 }
5f6d6c90 1905 if(lenbits>0) {
6a1f2d82 1906 GetParity(cmd, lenbits/8, par);
1907 ReaderTransmitBitsPar(cmd, lenbits, par, NULL);
5f6d6c90 1908 } else {
1909 ReaderTransmit(cmd,len, NULL);
1910 }
6a1f2d82 1911 arg0 = ReaderReceive(buf, par);
9492e0b0 1912 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1913 }
15c4dc5a 1914
79a73ab2 1915 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1916 iso14a_set_trigger(FALSE);
9492e0b0 1917 }
15c4dc5a 1918
79a73ab2 1919 if(param & ISO14A_NO_DISCONNECT) {
534983d7 1920 return;
9492e0b0 1921 }
15c4dc5a 1922
15c4dc5a 1923 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1924 LEDsoff();
15c4dc5a 1925}
b0127e65 1926
1c611bbd 1927
1c611bbd 1928// Determine the distance between two nonces.
1929// Assume that the difference is small, but we don't know which is first.
1930// Therefore try in alternating directions.
1931int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1932
1933 uint16_t i;
1934 uint32_t nttmp1, nttmp2;
e772353f 1935
1c611bbd 1936 if (nt1 == nt2) return 0;
1937
1938 nttmp1 = nt1;
1939 nttmp2 = nt2;
1940
1941 for (i = 1; i < 32768; i++) {
1942 nttmp1 = prng_successor(nttmp1, 1);
1943 if (nttmp1 == nt2) return i;
1944 nttmp2 = prng_successor(nttmp2, 1);
1945 if (nttmp2 == nt1) return -i;
1946 }
1947
1948 return(-99999); // either nt1 or nt2 are invalid nonces
e772353f 1949}
1950
e772353f 1951
1c611bbd 1952//-----------------------------------------------------------------------------
1953// Recover several bits of the cypher stream. This implements (first stages of)
1954// the algorithm described in "The Dark Side of Security by Obscurity and
1955// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
1956// (article by Nicolas T. Courtois, 2009)
1957//-----------------------------------------------------------------------------
1958void ReaderMifare(bool first_try)
1959{
1960 // Mifare AUTH
1961 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
1962 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
1963 static uint8_t mf_nr_ar3;
e772353f 1964
f71f4deb 1965 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
1966 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
7bc95e2e 1967
f71f4deb 1968 // free eventually allocated BigBuf memory. We want all for tracing.
1969 BigBuf_free();
1970
3000dc4e
MHS
1971 clear_trace();
1972 set_tracing(TRUE);
e772353f 1973
1c611bbd 1974 byte_t nt_diff = 0;
6a1f2d82 1975 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 1976 static byte_t par_low = 0;
1977 bool led_on = TRUE;
ca4714cd 1978 uint8_t uid[10] ={0};
1c611bbd 1979 uint32_t cuid;
e772353f 1980
6a1f2d82 1981 uint32_t nt = 0;
2ed270a8 1982 uint32_t previous_nt = 0;
1c611bbd 1983 static uint32_t nt_attacked = 0;
3fe4ff4f 1984 byte_t par_list[8] = {0x00};
1985 byte_t ks_list[8] = {0x00};
e772353f 1986
1c611bbd 1987 static uint32_t sync_time;
1988 static uint32_t sync_cycles;
1989 int catch_up_cycles = 0;
1990 int last_catch_up = 0;
1991 uint16_t consecutive_resyncs = 0;
1992 int isOK = 0;
e772353f 1993
1c611bbd 1994 if (first_try) {
1c611bbd 1995 mf_nr_ar3 = 0;
7bc95e2e 1996 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
1997 sync_time = GetCountSspClk() & 0xfffffff8;
1c611bbd 1998 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
1999 nt_attacked = 0;
2000 nt = 0;
6a1f2d82 2001 par[0] = 0;
1c611bbd 2002 }
2003 else {
2004 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1c611bbd 2005 mf_nr_ar3++;
2006 mf_nr_ar[3] = mf_nr_ar3;
6a1f2d82 2007 par[0] = par_low;
1c611bbd 2008 }
e30c654b 2009
15c4dc5a 2010 LED_A_ON();
2011 LED_B_OFF();
2012 LED_C_OFF();
1c611bbd 2013
7bc95e2e 2014
1c611bbd 2015 for(uint16_t i = 0; TRUE; i++) {
2016
2017 WDT_HIT();
e30c654b 2018
1c611bbd 2019 // Test if the action was cancelled
2020 if(BUTTON_PRESS()) {
2021 break;
2022 }
2023
2024 LED_C_ON();
e30c654b 2025
1c611bbd 2026 if(!iso14443a_select_card(uid, NULL, &cuid)) {
9492e0b0 2027 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1c611bbd 2028 continue;
2029 }
2030
9492e0b0 2031 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
1c611bbd 2032 catch_up_cycles = 0;
2033
2034 // if we missed the sync time already, advance to the next nonce repeat
7bc95e2e 2035 while(GetCountSspClk() > sync_time) {
9492e0b0 2036 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
1c611bbd 2037 }
e30c654b 2038
9492e0b0 2039 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2040 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2041
1c611bbd 2042 // Receive the (4 Byte) "random" nonce
6a1f2d82 2043 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2044 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
1c611bbd 2045 continue;
2046 }
2047
1c611bbd 2048 previous_nt = nt;
2049 nt = bytes_to_num(receivedAnswer, 4);
2050
2051 // Transmit reader nonce with fake par
9492e0b0 2052 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
1c611bbd 2053
2054 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2055 int nt_distance = dist_nt(previous_nt, nt);
2056 if (nt_distance == 0) {
2057 nt_attacked = nt;
2058 }
2059 else {
2060 if (nt_distance == -99999) { // invalid nonce received, try again
2061 continue;
2062 }
2063 sync_cycles = (sync_cycles - nt_distance);
9492e0b0 2064 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
1c611bbd 2065 continue;
2066 }
2067 }
2068
2069 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2070 catch_up_cycles = -dist_nt(nt_attacked, nt);
2071 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2072 catch_up_cycles = 0;
2073 continue;
2074 }
2075 if (catch_up_cycles == last_catch_up) {
2076 consecutive_resyncs++;
2077 }
2078 else {
2079 last_catch_up = catch_up_cycles;
2080 consecutive_resyncs = 0;
2081 }
2082 if (consecutive_resyncs < 3) {
9492e0b0 2083 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
1c611bbd 2084 }
2085 else {
2086 sync_cycles = sync_cycles + catch_up_cycles;
9492e0b0 2087 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
1c611bbd 2088 }
2089 continue;
2090 }
2091
2092 consecutive_resyncs = 0;
2093
2094 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
6a1f2d82 2095 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2096 {
9492e0b0 2097 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2098
2099 if (nt_diff == 0)
2100 {
6a1f2d82 2101 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2102 }
2103
2104 led_on = !led_on;
2105 if(led_on) LED_B_ON(); else LED_B_OFF();
2106
6a1f2d82 2107 par_list[nt_diff] = SwapBits(par[0], 8);
1c611bbd 2108 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2109
2110 // Test if the information is complete
2111 if (nt_diff == 0x07) {
2112 isOK = 1;
2113 break;
2114 }
2115
2116 nt_diff = (nt_diff + 1) & 0x07;
2117 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2118 par[0] = par_low;
1c611bbd 2119 } else {
2120 if (nt_diff == 0 && first_try)
2121 {
6a1f2d82 2122 par[0]++;
1c611bbd 2123 } else {
6a1f2d82 2124 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2125 }
2126 }
2127 }
2128
1c611bbd 2129
2130 mf_nr_ar[3] &= 0x1F;
2131
2132 byte_t buf[28];
2133 memcpy(buf + 0, uid, 4);
2134 num_to_bytes(nt, 4, buf + 4);
2135 memcpy(buf + 8, par_list, 8);
2136 memcpy(buf + 16, ks_list, 8);
2137 memcpy(buf + 24, mf_nr_ar, 4);
2138
2139 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2140
2141 // Thats it...
2142 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2143 LEDsoff();
7bc95e2e 2144
3000dc4e 2145 set_tracing(FALSE);
20f9a2a1 2146}
1c611bbd 2147
d2f487af 2148/**
2149 *MIFARE 1K simulate.
2150 *
2151 *@param flags :
2152 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2153 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2154 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2155 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2156 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2157 */
2158void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
20f9a2a1 2159{
50193c1e 2160 int cardSTATE = MFEMUL_NOFIELD;
8556b852 2161 int _7BUID = 0;
9ca155ba 2162 int vHf = 0; // in mV
8f51ddb0 2163 int res;
0a39986e
M
2164 uint32_t selTimer = 0;
2165 uint32_t authTimer = 0;
6a1f2d82 2166 uint16_t len = 0;
8f51ddb0 2167 uint8_t cardWRBL = 0;
9ca155ba
M
2168 uint8_t cardAUTHSC = 0;
2169 uint8_t cardAUTHKEY = 0xff; // no authentication
51969283 2170 uint32_t cardRr = 0;
9ca155ba 2171 uint32_t cuid = 0;
d2f487af 2172 //uint32_t rn_enc = 0;
51969283 2173 uint32_t ans = 0;
0014cb46
M
2174 uint32_t cardINTREG = 0;
2175 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2176 struct Crypto1State mpcs = {0, 0};
2177 struct Crypto1State *pcs;
2178 pcs = &mpcs;
d2f487af 2179 uint32_t numReads = 0;//Counts numer of times reader read a block
f71f4deb 2180 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2181 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2182 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2183 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
9ca155ba 2184
d2f487af 2185 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2186 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2187 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2188 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2189 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
9ca155ba 2190
d2f487af 2191 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2192 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
7bc95e2e 2193
d2f487af 2194 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2195 // This can be used in a reader-only attack.
2196 // (it can also be retrieved via 'hf 14a list', but hey...
2197 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2198 uint8_t ar_nr_collected = 0;
0014cb46 2199
f71f4deb 2200 // free eventually allocated BigBuf memory but keep Emulator Memory
2201 BigBuf_free_keep_EM();
0c8d25eb 2202
0a39986e 2203 // clear trace
3000dc4e
MHS
2204 clear_trace();
2205 set_tracing(TRUE);
51969283 2206
7bc95e2e 2207 // Authenticate response - nonce
51969283 2208 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
7bc95e2e 2209
d2f487af 2210 //-- Determine the UID
2211 // Can be set from emulator memory, incoming data
2212 // and can be 7 or 4 bytes long
7bc95e2e 2213 if (flags & FLAG_4B_UID_IN_DATA)
d2f487af 2214 {
2215 // 4B uid comes from data-portion of packet
2216 memcpy(rUIDBCC1,datain,4);
8556b852 2217 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
8556b852 2218
7bc95e2e 2219 } else if (flags & FLAG_7B_UID_IN_DATA) {
d2f487af 2220 // 7B uid comes from data-portion of packet
2221 memcpy(&rUIDBCC1[1],datain,3);
2222 memcpy(rUIDBCC2, datain+3, 4);
2223 _7BUID = true;
7bc95e2e 2224 } else {
d2f487af 2225 // get UID from emul memory
2226 emlGetMemBt(receivedCmd, 7, 1);
2227 _7BUID = !(receivedCmd[0] == 0x00);
2228 if (!_7BUID) { // ---------- 4BUID
2229 emlGetMemBt(rUIDBCC1, 0, 4);
2230 } else { // ---------- 7BUID
2231 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2232 emlGetMemBt(rUIDBCC2, 3, 4);
2233 }
2234 }
7bc95e2e 2235
d2f487af 2236 /*
2237 * Regardless of what method was used to set the UID, set fifth byte and modify
2238 * the ATQA for 4 or 7-byte UID
2239 */
d2f487af 2240 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
7bc95e2e 2241 if (_7BUID) {
d2f487af 2242 rATQA[0] = 0x44;
8556b852 2243 rUIDBCC1[0] = 0x88;
8556b852
M
2244 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2245 }
2246
9ca155ba 2247 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 2248 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
9ca155ba 2249
9ca155ba 2250
d2f487af 2251 if (MF_DBGLEVEL >= 1) {
2252 if (!_7BUID) {
b03c0f2d 2253 Dbprintf("4B UID: %02x%02x%02x%02x",
2254 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
7bc95e2e 2255 } else {
b03c0f2d 2256 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2257 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2258 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
d2f487af 2259 }
2260 }
7bc95e2e 2261
2262 bool finished = FALSE;
d2f487af 2263 while (!BUTTON_PRESS() && !finished) {
9ca155ba 2264 WDT_HIT();
9ca155ba
M
2265
2266 // find reader field
9ca155ba 2267 if (cardSTATE == MFEMUL_NOFIELD) {
0c8d25eb 2268 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
9ca155ba 2269 if (vHf > MF_MINFIELDV) {
0014cb46 2270 cardSTATE_TO_IDLE();
9ca155ba
M
2271 LED_A_ON();
2272 }
2273 }
d2f487af 2274 if(cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2275
d2f487af 2276 //Now, get data
2277
6a1f2d82 2278 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2279 if (res == 2) { //Field is off!
2280 cardSTATE = MFEMUL_NOFIELD;
2281 LEDsoff();
2282 continue;
7bc95e2e 2283 } else if (res == 1) {
2284 break; //return value 1 means button press
2285 }
2286
d2f487af 2287 // REQ or WUP request in ANY state and WUP in HALTED state
2288 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2289 selTimer = GetTickCount();
2290 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2291 cardSTATE = MFEMUL_SELECT1;
2292
2293 // init crypto block
2294 LED_B_OFF();
2295 LED_C_OFF();
2296 crypto1_destroy(pcs);
2297 cardAUTHKEY = 0xff;
2298 continue;
0a39986e 2299 }
7bc95e2e 2300
50193c1e 2301 switch (cardSTATE) {
d2f487af 2302 case MFEMUL_NOFIELD:
2303 case MFEMUL_HALTED:
50193c1e 2304 case MFEMUL_IDLE:{
6a1f2d82 2305 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2306 break;
2307 }
2308 case MFEMUL_SELECT1:{
9ca155ba
M
2309 // select all
2310 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
d2f487af 2311 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2312 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2313 break;
9ca155ba
M
2314 }
2315
d2f487af 2316 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2317 {
2318 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2319 }
9ca155ba 2320 // select card
0a39986e
M
2321 if (len == 9 &&
2322 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
bfb6a143 2323 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
9ca155ba 2324 cuid = bytes_to_num(rUIDBCC1, 4);
8556b852
M
2325 if (!_7BUID) {
2326 cardSTATE = MFEMUL_WORK;
0014cb46
M
2327 LED_B_ON();
2328 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2329 break;
8556b852
M
2330 } else {
2331 cardSTATE = MFEMUL_SELECT2;
8556b852 2332 }
9ca155ba 2333 }
50193c1e
M
2334 break;
2335 }
d2f487af 2336 case MFEMUL_AUTH1:{
2337 if( len != 8)
2338 {
2339 cardSTATE_TO_IDLE();
6a1f2d82 2340 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2341 break;
2342 }
0c8d25eb 2343
d2f487af 2344 uint32_t ar = bytes_to_num(receivedCmd, 4);
6a1f2d82 2345 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2346
2347 //Collect AR/NR
2348 if(ar_nr_collected < 2){
273b57a7 2349 if(ar_nr_responses[2] != ar)
2350 {// Avoid duplicates... probably not necessary, ar should vary.
d2f487af 2351 ar_nr_responses[ar_nr_collected*4] = cuid;
2352 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2353 ar_nr_responses[ar_nr_collected*4+2] = ar;
2354 ar_nr_responses[ar_nr_collected*4+3] = nr;
273b57a7 2355 ar_nr_collected++;
d2f487af 2356 }
2357 }
2358
2359 // --- crypto
2360 crypto1_word(pcs, ar , 1);
2361 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2362
2363 // test if auth OK
2364 if (cardRr != prng_successor(nonce, 64)){
b03c0f2d 2365 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2366 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2367 cardRr, prng_successor(nonce, 64));
7bc95e2e 2368 // Shouldn't we respond anything here?
d2f487af 2369 // Right now, we don't nack or anything, which causes the
2370 // reader to do a WUPA after a while. /Martin
b03c0f2d 2371 // -- which is the correct response. /piwi
d2f487af 2372 cardSTATE_TO_IDLE();
6a1f2d82 2373 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2374 break;
2375 }
2376
2377 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2378
2379 num_to_bytes(ans, 4, rAUTH_AT);
2380 // --- crypto
2381 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2382 LED_C_ON();
2383 cardSTATE = MFEMUL_WORK;
b03c0f2d 2384 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2385 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2386 GetTickCount() - authTimer);
d2f487af 2387 break;
2388 }
50193c1e 2389 case MFEMUL_SELECT2:{
7bc95e2e 2390 if (!len) {
6a1f2d82 2391 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2392 break;
2393 }
8556b852 2394 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
9ca155ba 2395 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
8556b852
M
2396 break;
2397 }
9ca155ba 2398
8556b852
M
2399 // select 2 card
2400 if (len == 9 &&
2401 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2402 EmSendCmd(rSAK, sizeof(rSAK));
8556b852
M
2403 cuid = bytes_to_num(rUIDBCC2, 4);
2404 cardSTATE = MFEMUL_WORK;
2405 LED_B_ON();
0014cb46 2406 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
8556b852
M
2407 break;
2408 }
0014cb46
M
2409
2410 // i guess there is a command). go into the work state.
7bc95e2e 2411 if (len != 4) {
6a1f2d82 2412 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2413 break;
2414 }
0014cb46 2415 cardSTATE = MFEMUL_WORK;
d2f487af 2416 //goto lbWORK;
2417 //intentional fall-through to the next case-stmt
50193c1e 2418 }
51969283 2419
7bc95e2e 2420 case MFEMUL_WORK:{
2421 if (len == 0) {
6a1f2d82 2422 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2423 break;
2424 }
2425
d2f487af 2426 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2427
7bc95e2e 2428 if(encrypted_data) {
51969283
M
2429 // decrypt seqence
2430 mf_crypto1_decrypt(pcs, receivedCmd, len);
d2f487af 2431 }
7bc95e2e 2432
d2f487af 2433 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2434 authTimer = GetTickCount();
2435 cardAUTHSC = receivedCmd[1] / 4; // received block num
2436 cardAUTHKEY = receivedCmd[0] - 0x60;
2437 crypto1_destroy(pcs);//Added by martin
2438 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2439
d2f487af 2440 if (!encrypted_data) { // first authentication
b03c0f2d 2441 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
51969283 2442
d2f487af 2443 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2444 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
7bc95e2e 2445 } else { // nested authentication
b03c0f2d 2446 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
7bc95e2e 2447 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2448 num_to_bytes(ans, 4, rAUTH_AT);
2449 }
0c8d25eb 2450
d2f487af 2451 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2452 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2453 cardSTATE = MFEMUL_AUTH1;
2454 break;
51969283 2455 }
7bc95e2e 2456
8f51ddb0
M
2457 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2458 // BUT... ACK --> NACK
2459 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2460 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2461 break;
2462 }
2463
2464 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2465 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2466 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2467 break;
0a39986e
M
2468 }
2469
7bc95e2e 2470 if(len != 4) {
6a1f2d82 2471 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2472 break;
2473 }
d2f487af 2474
2475 if(receivedCmd[0] == 0x30 // read block
2476 || receivedCmd[0] == 0xA0 // write block
b03c0f2d 2477 || receivedCmd[0] == 0xC0 // inc
2478 || receivedCmd[0] == 0xC1 // dec
2479 || receivedCmd[0] == 0xC2 // restore
7bc95e2e 2480 || receivedCmd[0] == 0xB0) { // transfer
2481 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2482 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2483 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2484 break;
2485 }
2486
7bc95e2e 2487 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2488 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
d2f487af 2489 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2490 break;
2491 }
d2f487af 2492 }
2493 // read block
2494 if (receivedCmd[0] == 0x30) {
b03c0f2d 2495 if (MF_DBGLEVEL >= 4) {
d2f487af 2496 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2497 }
8f51ddb0
M
2498 emlGetMem(response, receivedCmd[1], 1);
2499 AppendCrc14443a(response, 16);
6a1f2d82 2500 mf_crypto1_encrypt(pcs, response, 18, response_par);
2501 EmSendCmdPar(response, 18, response_par);
d2f487af 2502 numReads++;
7bc95e2e 2503 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
d2f487af 2504 Dbprintf("%d reads done, exiting", numReads);
2505 finished = true;
2506 }
0a39986e
M
2507 break;
2508 }
0a39986e 2509 // write block
d2f487af 2510 if (receivedCmd[0] == 0xA0) {
b03c0f2d 2511 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
8f51ddb0 2512 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2513 cardSTATE = MFEMUL_WRITEBL2;
2514 cardWRBL = receivedCmd[1];
0a39986e 2515 break;
7bc95e2e 2516 }
0014cb46 2517 // increment, decrement, restore
d2f487af 2518 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
b03c0f2d 2519 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2520 if (emlCheckValBl(receivedCmd[1])) {
2521 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2522 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2523 break;
2524 }
2525 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2526 if (receivedCmd[0] == 0xC1)
2527 cardSTATE = MFEMUL_INTREG_INC;
2528 if (receivedCmd[0] == 0xC0)
2529 cardSTATE = MFEMUL_INTREG_DEC;
2530 if (receivedCmd[0] == 0xC2)
2531 cardSTATE = MFEMUL_INTREG_REST;
2532 cardWRBL = receivedCmd[1];
0014cb46
M
2533 break;
2534 }
0014cb46 2535 // transfer
d2f487af 2536 if (receivedCmd[0] == 0xB0) {
b03c0f2d 2537 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
0014cb46
M
2538 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2539 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2540 else
2541 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2542 break;
2543 }
9ca155ba 2544 // halt
d2f487af 2545 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
9ca155ba 2546 LED_B_OFF();
0a39986e 2547 LED_C_OFF();
0014cb46
M
2548 cardSTATE = MFEMUL_HALTED;
2549 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2550 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2551 break;
9ca155ba 2552 }
d2f487af 2553 // RATS
2554 if (receivedCmd[0] == 0xe0) {//RATS
8f51ddb0
M
2555 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2556 break;
2557 }
d2f487af 2558 // command not allowed
2559 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2560 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2561 break;
8f51ddb0
M
2562 }
2563 case MFEMUL_WRITEBL2:{
2564 if (len == 18){
2565 mf_crypto1_decrypt(pcs, receivedCmd, len);
2566 emlSetMem(receivedCmd, cardWRBL, 1);
2567 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2568 cardSTATE = MFEMUL_WORK;
51969283 2569 } else {
0014cb46 2570 cardSTATE_TO_IDLE();
6a1f2d82 2571 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2572 }
8f51ddb0 2573 break;
50193c1e 2574 }
0014cb46
M
2575
2576 case MFEMUL_INTREG_INC:{
2577 mf_crypto1_decrypt(pcs, receivedCmd, len);
2578 memcpy(&ans, receivedCmd, 4);
2579 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2580 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2581 cardSTATE_TO_IDLE();
2582 break;
7bc95e2e 2583 }
6a1f2d82 2584 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2585 cardINTREG = cardINTREG + ans;
2586 cardSTATE = MFEMUL_WORK;
2587 break;
2588 }
2589 case MFEMUL_INTREG_DEC:{
2590 mf_crypto1_decrypt(pcs, receivedCmd, len);
2591 memcpy(&ans, receivedCmd, 4);
2592 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2593 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2594 cardSTATE_TO_IDLE();
2595 break;
2596 }
6a1f2d82 2597 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2598 cardINTREG = cardINTREG - ans;
2599 cardSTATE = MFEMUL_WORK;
2600 break;
2601 }
2602 case MFEMUL_INTREG_REST:{
2603 mf_crypto1_decrypt(pcs, receivedCmd, len);
2604 memcpy(&ans, receivedCmd, 4);
2605 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2606 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2607 cardSTATE_TO_IDLE();
2608 break;
2609 }
6a1f2d82 2610 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2611 cardSTATE = MFEMUL_WORK;
2612 break;
2613 }
50193c1e 2614 }
50193c1e
M
2615 }
2616
9ca155ba
M
2617 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2618 LEDsoff();
2619
d2f487af 2620 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2621 {
2622 //May just aswell send the collected ar_nr in the response aswell
2623 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2624 }
d714d3ef 2625
d2f487af 2626 if(flags & FLAG_NR_AR_ATTACK)
2627 {
7bc95e2e 2628 if(ar_nr_collected > 1) {
d2f487af 2629 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
d714d3ef 2630 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
0c8d25eb 2631 ar_nr_responses[0], // UID
d2f487af 2632 ar_nr_responses[1], //NT
2633 ar_nr_responses[2], //AR1
2634 ar_nr_responses[3], //NR1
2635 ar_nr_responses[6], //AR2
2636 ar_nr_responses[7] //NR2
2637 );
7bc95e2e 2638 } else {
d2f487af 2639 Dbprintf("Failed to obtain two AR/NR pairs!");
7bc95e2e 2640 if(ar_nr_collected >0) {
d714d3ef 2641 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
d2f487af 2642 ar_nr_responses[0], // UID
2643 ar_nr_responses[1], //NT
2644 ar_nr_responses[2], //AR1
2645 ar_nr_responses[3] //NR1
2646 );
2647 }
2648 }
2649 }
3000dc4e 2650 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
0c8d25eb 2651
15c4dc5a 2652}
b62a5a84 2653
d2f487af 2654
2655
b62a5a84
M
2656//-----------------------------------------------------------------------------
2657// MIFARE sniffer.
2658//
2659//-----------------------------------------------------------------------------
5cd9ec01
M
2660void RAMFUNC SniffMifare(uint8_t param) {
2661 // param:
2662 // bit 0 - trigger from first card answer
2663 // bit 1 - trigger from first reader 7-bit request
39864b0b
M
2664
2665 // C(red) A(yellow) B(green)
b62a5a84
M
2666 LEDsoff();
2667 // init trace buffer
3000dc4e
MHS
2668 clear_trace();
2669 set_tracing(TRUE);
b62a5a84 2670
b62a5a84
M
2671 // The command (reader -> tag) that we're receiving.
2672 // The length of a received command will in most cases be no more than 18 bytes.
2673 // So 32 should be enough!
f71f4deb 2674 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2675 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
b62a5a84 2676 // The response (tag -> reader) that we're receiving.
f71f4deb 2677 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2678 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
b62a5a84
M
2679
2680 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2681 // into trace, along with its length and other annotations.
2682 //uint8_t *trace = (uint8_t *)BigBuf;
2683
f71f4deb 2684 // free eventually allocated BigBuf memory
2685 BigBuf_free();
2686 // allocate the DMA buffer, used to stream samples from the FPGA
2687 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 2688 uint8_t *data = dmaBuf;
2689 uint8_t previous_data = 0;
5cd9ec01
M
2690 int maxDataLen = 0;
2691 int dataLen = 0;
7bc95e2e 2692 bool ReaderIsActive = FALSE;
2693 bool TagIsActive = FALSE;
2694
2695 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
b62a5a84
M
2696
2697 // Set up the demodulator for tag -> reader responses.
6a1f2d82 2698 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
2699
2700 // Set up the demodulator for the reader -> tag commands
6a1f2d82 2701 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
2702
2703 // Setup for the DMA.
7bc95e2e 2704 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 2705
b62a5a84 2706 LED_D_OFF();
39864b0b
M
2707
2708 // init sniffer
2709 MfSniffInit();
b62a5a84 2710
b62a5a84 2711 // And now we loop, receiving samples.
7bc95e2e 2712 for(uint32_t sniffCounter = 0; TRUE; ) {
2713
5cd9ec01
M
2714 if(BUTTON_PRESS()) {
2715 DbpString("cancelled by button");
7bc95e2e 2716 break;
5cd9ec01
M
2717 }
2718
b62a5a84
M
2719 LED_A_ON();
2720 WDT_HIT();
39864b0b 2721
7bc95e2e 2722 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2723 // check if a transaction is completed (timeout after 2000ms).
2724 // if yes, stop the DMA transfer and send what we have so far to the client
2725 if (MfSniffSend(2000)) {
2726 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2727 sniffCounter = 0;
2728 data = dmaBuf;
2729 maxDataLen = 0;
2730 ReaderIsActive = FALSE;
2731 TagIsActive = FALSE;
2732 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 2733 }
39864b0b 2734 }
7bc95e2e 2735
2736 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2737 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2738 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2739 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2740 } else {
2741 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
5cd9ec01
M
2742 }
2743 // test for length of buffer
7bc95e2e 2744 if(dataLen > maxDataLen) { // we are more behind than ever...
2745 maxDataLen = dataLen;
f71f4deb 2746 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 2747 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 2748 break;
b62a5a84
M
2749 }
2750 }
5cd9ec01 2751 if(dataLen < 1) continue;
b62a5a84 2752
7bc95e2e 2753 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
2754 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2755 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2756 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
55acbb2a 2757 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
2758 }
2759 // secondary buffer sets as primary, secondary buffer was stopped
2760 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2761 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
2762 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2763 }
5cd9ec01
M
2764
2765 LED_A_OFF();
b62a5a84 2766
7bc95e2e 2767 if (sniffCounter & 0x01) {
b62a5a84 2768
7bc95e2e 2769 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2770 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2771 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2772 LED_C_INV();
6a1f2d82 2773 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 2774
7bc95e2e 2775 /* And ready to receive another command. */
2776 UartReset();
2777
2778 /* And also reset the demod code */
2779 DemodReset();
2780 }
2781 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2782 }
2783
2784 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2785 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2786 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2787 LED_C_INV();
b62a5a84 2788
6a1f2d82 2789 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 2790
7bc95e2e 2791 // And ready to receive another response.
2792 DemodReset();
2793 }
2794 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2795 }
b62a5a84
M
2796 }
2797
7bc95e2e 2798 previous_data = *data;
2799 sniffCounter++;
5cd9ec01 2800 data++;
d714d3ef 2801 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01 2802 data = dmaBuf;
b62a5a84 2803 }
7bc95e2e 2804
b62a5a84
M
2805 } // main cycle
2806
2807 DbpString("COMMAND FINISHED");
2808
55acbb2a 2809 FpgaDisableSscDma();
39864b0b
M
2810 MfSniffEnd();
2811
7bc95e2e 2812 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
b62a5a84 2813 LEDsoff();
3803d529 2814}
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