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fix: avoid USB Speed Test timeout in case of slow transfer speeds
[proxmark3-svn] / armsrc / lfops.c
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e09f21fa 1//-----------------------------------------------------------------------------
2// This code is licensed to you under the terms of the GNU GPL, version 2 or,
3// at your option, any later version. See the LICENSE.txt file for the text of
4// the license.
5//-----------------------------------------------------------------------------
6// Miscellaneous routines for low frequency tag operations.
7// Tags supported here so far are Texas Instruments (TI), HID
8// Also routines for raw mode reading/simulating of LF waveform
9//-----------------------------------------------------------------------------
10
11#include "proxmark3.h"
12#include "apps.h"
13#include "util.h"
14#include "hitag2.h"
15#include "crc16.h"
16#include "string.h"
17#include "lfdemod.h"
18#include "lfsampling.h"
f7048dc8 19#include "usb_cdc.h"
e09f21fa 20
21
22/**
23 * Function to do a modulation and then get samples.
24 * @param delay_off
25 * @param period_0
26 * @param period_1
27 * @param command
28 */
29void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
30{
31
e0165dcf 32 int divisor_used = 95; // 125 KHz
33 // see if 'h' was specified
e09f21fa 34
e0165dcf 35 if (command[strlen((char *) command) - 1] == 'h')
36 divisor_used = 88; // 134.8 KHz
e09f21fa 37
38 sample_config sc = { 0,0,1, divisor_used, 0};
39 setSamplingConfig(&sc);
40
41 /* Make sure the tag is reset */
42 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
43 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
44 SpinDelay(2500);
45
46 LFSetupFPGAForADC(sc.divisor, 1);
47
48 // And a little more time for the tag to fully power up
49 SpinDelay(2000);
50
e0165dcf 51 // now modulate the reader field
52 while(*command != '\0' && *command != ' ') {
53 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
54 LED_D_OFF();
55 SpinDelayUs(delay_off);
e09f21fa 56 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
57
e0165dcf 58 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
59 LED_D_ON();
60 if(*(command++) == '0')
61 SpinDelayUs(period_0);
62 else
63 SpinDelayUs(period_1);
64 }
65 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
66 LED_D_OFF();
67 SpinDelayUs(delay_off);
e09f21fa 68 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
69
e0165dcf 70 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
e09f21fa 71
e0165dcf 72 // now do the read
e09f21fa 73 DoAcquisition_config(false);
74}
75
76
77
78/* blank r/w tag data stream
79...0000000000000000 01111111
801010101010101010101010101010101010101010101010101010101010101010
810011010010100001
8201111111
83101010101010101[0]000...
84
85[5555fe852c5555555555555555fe0000]
86*/
87void ReadTItag(void)
88{
e0165dcf 89 // some hardcoded initial params
90 // when we read a TI tag we sample the zerocross line at 2Mhz
91 // TI tags modulate a 1 as 16 cycles of 123.2Khz
92 // TI tags modulate a 0 as 16 cycles of 134.2Khz
e09f21fa 93 #define FSAMPLE 2000000
94 #define FREQLO 123200
95 #define FREQHI 134200
96
e0165dcf 97 signed char *dest = (signed char *)BigBuf_get_addr();
98 uint16_t n = BigBuf_max_traceLen();
99 // 128 bit shift register [shift3:shift2:shift1:shift0]
100 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
101
102 int i, cycles=0, samples=0;
103 // how many sample points fit in 16 cycles of each frequency
104 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
105 // when to tell if we're close enough to one freq or another
106 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
107
108 // TI tags charge at 134.2Khz
109 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
111
112 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
113 // connects to SSP_DIN and the SSP_DOUT logic level controls
114 // whether we're modulating the antenna (high)
115 // or listening to the antenna (low)
116 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
117
118 // get TI tag data into the buffer
119 AcquireTiType();
120
121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
122
123 for (i=0; i<n-1; i++) {
124 // count cycles by looking for lo to hi zero crossings
125 if ( (dest[i]<0) && (dest[i+1]>0) ) {
126 cycles++;
127 // after 16 cycles, measure the frequency
128 if (cycles>15) {
129 cycles=0;
130 samples=i-samples; // number of samples in these 16 cycles
131
132 // TI bits are coming to us lsb first so shift them
133 // right through our 128 bit right shift register
134 shift0 = (shift0>>1) | (shift1 << 31);
135 shift1 = (shift1>>1) | (shift2 << 31);
136 shift2 = (shift2>>1) | (shift3 << 31);
137 shift3 >>= 1;
138
139 // check if the cycles fall close to the number
140 // expected for either the low or high frequency
141 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
142 // low frequency represents a 1
143 shift3 |= (1<<31);
144 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
145 // high frequency represents a 0
146 } else {
147 // probably detected a gay waveform or noise
148 // use this as gaydar or discard shift register and start again
149 shift3 = shift2 = shift1 = shift0 = 0;
150 }
151 samples = i;
152
153 // for each bit we receive, test if we've detected a valid tag
154
155 // if we see 17 zeroes followed by 6 ones, we might have a tag
156 // remember the bits are backwards
157 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
158 // if start and end bytes match, we have a tag so break out of the loop
159 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
160 cycles = 0xF0B; //use this as a flag (ugly but whatever)
161 break;
162 }
163 }
164 }
165 }
166 }
167
168 // if flag is set we have a tag
169 if (cycles!=0xF0B) {
170 DbpString("Info: No valid tag detected.");
171 } else {
172 // put 64 bit data into shift1 and shift0
173 shift0 = (shift0>>24) | (shift1 << 8);
174 shift1 = (shift1>>24) | (shift2 << 8);
175
176 // align 16 bit crc into lower half of shift2
177 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
178
179 // if r/w tag, check ident match
e09f21fa 180 if (shift3 & (1<<15) ) {
e0165dcf 181 DbpString("Info: TI tag is rewriteable");
182 // only 15 bits compare, last bit of ident is not valid
e09f21fa 183 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
e0165dcf 184 DbpString("Error: Ident mismatch!");
185 } else {
186 DbpString("Info: TI tag ident is valid");
187 }
188 } else {
189 DbpString("Info: TI tag is readonly");
190 }
191
192 // WARNING the order of the bytes in which we calc crc below needs checking
193 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
194 // bytes in reverse or something
195 // calculate CRC
196 uint32_t crc=0;
197
198 crc = update_crc16(crc, (shift0)&0xff);
199 crc = update_crc16(crc, (shift0>>8)&0xff);
200 crc = update_crc16(crc, (shift0>>16)&0xff);
201 crc = update_crc16(crc, (shift0>>24)&0xff);
202 crc = update_crc16(crc, (shift1)&0xff);
203 crc = update_crc16(crc, (shift1>>8)&0xff);
204 crc = update_crc16(crc, (shift1>>16)&0xff);
205 crc = update_crc16(crc, (shift1>>24)&0xff);
206
207 Dbprintf("Info: Tag data: %x%08x, crc=%x",
208 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
209 if (crc != (shift2&0xffff)) {
210 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
211 } else {
212 DbpString("Info: CRC is good");
213 }
214 }
e09f21fa 215}
216
217void WriteTIbyte(uint8_t b)
218{
e0165dcf 219 int i = 0;
220
221 // modulate 8 bits out to the antenna
222 for (i=0; i<8; i++)
223 {
224 if (b&(1<<i)) {
225 // stop modulating antenna
226 LOW(GPIO_SSC_DOUT);
227 SpinDelayUs(1000);
228 // modulate antenna
229 HIGH(GPIO_SSC_DOUT);
230 SpinDelayUs(1000);
231 } else {
232 // stop modulating antenna
233 LOW(GPIO_SSC_DOUT);
234 SpinDelayUs(300);
235 // modulate antenna
236 HIGH(GPIO_SSC_DOUT);
237 SpinDelayUs(1700);
238 }
239 }
e09f21fa 240}
241
242void AcquireTiType(void)
243{
e0165dcf 244 int i, j, n;
245 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
246 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
e09f21fa 247 #define TIBUFLEN 1250
248
e0165dcf 249 // clear buffer
e09f21fa 250 uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
e0165dcf 251 memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
252
253 // Set up the synchronous serial port
254 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
255 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
256
257 // steal this pin from the SSP and use it to control the modulation
258 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
259 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
260
261 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
262 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
263
264 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
265 // 48/2 = 24 MHz clock must be divided by 12
266 AT91C_BASE_SSC->SSC_CMR = 12;
267
268 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
269 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
270 AT91C_BASE_SSC->SSC_TCMR = 0;
271 AT91C_BASE_SSC->SSC_TFMR = 0;
272
273 LED_D_ON();
274
275 // modulate antenna
276 HIGH(GPIO_SSC_DOUT);
277
278 // Charge TI tag for 50ms.
279 SpinDelay(50);
280
281 // stop modulating antenna and listen
282 LOW(GPIO_SSC_DOUT);
283
284 LED_D_OFF();
285
286 i = 0;
287 for(;;) {
288 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
289 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
290 i++; if(i >= TIBUFLEN) break;
291 }
292 WDT_HIT();
293 }
294
295 // return stolen pin to SSP
296 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
297 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
298
299 char *dest = (char *)BigBuf_get_addr();
300 n = TIBUFLEN*32;
301 // unpack buffer
302 for (i=TIBUFLEN-1; i>=0; i--) {
303 for (j=0; j<32; j++) {
304 if(BigBuf[i] & (1 << j)) {
305 dest[--n] = 1;
306 } else {
307 dest[--n] = -1;
308 }
309 }
310 }
e09f21fa 311}
312
313// arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
314// if crc provided, it will be written with the data verbatim (even if bogus)
315// if not provided a valid crc will be computed from the data and written.
316void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
317{
e0165dcf 318 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
319 if(crc == 0) {
320 crc = update_crc16(crc, (idlo)&0xff);
321 crc = update_crc16(crc, (idlo>>8)&0xff);
322 crc = update_crc16(crc, (idlo>>16)&0xff);
323 crc = update_crc16(crc, (idlo>>24)&0xff);
324 crc = update_crc16(crc, (idhi)&0xff);
325 crc = update_crc16(crc, (idhi>>8)&0xff);
326 crc = update_crc16(crc, (idhi>>16)&0xff);
327 crc = update_crc16(crc, (idhi>>24)&0xff);
328 }
329 Dbprintf("Writing to tag: %x%08x, crc=%x",
330 (unsigned int) idhi, (unsigned int) idlo, crc);
331
332 // TI tags charge at 134.2Khz
333 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
334 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
335 // connects to SSP_DIN and the SSP_DOUT logic level controls
336 // whether we're modulating the antenna (high)
337 // or listening to the antenna (low)
338 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
339 LED_A_ON();
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 // writing algorithm:
346 // a high bit consists of a field off for 1ms and field on for 1ms
347 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
348 // initiate a charge time of 50ms (field on) then immediately start writing bits
349 // start by writing 0xBB (keyword) and 0xEB (password)
350 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
351 // finally end with 0x0300 (write frame)
352 // all data is sent lsb firts
353 // finish with 15ms programming time
354
355 // modulate antenna
356 HIGH(GPIO_SSC_DOUT);
357 SpinDelay(50); // charge time
358
359 WriteTIbyte(0xbb); // keyword
360 WriteTIbyte(0xeb); // password
361 WriteTIbyte( (idlo )&0xff );
362 WriteTIbyte( (idlo>>8 )&0xff );
363 WriteTIbyte( (idlo>>16)&0xff );
364 WriteTIbyte( (idlo>>24)&0xff );
365 WriteTIbyte( (idhi )&0xff );
366 WriteTIbyte( (idhi>>8 )&0xff );
367 WriteTIbyte( (idhi>>16)&0xff );
368 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
369 WriteTIbyte( (crc )&0xff ); // crc lo
370 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
371 WriteTIbyte(0x00); // write frame lo
372 WriteTIbyte(0x03); // write frame hi
373 HIGH(GPIO_SSC_DOUT);
374 SpinDelay(50); // programming time
375
376 LED_A_OFF();
377
378 // get TI tag data into the buffer
379 AcquireTiType();
380
381 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
382 DbpString("Now use tiread to check");
e09f21fa 383}
384
385void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
386{
e0165dcf 387 int i;
388 uint8_t *tab = BigBuf_get_addr();
e09f21fa 389
e0165dcf 390 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
391 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
e09f21fa 392
e0165dcf 393 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
e09f21fa 394
e0165dcf 395 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
396 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
e09f21fa 397
398 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
399 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
400
e0165dcf 401 i = 0;
402 for(;;) {
403 //wait until SSC_CLK goes HIGH
404 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
83f3f8ac 405 if(BUTTON_PRESS() || (usb_poll_validate_length() )) {
e0165dcf 406 DbpString("Stopped");
407 return;
408 }
409 WDT_HIT();
410 }
411 if (ledcontrol)
412 LED_D_ON();
413
414 if(tab[i])
415 OPEN_COIL();
416 else
417 SHORT_COIL();
418
419 if (ledcontrol)
420 LED_D_OFF();
421 //wait until SSC_CLK goes LOW
422 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
423 if(BUTTON_PRESS()) {
424 DbpString("Stopped");
425 return;
426 }
427 WDT_HIT();
428 }
429
430 i++;
431 if(i == period) {
432
433 i = 0;
434 if (gap) {
435 SHORT_COIL();
436 SpinDelayUs(gap);
437 }
438 }
439 }
e09f21fa 440}
441
e09f21fa 442#define DEBUG_FRAME_CONTENTS 1
443void SimulateTagLowFrequencyBidir(int divisor, int t0)
444{
445}
446
447// compose fc/8 fc/10 waveform (FSK2)
448static void fc(int c, int *n)
449{
e0165dcf 450 uint8_t *dest = BigBuf_get_addr();
451 int idx;
452
453 // for when we want an fc8 pattern every 4 logical bits
454 if(c==0) {
455 dest[((*n)++)]=1;
456 dest[((*n)++)]=1;
457 dest[((*n)++)]=1;
458 dest[((*n)++)]=1;
459 dest[((*n)++)]=0;
460 dest[((*n)++)]=0;
461 dest[((*n)++)]=0;
462 dest[((*n)++)]=0;
463 }
464
465 // an fc/8 encoded bit is a bit pattern of 11110000 x6 = 48 samples
466 if(c==8) {
467 for (idx=0; idx<6; idx++) {
468 dest[((*n)++)]=1;
469 dest[((*n)++)]=1;
470 dest[((*n)++)]=1;
471 dest[((*n)++)]=1;
472 dest[((*n)++)]=0;
473 dest[((*n)++)]=0;
474 dest[((*n)++)]=0;
475 dest[((*n)++)]=0;
476 }
477 }
478
479 // an fc/10 encoded bit is a bit pattern of 1111100000 x5 = 50 samples
480 if(c==10) {
481 for (idx=0; idx<5; idx++) {
482 dest[((*n)++)]=1;
483 dest[((*n)++)]=1;
484 dest[((*n)++)]=1;
485 dest[((*n)++)]=1;
486 dest[((*n)++)]=1;
487 dest[((*n)++)]=0;
488 dest[((*n)++)]=0;
489 dest[((*n)++)]=0;
490 dest[((*n)++)]=0;
491 dest[((*n)++)]=0;
492 }
493 }
e09f21fa 494}
495// compose fc/X fc/Y waveform (FSKx)
712ebfa6 496static void fcAll(uint8_t fc, int *n, uint8_t clock, uint16_t *modCnt)
e09f21fa 497{
e0165dcf 498 uint8_t *dest = BigBuf_get_addr();
499 uint8_t halfFC = fc/2;
500 uint8_t wavesPerClock = clock/fc;
501 uint8_t mod = clock % fc; //modifier
502 uint8_t modAdj = fc/mod; //how often to apply modifier
503 bool modAdjOk = !(fc % mod); //if (fc % mod==0) modAdjOk=TRUE;
504 // loop through clock - step field clock
505 for (uint8_t idx=0; idx < wavesPerClock; idx++){
506 // put 1/2 FC length 1's and 1/2 0's per field clock wave (to create the wave)
507 memset(dest+(*n), 0, fc-halfFC); //in case of odd number use extra here
508 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
509 *n += fc;
510 }
511 if (mod>0) (*modCnt)++;
512 if ((mod>0) && modAdjOk){ //fsk2
513 if ((*modCnt % modAdj) == 0){ //if 4th 8 length wave in a rf/50 add extra 8 length wave
514 memset(dest+(*n), 0, fc-halfFC);
515 memset(dest+(*n)+(fc-halfFC), 1, halfFC);
516 *n += fc;
517 }
518 }
519 if (mod>0 && !modAdjOk){ //fsk1
520 memset(dest+(*n), 0, mod-(mod/2));
521 memset(dest+(*n)+(mod-(mod/2)), 1, mod/2);
522 *n += mod;
523 }
e09f21fa 524}
525
526// prepare a waveform pattern in the buffer based on the ID given then
527// simulate a HID tag until the button is pressed
528void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
529{
e0165dcf 530 int n=0, i=0;
531 /*
532 HID tag bitstream format
533 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
534 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
535 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
536 A fc8 is inserted before every 4 bits
537 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
538 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
539 */
540
541 if (hi>0xFFF) {
542 DbpString("Tags can only have 44 bits. - USE lf simfsk for larger tags");
543 return;
544 }
545 fc(0,&n);
546 // special start of frame marker containing invalid bit sequences
547 fc(8, &n); fc(8, &n); // invalid
548 fc(8, &n); fc(10, &n); // logical 0
549 fc(10, &n); fc(10, &n); // invalid
550 fc(8, &n); fc(10, &n); // logical 0
551
552 WDT_HIT();
553 // manchester encode bits 43 to 32
554 for (i=11; i>=0; i--) {
555 if ((i%4)==3) fc(0,&n);
556 if ((hi>>i)&1) {
557 fc(10, &n); fc(8, &n); // low-high transition
558 } else {
559 fc(8, &n); fc(10, &n); // high-low transition
560 }
561 }
562
563 WDT_HIT();
564 // manchester encode bits 31 to 0
565 for (i=31; i>=0; i--) {
566 if ((i%4)==3) fc(0,&n);
567 if ((lo>>i)&1) {
568 fc(10, &n); fc(8, &n); // low-high transition
569 } else {
570 fc(8, &n); fc(10, &n); // high-low transition
571 }
572 }
573
574 if (ledcontrol)
575 LED_A_ON();
576 SimulateTagLowFrequency(n, 0, ledcontrol);
577
578 if (ledcontrol)
579 LED_A_OFF();
e09f21fa 580}
581
582// prepare a waveform pattern in the buffer based on the ID given then
583// simulate a FSK tag until the button is pressed
584// arg1 contains fcHigh and fcLow, arg2 contains invert and clock
585void CmdFSKsimTAG(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
586{
e0165dcf 587 int ledcontrol=1;
588 int n=0, i=0;
589 uint8_t fcHigh = arg1 >> 8;
590 uint8_t fcLow = arg1 & 0xFF;
591 uint16_t modCnt = 0;
592 uint8_t clk = arg2 & 0xFF;
593 uint8_t invert = (arg2 >> 8) & 1;
594
595 for (i=0; i<size; i++){
596 if (BitStream[i] == invert){
597 fcAll(fcLow, &n, clk, &modCnt);
598 } else {
599 fcAll(fcHigh, &n, clk, &modCnt);
600 }
601 }
602 Dbprintf("Simulating with fcHigh: %d, fcLow: %d, clk: %d, invert: %d, n: %d",fcHigh, fcLow, clk, invert, n);
603 /*Dbprintf("DEBUG: First 32:");
604 uint8_t *dest = BigBuf_get_addr();
605 i=0;
606 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
607 i+=16;
608 Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
609 */
610 if (ledcontrol)
611 LED_A_ON();
612
613 SimulateTagLowFrequency(n, 0, ledcontrol);
614
615 if (ledcontrol)
616 LED_A_OFF();
e09f21fa 617}
618
619// compose ask waveform for one bit(ASK)
e0165dcf 620static void askSimBit(uint8_t c, int *n, uint8_t clock, uint8_t manchester)
e09f21fa 621{
e0165dcf 622 uint8_t *dest = BigBuf_get_addr();
623 uint8_t halfClk = clock/2;
624 // c = current bit 1 or 0
625 if (manchester==1){
626 memset(dest+(*n), c, halfClk);
627 memset(dest+(*n) + halfClk, c^1, halfClk);
628 } else {
629 memset(dest+(*n), c, clock);
630 }
631 *n += clock;
e09f21fa 632}
633
b41534d1 634static void biphaseSimBit(uint8_t c, int *n, uint8_t clock, uint8_t *phase)
635{
e0165dcf 636 uint8_t *dest = BigBuf_get_addr();
637 uint8_t halfClk = clock/2;
638 if (c){
639 memset(dest+(*n), c ^ 1 ^ *phase, halfClk);
640 memset(dest+(*n) + halfClk, c ^ *phase, halfClk);
641 } else {
642 memset(dest+(*n), c ^ *phase, clock);
643 *phase ^= 1;
644 }
b41534d1 645
646}
647
e09f21fa 648// args clock, ask/man or askraw, invert, transmission separator
649void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
650{
e0165dcf 651 int ledcontrol = 1;
652 int n=0, i=0;
653 uint8_t clk = (arg1 >> 8) & 0xFF;
2b3af97d 654 uint8_t encoding = arg1 & 0xFF;
e0165dcf 655 uint8_t separator = arg2 & 1;
656 uint8_t invert = (arg2 >> 8) & 1;
657
658 if (encoding==2){ //biphase
659 uint8_t phase=0;
660 for (i=0; i<size; i++){
661 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
662 }
663 if (BitStream[0]==BitStream[size-1]){ //run a second set inverted to keep phase in check
664 for (i=0; i<size; i++){
665 biphaseSimBit(BitStream[i]^invert, &n, clk, &phase);
666 }
667 }
668 } else { // ask/manchester || ask/raw
669 for (i=0; i<size; i++){
670 askSimBit(BitStream[i]^invert, &n, clk, encoding);
671 }
672 if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
673 for (i=0; i<size; i++){
674 askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
675 }
676 }
677 }
678
679 if (separator==1) Dbprintf("sorry but separator option not yet available");
680
681 Dbprintf("Simulating with clk: %d, invert: %d, encoding: %d, separator: %d, n: %d",clk, invert, encoding, separator, n);
682 //DEBUG
683 //Dbprintf("First 32:");
684 //uint8_t *dest = BigBuf_get_addr();
685 //i=0;
686 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
687 //i+=16;
688 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
689
690 if (ledcontrol)
691 LED_A_ON();
692
693 SimulateTagLowFrequency(n, 0, ledcontrol);
694
695 if (ledcontrol)
696 LED_A_OFF();
e09f21fa 697}
698
699//carrier can be 2,4 or 8
700static void pskSimBit(uint8_t waveLen, int *n, uint8_t clk, uint8_t *curPhase, bool phaseChg)
701{
e0165dcf 702 uint8_t *dest = BigBuf_get_addr();
703 uint8_t halfWave = waveLen/2;
704 //uint8_t idx;
705 int i = 0;
706 if (phaseChg){
707 // write phase change
708 memset(dest+(*n), *curPhase^1, halfWave);
709 memset(dest+(*n) + halfWave, *curPhase, halfWave);
710 *n += waveLen;
711 *curPhase ^= 1;
712 i += waveLen;
713 }
714 //write each normal clock wave for the clock duration
715 for (; i < clk; i+=waveLen){
716 memset(dest+(*n), *curPhase, halfWave);
717 memset(dest+(*n) + halfWave, *curPhase^1, halfWave);
718 *n += waveLen;
719 }
e09f21fa 720}
721
722// args clock, carrier, invert,
723void CmdPSKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
724{
e0165dcf 725 int ledcontrol=1;
726 int n=0, i=0;
727 uint8_t clk = arg1 >> 8;
728 uint8_t carrier = arg1 & 0xFF;
729 uint8_t invert = arg2 & 0xFF;
730 uint8_t curPhase = 0;
731 for (i=0; i<size; i++){
732 if (BitStream[i] == curPhase){
733 pskSimBit(carrier, &n, clk, &curPhase, FALSE);
734 } else {
735 pskSimBit(carrier, &n, clk, &curPhase, TRUE);
736 }
737 }
738 Dbprintf("Simulating with Carrier: %d, clk: %d, invert: %d, n: %d",carrier, clk, invert, n);
739 //Dbprintf("DEBUG: First 32:");
740 //uint8_t *dest = BigBuf_get_addr();
741 //i=0;
742 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
743 //i+=16;
744 //Dbprintf("%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d%d", dest[i],dest[i+1],dest[i+2],dest[i+3],dest[i+4],dest[i+5],dest[i+6],dest[i+7],dest[i+8],dest[i+9],dest[i+10],dest[i+11],dest[i+12],dest[i+13],dest[i+14],dest[i+15]);
745
746 if (ledcontrol)
747 LED_A_ON();
748 SimulateTagLowFrequency(n, 0, ledcontrol);
749
750 if (ledcontrol)
751 LED_A_OFF();
e09f21fa 752}
753
754// loop to get raw HID waveform then FSK demodulate the TAG ID from it
755void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
756{
e0165dcf 757 uint8_t *dest = BigBuf_get_addr();
2eec55c8 758 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
759 size_t size;
e0165dcf 760 uint32_t hi2=0, hi=0, lo=0;
761 int idx=0;
762 // Configure to go in 125Khz listen mode
763 LFSetupFPGAForADC(95, true);
e09f21fa 764
e0165dcf 765 while(!BUTTON_PRESS()) {
e09f21fa 766
e0165dcf 767 WDT_HIT();
768 if (ledcontrol) LED_A_ON();
e09f21fa 769
770 DoAcquisition_default(-1,true);
771 // FSK demodulator
2eec55c8 772 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
773 size = 50*128*2; //big enough to catch 2 sequences of largest format
e09f21fa 774 idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
e0165dcf 775
2eec55c8 776 if (idx>0 && lo>0 && (size==96 || size==192)){
777 // go over previously decoded manchester data and decode into usable tag ID
778 if (hi2 != 0){ //extra large HID tags 88/192 bits
e0165dcf 779 Dbprintf("TAG ID: %x%08x%08x (%d)",
780 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
2eec55c8 781 }else { //standard HID tags 44/96 bits
e0165dcf 782 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
783 uint8_t bitlen = 0;
784 uint32_t fc = 0;
785 uint32_t cardnum = 0;
e09f21fa 786 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
e0165dcf 787 uint32_t lo2=0;
788 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
789 uint8_t idx3 = 1;
e09f21fa 790 while(lo2 > 1){ //find last bit set to 1 (format len bit)
791 lo2=lo2 >> 1;
e0165dcf 792 idx3++;
793 }
e09f21fa 794 bitlen = idx3+19;
e0165dcf 795 fc =0;
796 cardnum=0;
e09f21fa 797 if(bitlen == 26){
e0165dcf 798 cardnum = (lo>>1)&0xFFFF;
799 fc = (lo>>17)&0xFF;
800 }
e09f21fa 801 if(bitlen == 37){
e0165dcf 802 cardnum = (lo>>1)&0x7FFFF;
803 fc = ((hi&0xF)<<12)|(lo>>20);
804 }
e09f21fa 805 if(bitlen == 34){
e0165dcf 806 cardnum = (lo>>1)&0xFFFF;
807 fc= ((hi&1)<<15)|(lo>>17);
808 }
e09f21fa 809 if(bitlen == 35){
e0165dcf 810 cardnum = (lo>>1)&0xFFFFF;
811 fc = ((hi&1)<<11)|(lo>>21);
812 }
813 }
814 else { //if bit 38 is not set then 37 bit format is used
815 bitlen= 37;
816 fc =0;
817 cardnum=0;
818 if(bitlen==37){
819 cardnum = (lo>>1)&0x7FFFF;
820 fc = ((hi&0xF)<<12)|(lo>>20);
821 }
822 }
823 //Dbprintf("TAG ID: %x%08x (%d)",
824 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
825 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
826 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
827 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
828 }
829 if (findone){
830 if (ledcontrol) LED_A_OFF();
831 *high = hi;
832 *low = lo;
833 return;
834 }
835 // reset
e0165dcf 836 }
2eec55c8 837 hi2 = hi = lo = idx = 0;
e0165dcf 838 WDT_HIT();
839 }
840 DbpString("Stopped");
841 if (ledcontrol) LED_A_OFF();
e09f21fa 842}
843
dbf6e824
CY
844// loop to get raw HID waveform then FSK demodulate the TAG ID from it
845void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
846{
847 uint8_t *dest = BigBuf_get_addr();
848 //const size_t sizeOfBigBuff = BigBuf_max_traceLen();
849 size_t size;
850 int idx=0;
851 // Configure to go in 125Khz listen mode
852 LFSetupFPGAForADC(95, true);
853
854 while(!BUTTON_PRESS()) {
855
856 WDT_HIT();
857 if (ledcontrol) LED_A_ON();
858
859 DoAcquisition_default(-1,true);
860 // FSK demodulator
861 //size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
862 size = 50*128*2; //big enough to catch 2 sequences of largest format
863 idx = AWIDdemodFSK(dest, &size);
864
865 if (idx>0 && size==96){
866 // Index map
867 // 0 10 20 30 40 50 60
868 // | | | | | | |
869 // 01234567 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 456 7 890 1 234 5 678 9 012 3 - to 96
870 // -----------------------------------------------------------------------------
871 // 00000001 000 1 110 1 101 1 011 1 101 1 010 0 000 1 000 1 010 0 001 0 110 1 100 0 000 1 000 1
872 // premable bbb o bbb o bbw o fff o fff o ffc o ccc o ccc o ccc o ccc o ccc o wxx o xxx o xxx o - to 96
873 // |---26 bit---| |-----117----||-------------142-------------|
874 // b = format bit len, o = odd parity of last 3 bits
875 // f = facility code, c = card number
876 // w = wiegand parity
877 // (26 bit format shown)
878
879 //get raw ID before removing parities
880 uint32_t rawLo = bytebits_to_byte(dest+idx+64,32);
881 uint32_t rawHi = bytebits_to_byte(dest+idx+32,32);
882 uint32_t rawHi2 = bytebits_to_byte(dest+idx,32);
883
884 size = removeParity(dest, idx+8, 4, 1, 88);
885 // ok valid card found!
886
887 // Index map
888 // 0 10 20 30 40 50 60
889 // | | | | | | |
890 // 01234567 8 90123456 7890123456789012 3 456789012345678901234567890123456
891 // -----------------------------------------------------------------------------
892 // 00011010 1 01110101 0000000010001110 1 000000000000000000000000000000000
893 // bbbbbbbb w ffffffff cccccccccccccccc w xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
894 // |26 bit| |-117--| |-----142------|
895 // b = format bit len, o = odd parity of last 3 bits
896 // f = facility code, c = card number
897 // w = wiegand parity
898 // (26 bit format shown)
899
900 uint32_t fc = 0;
901 uint32_t cardnum = 0;
902 uint32_t code1 = 0;
903 uint32_t code2 = 0;
904 uint8_t fmtLen = bytebits_to_byte(dest,8);
905 if (fmtLen==26){
906 fc = bytebits_to_byte(dest+9, 8);
907 cardnum = bytebits_to_byte(dest+17, 16);
908 code1 = bytebits_to_byte(dest+8,fmtLen);
909 Dbprintf("AWID Found - BitLength: %d, FC: %d, Card: %d - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, fc, cardnum, code1, rawHi2, rawHi, rawLo);
910 } else {
911 cardnum = bytebits_to_byte(dest+8+(fmtLen-17), 16);
912 if (fmtLen>32){
913 code1 = bytebits_to_byte(dest+8,fmtLen-32);
914 code2 = bytebits_to_byte(dest+8+(fmtLen-32),32);
915 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x%08x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, code2, rawHi2, rawHi, rawLo);
916 } else{
917 code1 = bytebits_to_byte(dest+8,fmtLen);
918 Dbprintf("AWID Found - BitLength: %d -unknown BitLength- (%d) - Wiegand: %x, Raw: %08x%08x%08x", fmtLen, cardnum, code1, rawHi2, rawHi, rawLo);
919 }
920 }
921 if (findone){
922 if (ledcontrol) LED_A_OFF();
923 return;
924 }
925 // reset
926 }
927 idx = 0;
928 WDT_HIT();
929 }
930 DbpString("Stopped");
931 if (ledcontrol) LED_A_OFF();
932}
933
e09f21fa 934void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
935{
e0165dcf 936 uint8_t *dest = BigBuf_get_addr();
937
938 size_t size=0, idx=0;
939 int clk=0, invert=0, errCnt=0, maxErr=20;
940 uint32_t hi=0;
941 uint64_t lo=0;
942 // Configure to go in 125Khz listen mode
943 LFSetupFPGAForADC(95, true);
944
945 while(!BUTTON_PRESS()) {
946
947 WDT_HIT();
948 if (ledcontrol) LED_A_ON();
949
950 DoAcquisition_default(-1,true);
951 size = BigBuf_max_traceLen();
e0165dcf 952 //askdemod and manchester decode
2eec55c8 953 if (size > 16385) size = 16385; //big enough to catch 2 sequences of largest format
fef74fdc 954 errCnt = askdemod(dest, &size, &clk, &invert, maxErr, 0, 1);
e0165dcf 955 WDT_HIT();
956
2eec55c8 957 if (errCnt<0) continue;
958
959 errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
960 if (errCnt){
961 if (size>64){
962 Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
963 hi,
964 (uint32_t)(lo>>32),
965 (uint32_t)lo,
966 (uint32_t)(lo&0xFFFF),
967 (uint32_t)((lo>>16LL) & 0xFF),
968 (uint32_t)(lo & 0xFFFFFF));
969 } else {
970 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
971 (uint32_t)(lo>>32),
972 (uint32_t)lo,
973 (uint32_t)(lo&0xFFFF),
974 (uint32_t)((lo>>16LL) & 0xFF),
975 (uint32_t)(lo & 0xFFFFFF));
e0165dcf 976 }
2eec55c8 977
e0165dcf 978 if (findone){
979 if (ledcontrol) LED_A_OFF();
980 *high=lo>>32;
981 *low=lo & 0xFFFFFFFF;
982 return;
983 }
e0165dcf 984 }
985 WDT_HIT();
2eec55c8 986 hi = lo = size = idx = 0;
987 clk = invert = errCnt = 0;
e0165dcf 988 }
989 DbpString("Stopped");
990 if (ledcontrol) LED_A_OFF();
e09f21fa 991}
992
993void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
994{
e0165dcf 995 uint8_t *dest = BigBuf_get_addr();
996 int idx=0;
997 uint32_t code=0, code2=0;
998 uint8_t version=0;
999 uint8_t facilitycode=0;
1000 uint16_t number=0;
1001 // Configure to go in 125Khz listen mode
1002 LFSetupFPGAForADC(95, true);
1003
1004 while(!BUTTON_PRESS()) {
1005 WDT_HIT();
1006 if (ledcontrol) LED_A_ON();
e09f21fa 1007 DoAcquisition_default(-1,true);
1008 //fskdemod and get start index
e0165dcf 1009 WDT_HIT();
1010 idx = IOdemodFSK(dest, BigBuf_max_traceLen());
2eec55c8 1011 if (idx<0) continue;
1012 //valid tag found
1013
1014 //Index map
1015 //0 10 20 30 40 50 60
1016 //| | | | | | |
1017 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
1018 //-----------------------------------------------------------------------------
1019 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
1020 //
1021 //XSF(version)facility:codeone+codetwo
1022 //Handle the data
1023 if(findone){ //only print binary if we are doing one
1024 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
1025 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
1026 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
1027 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
1028 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
1029 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
1030 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
1031 }
1032 code = bytebits_to_byte(dest+idx,32);
1033 code2 = bytebits_to_byte(dest+idx+32,32);
1034 version = bytebits_to_byte(dest+idx+27,8); //14,4
1035 facilitycode = bytebits_to_byte(dest+idx+18,8);
1036 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
1037
1038 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
1039 // if we're only looking for one tag
1040 if (findone){
1041 if (ledcontrol) LED_A_OFF();
1042 //LED_A_OFF();
1043 *high=code;
1044 *low=code2;
1045 return;
e0165dcf 1046 }
2eec55c8 1047 code=code2=0;
1048 version=facilitycode=0;
1049 number=0;
1050 idx=0;
1051
e0165dcf 1052 WDT_HIT();
1053 }
1054 DbpString("Stopped");
1055 if (ledcontrol) LED_A_OFF();
e09f21fa 1056}
1057
1058/*------------------------------
1059 * T5555/T5557/T5567 routines
1060 *------------------------------
1061 */
1062
1063/* T55x7 configuration register definitions */
1064#define T55x7_POR_DELAY 0x00000001
1065#define T55x7_ST_TERMINATOR 0x00000008
1066#define T55x7_PWD 0x00000010
1067#define T55x7_MAXBLOCK_SHIFT 5
1068#define T55x7_AOR 0x00000200
1069#define T55x7_PSKCF_RF_2 0
1070#define T55x7_PSKCF_RF_4 0x00000400
1071#define T55x7_PSKCF_RF_8 0x00000800
1072#define T55x7_MODULATION_DIRECT 0
1073#define T55x7_MODULATION_PSK1 0x00001000
1074#define T55x7_MODULATION_PSK2 0x00002000
1075#define T55x7_MODULATION_PSK3 0x00003000
1076#define T55x7_MODULATION_FSK1 0x00004000
1077#define T55x7_MODULATION_FSK2 0x00005000
1078#define T55x7_MODULATION_FSK1a 0x00006000
1079#define T55x7_MODULATION_FSK2a 0x00007000
1080#define T55x7_MODULATION_MANCHESTER 0x00008000
1081#define T55x7_MODULATION_BIPHASE 0x00010000
1082#define T55x7_BITRATE_RF_8 0
1083#define T55x7_BITRATE_RF_16 0x00040000
1084#define T55x7_BITRATE_RF_32 0x00080000
1085#define T55x7_BITRATE_RF_40 0x000C0000
1086#define T55x7_BITRATE_RF_50 0x00100000
1087#define T55x7_BITRATE_RF_64 0x00140000
1088#define T55x7_BITRATE_RF_100 0x00180000
1089#define T55x7_BITRATE_RF_128 0x001C0000
1090
1091/* T5555 (Q5) configuration register definitions */
1092#define T5555_ST_TERMINATOR 0x00000001
1093#define T5555_MAXBLOCK_SHIFT 0x00000001
1094#define T5555_MODULATION_MANCHESTER 0
1095#define T5555_MODULATION_PSK1 0x00000010
1096#define T5555_MODULATION_PSK2 0x00000020
1097#define T5555_MODULATION_PSK3 0x00000030
1098#define T5555_MODULATION_FSK1 0x00000040
1099#define T5555_MODULATION_FSK2 0x00000050
1100#define T5555_MODULATION_BIPHASE 0x00000060
1101#define T5555_MODULATION_DIRECT 0x00000070
1102#define T5555_INVERT_OUTPUT 0x00000080
1103#define T5555_PSK_RF_2 0
1104#define T5555_PSK_RF_4 0x00000100
1105#define T5555_PSK_RF_8 0x00000200
1106#define T5555_USE_PWD 0x00000400
1107#define T5555_USE_AOR 0x00000800
1108#define T5555_BITRATE_SHIFT 12
1109#define T5555_FAST_WRITE 0x00004000
1110#define T5555_PAGE_SELECT 0x00008000
1111
1112/*
1113 * Relevant times in microsecond
1114 * To compensate antenna falling times shorten the write times
1115 * and enlarge the gap ones.
1116 */
4a3f1a37 1117#define START_GAP 31*8 // was 250 // SPEC: 1*8 to 50*8 - typ 15*8 (or 15fc)
1118#define WRITE_GAP 20*8 // was 160 // SPEC: 1*8 to 20*8 - typ 10*8 (or 10fc)
1119#define WRITE_0 18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
1120#define WRITE_1 50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc) 432 for T55x7; 448 for E5550
13d77ef9 1121
1122#define T55xx_SAMPLES_SIZE 12000 // 32 x 32 x 10 (32 bit times numofblock (7), times clock skip..)
e09f21fa 1123
1124// Write one bit to card
1125void T55xxWriteBit(int bit)
1126{
e0165dcf 1127 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1128 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1129 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1130 if (bit == 0)
1131 SpinDelayUs(WRITE_0);
1132 else
1133 SpinDelayUs(WRITE_1);
1134 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1135 SpinDelayUs(WRITE_GAP);
e09f21fa 1136}
1137
1138// Write one card block in page 0, no lock
1139void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1140{
e0165dcf 1141 uint32_t i = 0;
1142
1143 // Set up FPGA, 125kHz
1144 // Wait for config.. (192+8190xPOW)x8 == 67ms
1145 LFSetupFPGAForADC(0, true);
1146
1147 // Now start writting
1148 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1149 SpinDelayUs(START_GAP);
1150
1151 // Opcode
1152 T55xxWriteBit(1);
1153 T55xxWriteBit(0); //Page 0
1154 if (PwdMode == 1){
1155 // Pwd
1156 for (i = 0x80000000; i != 0; i >>= 1)
1157 T55xxWriteBit(Pwd & i);
1158 }
1159 // Lock bit
1160 T55xxWriteBit(0);
1161
1162 // Data
1163 for (i = 0x80000000; i != 0; i >>= 1)
1164 T55xxWriteBit(Data & i);
1165
1166 // Block
1167 for (i = 0x04; i != 0; i >>= 1)
1168 T55xxWriteBit(Block & i);
1169
1170 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1171 // so wait a little more)
1172 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1173 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1174 SpinDelay(20);
1175 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
e09f21fa 1176}
1177
13d77ef9 1178void TurnReadLFOn(){
e0165dcf 1179 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1180 // Give it a bit of time for the resonant antenna to settle.
1181 SpinDelayUs(8*150);
13d77ef9 1182}
1183
1184
e09f21fa 1185// Read one card block in page 0
1186void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1187{
e0165dcf 1188 uint32_t i = 0;
1189 uint8_t *dest = BigBuf_get_addr();
1190 uint16_t bufferlength = BigBuf_max_traceLen();
1191 if ( bufferlength > T55xx_SAMPLES_SIZE )
1192 bufferlength = T55xx_SAMPLES_SIZE;
1193
1194 // Clear destination buffer before sending the command
1195 memset(dest, 0x80, bufferlength);
1196
1197 // Set up FPGA, 125kHz
1198 // Wait for config.. (192+8190xPOW)x8 == 67ms
1199 LFSetupFPGAForADC(0, true);
1200 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1201 SpinDelayUs(START_GAP);
1202
1203 // Opcode
1204 T55xxWriteBit(1);
1205 T55xxWriteBit(0); //Page 0
1206 if (PwdMode == 1){
1207 // Pwd
1208 for (i = 0x80000000; i != 0; i >>= 1)
1209 T55xxWriteBit(Pwd & i);
1210 }
1211 // Lock bit
1212 T55xxWriteBit(0);
1213 // Block
1214 for (i = 0x04; i != 0; i >>= 1)
1215 T55xxWriteBit(Block & i);
1216
1217 // Turn field on to read the response
1218 TurnReadLFOn();
1219 // Now do the acquisition
1220 i = 0;
1221 for(;;) {
1222 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1223 AT91C_BASE_SSC->SSC_THR = 0x43;
1224 LED_D_ON();
1225 }
1226 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1227 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1228 i++;
1229 LED_D_OFF();
1230 if (i >= bufferlength) break;
1231 }
1232 }
1233
1234 cmd_send(CMD_ACK,0,0,0,0,0);
1235 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1236 LED_D_OFF();
e09f21fa 1237}
1238
1239// Read card traceability data (page 1)
1240void T55xxReadTrace(void){
e0165dcf 1241
1242 uint32_t i = 0;
1243 uint8_t *dest = BigBuf_get_addr();
1244 uint16_t bufferlength = BigBuf_max_traceLen();
1245 if ( bufferlength > T55xx_SAMPLES_SIZE )
1246 bufferlength= T55xx_SAMPLES_SIZE;
1247
1248 // Clear destination buffer before sending the command
1249 memset(dest, 0x80, bufferlength);
1250
1251 LFSetupFPGAForADC(0, true);
1252 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1253 SpinDelayUs(START_GAP);
1254
1255 // Opcode
1256 T55xxWriteBit(1);
1257 T55xxWriteBit(1); //Page 1
1258
1259 // Turn field on to read the response
1260 TurnReadLFOn();
1261
1262 // Now do the acquisition
1263 for(;;) {
1264 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1265 AT91C_BASE_SSC->SSC_THR = 0x43;
1266 LED_D_ON();
1267 }
1268 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1269 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1270 i++;
1271 LED_D_OFF();
1272
1273 if (i >= bufferlength) break;
1274 }
1275 }
1276
1277 cmd_send(CMD_ACK,0,0,0,0,0);
1278 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1279 LED_D_OFF();
e09f21fa 1280}
1281
1282/*-------------- Cloning routines -----------*/
1283// Copy HID id to card and setup block 0 config
1284void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1285{
e0165dcf 1286 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1287 int last_block = 0;
1288
1289 if (longFMT){
1290 // Ensure no more than 84 bits supplied
1291 if (hi2>0xFFFFF) {
1292 DbpString("Tags can only have 84 bits.");
1293 return;
1294 }
1295 // Build the 6 data blocks for supplied 84bit ID
1296 last_block = 6;
1297 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1298 for (int i=0;i<4;i++) {
1299 if (hi2 & (1<<(19-i)))
1300 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1301 else
1302 data1 |= (1<<((3-i)*2)); // 0 -> 01
1303 }
1304
1305 data2 = 0;
1306 for (int i=0;i<16;i++) {
1307 if (hi2 & (1<<(15-i)))
1308 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1309 else
1310 data2 |= (1<<((15-i)*2)); // 0 -> 01
1311 }
1312
1313 data3 = 0;
1314 for (int i=0;i<16;i++) {
1315 if (hi & (1<<(31-i)))
1316 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1317 else
1318 data3 |= (1<<((15-i)*2)); // 0 -> 01
1319 }
1320
1321 data4 = 0;
1322 for (int i=0;i<16;i++) {
1323 if (hi & (1<<(15-i)))
1324 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1325 else
1326 data4 |= (1<<((15-i)*2)); // 0 -> 01
1327 }
1328
1329 data5 = 0;
1330 for (int i=0;i<16;i++) {
1331 if (lo & (1<<(31-i)))
1332 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1333 else
1334 data5 |= (1<<((15-i)*2)); // 0 -> 01
1335 }
1336
1337 data6 = 0;
1338 for (int i=0;i<16;i++) {
1339 if (lo & (1<<(15-i)))
1340 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1341 else
1342 data6 |= (1<<((15-i)*2)); // 0 -> 01
1343 }
1344 }
1345 else {
1346 // Ensure no more than 44 bits supplied
1347 if (hi>0xFFF) {
1348 DbpString("Tags can only have 44 bits.");
1349 return;
1350 }
1351
1352 // Build the 3 data blocks for supplied 44bit ID
1353 last_block = 3;
1354
1355 data1 = 0x1D000000; // load preamble
1356
1357 for (int i=0;i<12;i++) {
1358 if (hi & (1<<(11-i)))
1359 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1360 else
1361 data1 |= (1<<((11-i)*2)); // 0 -> 01
1362 }
1363
1364 data2 = 0;
1365 for (int i=0;i<16;i++) {
1366 if (lo & (1<<(31-i)))
1367 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1368 else
1369 data2 |= (1<<((15-i)*2)); // 0 -> 01
1370 }
1371
1372 data3 = 0;
1373 for (int i=0;i<16;i++) {
1374 if (lo & (1<<(15-i)))
1375 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1376 else
1377 data3 |= (1<<((15-i)*2)); // 0 -> 01
1378 }
1379 }
1380
1381 LED_D_ON();
1382 // Program the data blocks for supplied ID
1383 // and the block 0 for HID format
1384 T55xxWriteBlock(data1,1,0,0);
1385 T55xxWriteBlock(data2,2,0,0);
1386 T55xxWriteBlock(data3,3,0,0);
1387
1388 if (longFMT) { // if long format there are 6 blocks
1389 T55xxWriteBlock(data4,4,0,0);
1390 T55xxWriteBlock(data5,5,0,0);
1391 T55xxWriteBlock(data6,6,0,0);
1392 }
1393
1394 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1395 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1396 T55x7_MODULATION_FSK2a |
1397 last_block << T55x7_MAXBLOCK_SHIFT,
1398 0,0,0);
1399
1400 LED_D_OFF();
1401
1402 DbpString("DONE!");
e09f21fa 1403}
1404
1405void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1406{
e0165dcf 1407 int data1=0, data2=0; //up to six blocks for long format
e09f21fa 1408
e0165dcf 1409 data1 = hi; // load preamble
1410 data2 = lo;
e09f21fa 1411
e0165dcf 1412 LED_D_ON();
1413 // Program the data blocks for supplied ID
1414 // and the block 0 for HID format
1415 T55xxWriteBlock(data1,1,0,0);
1416 T55xxWriteBlock(data2,2,0,0);
e09f21fa 1417
e0165dcf 1418 //Config Block
1419 T55xxWriteBlock(0x00147040,0,0,0);
1420 LED_D_OFF();
e09f21fa 1421
e0165dcf 1422 DbpString("DONE!");
e09f21fa 1423}
1424
1425// Define 9bit header for EM410x tags
1426#define EM410X_HEADER 0x1FF
1427#define EM410X_ID_LENGTH 40
1428
1429void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1430{
e0165dcf 1431 int i, id_bit;
1432 uint64_t id = EM410X_HEADER;
1433 uint64_t rev_id = 0; // reversed ID
1434 int c_parity[4]; // column parity
1435 int r_parity = 0; // row parity
1436 uint32_t clock = 0;
1437
1438 // Reverse ID bits given as parameter (for simpler operations)
1439 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1440 if (i < 32) {
1441 rev_id = (rev_id << 1) | (id_lo & 1);
1442 id_lo >>= 1;
1443 } else {
1444 rev_id = (rev_id << 1) | (id_hi & 1);
1445 id_hi >>= 1;
1446 }
1447 }
1448
1449 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1450 id_bit = rev_id & 1;
1451
1452 if (i % 4 == 0) {
1453 // Don't write row parity bit at start of parsing
1454 if (i)
1455 id = (id << 1) | r_parity;
1456 // Start counting parity for new row
1457 r_parity = id_bit;
1458 } else {
1459 // Count row parity
1460 r_parity ^= id_bit;
1461 }
1462
1463 // First elements in column?
1464 if (i < 4)
1465 // Fill out first elements
1466 c_parity[i] = id_bit;
1467 else
1468 // Count column parity
1469 c_parity[i % 4] ^= id_bit;
1470
1471 // Insert ID bit
1472 id = (id << 1) | id_bit;
1473 rev_id >>= 1;
1474 }
1475
1476 // Insert parity bit of last row
1477 id = (id << 1) | r_parity;
1478
1479 // Fill out column parity at the end of tag
1480 for (i = 0; i < 4; ++i)
1481 id = (id << 1) | c_parity[i];
1482
1483 // Add stop bit
1484 id <<= 1;
1485
1486 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1487 LED_D_ON();
1488
1489 // Write EM410x ID
1490 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1491 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1492
1493 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1494 if (card) {
1495 // Clock rate is stored in bits 8-15 of the card value
1496 clock = (card & 0xFF00) >> 8;
1497 Dbprintf("Clock rate: %d", clock);
1498 switch (clock)
1499 {
1500 case 32:
1501 clock = T55x7_BITRATE_RF_32;
1502 break;
1503 case 16:
1504 clock = T55x7_BITRATE_RF_16;
1505 break;
1506 case 0:
1507 // A value of 0 is assumed to be 64 for backwards-compatibility
1508 // Fall through...
1509 case 64:
1510 clock = T55x7_BITRATE_RF_64;
1511 break;
1512 default:
1513 Dbprintf("Invalid clock rate: %d", clock);
1514 return;
1515 }
1516
1517 // Writing configuration for T55x7 tag
1518 T55xxWriteBlock(clock |
1519 T55x7_MODULATION_MANCHESTER |
1520 2 << T55x7_MAXBLOCK_SHIFT,
1521 0, 0, 0);
1522 }
1523 else
1524 // Writing configuration for T5555(Q5) tag
1525 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1526 T5555_MODULATION_MANCHESTER |
1527 2 << T5555_MAXBLOCK_SHIFT,
1528 0, 0, 0);
1529
1530 LED_D_OFF();
1531 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1532 (uint32_t)(id >> 32), (uint32_t)id);
e09f21fa 1533}
1534
1535// Clone Indala 64-bit tag by UID to T55x7
1536void CopyIndala64toT55x7(int hi, int lo)
1537{
1538
e0165dcf 1539 //Program the 2 data blocks for supplied 64bit UID
1540 // and the block 0 for Indala64 format
1541 T55xxWriteBlock(hi,1,0,0);
1542 T55xxWriteBlock(lo,2,0,0);
1543 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1544 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1545 T55x7_MODULATION_PSK1 |
1546 2 << T55x7_MAXBLOCK_SHIFT,
1547 0, 0, 0);
1548 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1549 // T5567WriteBlock(0x603E1042,0);
e09f21fa 1550
e0165dcf 1551 DbpString("DONE!");
e09f21fa 1552
1553}
1554
1555void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1556{
1557
e0165dcf 1558 //Program the 7 data blocks for supplied 224bit UID
1559 // and the block 0 for Indala224 format
1560 T55xxWriteBlock(uid1,1,0,0);
1561 T55xxWriteBlock(uid2,2,0,0);
1562 T55xxWriteBlock(uid3,3,0,0);
1563 T55xxWriteBlock(uid4,4,0,0);
1564 T55xxWriteBlock(uid5,5,0,0);
1565 T55xxWriteBlock(uid6,6,0,0);
1566 T55xxWriteBlock(uid7,7,0,0);
1567 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1568 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1569 T55x7_MODULATION_PSK1 |
1570 7 << T55x7_MAXBLOCK_SHIFT,
1571 0,0,0);
1572 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1573 // T5567WriteBlock(0x603E10E2,0);
1574
1575 DbpString("DONE!");
e09f21fa 1576
1577}
1578
1579
1580#define abs(x) ( ((x)<0) ? -(x) : (x) )
1581#define max(x,y) ( x<y ? y:x)
1582
1583int DemodPCF7931(uint8_t **outBlocks) {
e0165dcf 1584 uint8_t BitStream[256];
1585 uint8_t Blocks[8][16];
1586 uint8_t *GraphBuffer = BigBuf_get_addr();
1587 int GraphTraceLen = BigBuf_max_traceLen();
1588 int i, j, lastval, bitidx, half_switch;
1589 int clock = 64;
1590 int tolerance = clock / 8;
1591 int pmc, block_done;
1592 int lc, warnings = 0;
1593 int num_blocks = 0;
1594 int lmin=128, lmax=128;
1595 uint8_t dir;
e09f21fa 1596
1597 LFSetupFPGAForADC(95, true);
1598 DoAcquisition_default(0, 0);
1599
1600
e0165dcf 1601 lmin = 64;
1602 lmax = 192;
1603
1604 i = 2;
1605
1606 /* Find first local max/min */
1607 if(GraphBuffer[1] > GraphBuffer[0]) {
1608 while(i < GraphTraceLen) {
1609 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1610 break;
1611 i++;
1612 }
1613 dir = 0;
1614 }
1615 else {
1616 while(i < GraphTraceLen) {
1617 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1618 break;
1619 i++;
1620 }
1621 dir = 1;
1622 }
1623
1624 lastval = i++;
1625 half_switch = 0;
1626 pmc = 0;
1627 block_done = 0;
1628
1629 for (bitidx = 0; i < GraphTraceLen; i++)
1630 {
1631 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1632 {
1633 lc = i - lastval;
1634 lastval = i;
1635
1636 // Switch depending on lc length:
1637 // Tolerance is 1/8 of clock rate (arbitrary)
1638 if (abs(lc-clock/4) < tolerance) {
1639 // 16T0
1640 if((i - pmc) == lc) { /* 16T0 was previous one */
1641 /* It's a PMC ! */
1642 i += (128+127+16+32+33+16)-1;
1643 lastval = i;
1644 pmc = 0;
1645 block_done = 1;
1646 }
1647 else {
1648 pmc = i;
1649 }
1650 } else if (abs(lc-clock/2) < tolerance) {
1651 // 32TO
1652 if((i - pmc) == lc) { /* 16T0 was previous one */
1653 /* It's a PMC ! */
1654 i += (128+127+16+32+33)-1;
1655 lastval = i;
1656 pmc = 0;
1657 block_done = 1;
1658 }
1659 else if(half_switch == 1) {
1660 BitStream[bitidx++] = 0;
1661 half_switch = 0;
1662 }
1663 else
1664 half_switch++;
1665 } else if (abs(lc-clock) < tolerance) {
1666 // 64TO
1667 BitStream[bitidx++] = 1;
1668 } else {
1669 // Error
1670 warnings++;
1671 if (warnings > 10)
1672 {
1673 Dbprintf("Error: too many detection errors, aborting.");
1674 return 0;
1675 }
1676 }
1677
1678 if(block_done == 1) {
1679 if(bitidx == 128) {
1680 for(j=0; j<16; j++) {
1681 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1682 64*BitStream[j*8+6]+
1683 32*BitStream[j*8+5]+
1684 16*BitStream[j*8+4]+
1685 8*BitStream[j*8+3]+
1686 4*BitStream[j*8+2]+
1687 2*BitStream[j*8+1]+
1688 BitStream[j*8];
1689 }
1690 num_blocks++;
1691 }
1692 bitidx = 0;
1693 block_done = 0;
1694 half_switch = 0;
1695 }
1696 if(i < GraphTraceLen)
1697 {
1698 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1699 else dir = 1;
1700 }
1701 }
1702 if(bitidx==255)
1703 bitidx=0;
1704 warnings = 0;
1705 if(num_blocks == 4) break;
1706 }
1707 memcpy(outBlocks, Blocks, 16*num_blocks);
1708 return num_blocks;
e09f21fa 1709}
1710
1711int IsBlock0PCF7931(uint8_t *Block) {
e0165dcf 1712 // Assume RFU means 0 :)
1713 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1714 return 1;
1715 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1716 return 1;
1717 return 0;
e09f21fa 1718}
1719
1720int IsBlock1PCF7931(uint8_t *Block) {
e0165dcf 1721 // Assume RFU means 0 :)
1722 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1723 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1724 return 1;
e09f21fa 1725
e0165dcf 1726 return 0;
e09f21fa 1727}
1728
1729#define ALLOC 16
1730
1731void ReadPCF7931() {
e0165dcf 1732 uint8_t Blocks[8][17];
1733 uint8_t tmpBlocks[4][16];
1734 int i, j, ind, ind2, n;
1735 int num_blocks = 0;
1736 int max_blocks = 8;
1737 int ident = 0;
1738 int error = 0;
1739 int tries = 0;
1740
1741 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1742
1743 do {
1744 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1745 n = DemodPCF7931((uint8_t**)tmpBlocks);
1746 if(!n)
1747 error++;
1748 if(error==10 && num_blocks == 0) {
1749 Dbprintf("Error, no tag or bad tag");
1750 return;
1751 }
1752 else if (tries==20 || error==10) {
1753 Dbprintf("Error reading the tag");
1754 Dbprintf("Here is the partial content");
1755 goto end;
1756 }
1757
1758 for(i=0; i<n; i++)
1759 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1760 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1761 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1762 if(!ident) {
1763 for(i=0; i<n; i++) {
1764 if(IsBlock0PCF7931(tmpBlocks[i])) {
1765 // Found block 0 ?
1766 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1767 // Found block 1!
1768 // \o/
1769 ident = 1;
1770 memcpy(Blocks[0], tmpBlocks[i], 16);
1771 Blocks[0][ALLOC] = 1;
1772 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1773 Blocks[1][ALLOC] = 1;
1774 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1775 // Debug print
1776 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1777 num_blocks = 2;
1778 // Handle following blocks
1779 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1780 if(j==n) j=0;
1781 if(j==i) break;
1782 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1783 Blocks[ind2][ALLOC] = 1;
1784 }
1785 break;
1786 }
1787 }
1788 }
1789 }
1790 else {
1791 for(i=0; i<n; i++) { // Look for identical block in known blocks
1792 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1793 for(j=0; j<max_blocks; j++) {
1794 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1795 // Found an identical block
1796 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1797 if(ind2 < 0)
1798 ind2 = max_blocks;
1799 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1800 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1801 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1802 Blocks[ind2][ALLOC] = 1;
1803 num_blocks++;
1804 if(num_blocks == max_blocks) goto end;
1805 }
1806 }
1807 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1808 if(ind2 > max_blocks)
1809 ind2 = 0;
1810 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1811 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1812 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1813 Blocks[ind2][ALLOC] = 1;
1814 num_blocks++;
1815 if(num_blocks == max_blocks) goto end;
1816 }
1817 }
1818 }
1819 }
1820 }
1821 }
1822 }
1823 tries++;
1824 if (BUTTON_PRESS()) return;
1825 } while (num_blocks != max_blocks);
e09f21fa 1826 end:
e0165dcf 1827 Dbprintf("-----------------------------------------");
1828 Dbprintf("Memory content:");
1829 Dbprintf("-----------------------------------------");
1830 for(i=0; i<max_blocks; i++) {
1831 if(Blocks[i][ALLOC]==1)
1832 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1833 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1834 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1835 else
1836 Dbprintf("<missing block %d>", i);
1837 }
1838 Dbprintf("-----------------------------------------");
1839
1840 return ;
e09f21fa 1841}
1842
1843
1844//-----------------------------------
1845// EM4469 / EM4305 routines
1846//-----------------------------------
1847#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1848#define FWD_CMD_WRITE 0xA
1849#define FWD_CMD_READ 0x9
1850#define FWD_CMD_DISABLE 0x5
1851
1852
1853uint8_t forwardLink_data[64]; //array of forwarded bits
1854uint8_t * forward_ptr; //ptr for forward message preparation
1855uint8_t fwd_bit_sz; //forwardlink bit counter
1856uint8_t * fwd_write_ptr; //forwardlink bit pointer
1857
1858//====================================================================
1859// prepares command bits
1860// see EM4469 spec
1861//====================================================================
1862//--------------------------------------------------------------------
1863uint8_t Prepare_Cmd( uint8_t cmd ) {
e0165dcf 1864 //--------------------------------------------------------------------
e09f21fa 1865
e0165dcf 1866 *forward_ptr++ = 0; //start bit
1867 *forward_ptr++ = 0; //second pause for 4050 code
e09f21fa 1868
e0165dcf 1869 *forward_ptr++ = cmd;
1870 cmd >>= 1;
1871 *forward_ptr++ = cmd;
1872 cmd >>= 1;
1873 *forward_ptr++ = cmd;
1874 cmd >>= 1;
1875 *forward_ptr++ = cmd;
e09f21fa 1876
e0165dcf 1877 return 6; //return number of emited bits
e09f21fa 1878}
1879
1880//====================================================================
1881// prepares address bits
1882// see EM4469 spec
1883//====================================================================
1884
1885//--------------------------------------------------------------------
1886uint8_t Prepare_Addr( uint8_t addr ) {
e0165dcf 1887 //--------------------------------------------------------------------
e09f21fa 1888
e0165dcf 1889 register uint8_t line_parity;
e09f21fa 1890
e0165dcf 1891 uint8_t i;
1892 line_parity = 0;
1893 for(i=0;i<6;i++) {
1894 *forward_ptr++ = addr;
1895 line_parity ^= addr;
1896 addr >>= 1;
1897 }
e09f21fa 1898
e0165dcf 1899 *forward_ptr++ = (line_parity & 1);
e09f21fa 1900
e0165dcf 1901 return 7; //return number of emited bits
e09f21fa 1902}
1903
1904//====================================================================
1905// prepares data bits intreleaved with parity bits
1906// see EM4469 spec
1907//====================================================================
1908
1909//--------------------------------------------------------------------
1910uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
e0165dcf 1911 //--------------------------------------------------------------------
1912
1913 register uint8_t line_parity;
1914 register uint8_t column_parity;
1915 register uint8_t i, j;
1916 register uint16_t data;
1917
1918 data = data_low;
1919 column_parity = 0;
1920
1921 for(i=0; i<4; i++) {
1922 line_parity = 0;
1923 for(j=0; j<8; j++) {
1924 line_parity ^= data;
1925 column_parity ^= (data & 1) << j;
1926 *forward_ptr++ = data;
1927 data >>= 1;
1928 }
1929 *forward_ptr++ = line_parity;
1930 if(i == 1)
1931 data = data_hi;
1932 }
1933
1934 for(j=0; j<8; j++) {
1935 *forward_ptr++ = column_parity;
1936 column_parity >>= 1;
1937 }
1938 *forward_ptr = 0;
1939
1940 return 45; //return number of emited bits
e09f21fa 1941}
1942
1943//====================================================================
1944// Forward Link send function
1945// Requires: forwarLink_data filled with valid bits (1 bit per byte)
1946// fwd_bit_count set with number of bits to be sent
1947//====================================================================
1948void SendForward(uint8_t fwd_bit_count) {
1949
e0165dcf 1950 fwd_write_ptr = forwardLink_data;
1951 fwd_bit_sz = fwd_bit_count;
1952
1953 LED_D_ON();
1954
1955 //Field on
1956 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1957 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1958 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1959
1960 // Give it a bit of time for the resonant antenna to settle.
1961 // And for the tag to fully power up
1962 SpinDelay(150);
1963
1964 // force 1st mod pulse (start gap must be longer for 4305)
1965 fwd_bit_sz--; //prepare next bit modulation
1966 fwd_write_ptr++;
1967 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1968 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1969 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1970 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1971 SpinDelayUs(16*8); //16 cycles on (8us each)
1972
1973 // now start writting
1974 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1975 if(((*fwd_write_ptr++) & 1) == 1)
1976 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1977 else {
1978 //These timings work for 4469/4269/4305 (with the 55*8 above)
1979 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1980 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1981 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1982 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1983 SpinDelayUs(9*8); //16 cycles on (8us each)
1984 }
1985 }
e09f21fa 1986}
1987
1988void EM4xLogin(uint32_t Password) {
1989
e0165dcf 1990 uint8_t fwd_bit_count;
e09f21fa 1991
e0165dcf 1992 forward_ptr = forwardLink_data;
1993 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1994 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
e09f21fa 1995
e0165dcf 1996 SendForward(fwd_bit_count);
e09f21fa 1997
e0165dcf 1998 //Wait for command to complete
1999 SpinDelay(20);
e09f21fa 2000
2001}
2002
2003void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2004
e0165dcf 2005 uint8_t fwd_bit_count;
2006 uint8_t *dest = BigBuf_get_addr();
2007 int m=0, i=0;
2008
2009 //If password mode do login
2010 if (PwdMode == 1) EM4xLogin(Pwd);
2011
2012 forward_ptr = forwardLink_data;
2013 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
2014 fwd_bit_count += Prepare_Addr( Address );
2015
2016 m = BigBuf_max_traceLen();
2017 // Clear destination buffer before sending the command
2018 memset(dest, 128, m);
2019 // Connect the A/D to the peak-detected low-frequency path.
2020 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
2021 // Now set up the SSC to get the ADC samples that are now streaming at us.
2022 FpgaSetupSsc();
2023
2024 SendForward(fwd_bit_count);
2025
2026 // Now do the acquisition
2027 i = 0;
2028 for(;;) {
2029 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
2030 AT91C_BASE_SSC->SSC_THR = 0x43;
2031 }
2032 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
2033 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
2034 i++;
2035 if (i >= m) break;
2036 }
2037 }
2038 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2039 LED_D_OFF();
e09f21fa 2040}
2041
2042void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
2043
e0165dcf 2044 uint8_t fwd_bit_count;
e09f21fa 2045
e0165dcf 2046 //If password mode do login
2047 if (PwdMode == 1) EM4xLogin(Pwd);
e09f21fa 2048
e0165dcf 2049 forward_ptr = forwardLink_data;
2050 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
2051 fwd_bit_count += Prepare_Addr( Address );
2052 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
e09f21fa 2053
e0165dcf 2054 SendForward(fwd_bit_count);
e09f21fa 2055
e0165dcf 2056 //Wait for write to complete
2057 SpinDelay(20);
2058 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
2059 LED_D_OFF();
e09f21fa 2060}
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