]> git.zerfleddert.de Git - proxmark3-svn/blame - armsrc/iso14443a.c
Generic trace pt1: Moved arm-side trace functionality into util-package
[proxmark3-svn] / armsrc / iso14443a.c
CommitLineData
15c4dc5a 1//-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
e30c654b 13#include "proxmark3.h"
15c4dc5a 14#include "apps.h"
f7e3ed82 15#include "util.h"
9ab7a6c7 16#include "string.h"
902cb3c0 17#include "cmd.h"
9ab7a6c7 18
15c4dc5a 19#include "iso14443crc.h"
534983d7 20#include "iso14443a.h"
20f9a2a1
M
21#include "crapto1.h"
22#include "mifareutil.h"
15c4dc5a 23
534983d7 24static uint32_t iso14a_timeout;
d19929cb 25uint8_t *trace = (uint8_t *) BigBuf+TRACE_OFFSET;
1e262141 26int rsamples = 0;
7bc95e2e 27int traceLen = 0;
1e262141 28int tracing = TRUE;
29uint8_t trigger = 0;
b0127e65 30// the block number for the ISO14443-4 PCB
31static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 32
7bc95e2e 33//
34// ISO14443 timing:
35//
36// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
37#define REQUEST_GUARD_TIME (7000/16 + 1)
38// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
39#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
40// bool LastCommandWasRequest = FALSE;
41
42//
43// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
44//
d714d3ef 45// When the PM acts as reader and is receiving tag data, it takes
46// 3 ticks delay in the AD converter
47// 16 ticks until the modulation detector completes and sets curbit
48// 8 ticks until bit_to_arm is assigned from curbit
49// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 50// 4*16 ticks until we measure the time
51// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 52#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 53
54// When the PM acts as a reader and is sending, it takes
55// 4*16 ticks until we can write data to the sending hold register
56// 8*16 ticks until the SHR is transferred to the Sending Shift Register
57// 8 ticks until the first transfer starts
58// 8 ticks later the FPGA samples the data
59// 1 tick to assign mod_sig_coil
60#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
61
62// When the PM acts as tag and is receiving it takes
d714d3ef 63// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 64// 3 ticks for the A/D conversion,
65// 8 ticks on average until the start of the SSC transfer,
66// 8 ticks until the SSC samples the first data
67// 7*16 ticks to complete the transfer from FPGA to ARM
68// 8 ticks until the next ssp_clk rising edge
d714d3ef 69// 4*16 ticks until we measure the time
7bc95e2e 70// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 71#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 72
73// The FPGA will report its internal sending delay in
74uint16_t FpgaSendQueueDelay;
75// the 5 first bits are the number of bits buffered in mod_sig_buf
76// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
77#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
78
79// When the PM acts as tag and is sending, it takes
d714d3ef 80// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 81// 8*16 ticks until the SHR is transferred to the Sending Shift Register
82// 8 ticks until the first transfer starts
83// 8 ticks later the FPGA samples the data
84// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
85// + 1 tick to assign mod_sig_coil
d714d3ef 86#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 87
88// When the PM acts as sniffer and is receiving tag data, it takes
89// 3 ticks A/D conversion
d714d3ef 90// 14 ticks to complete the modulation detection
91// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 92// + the delays in transferring data - which is the same for
93// sniffing reader and tag data and therefore not relevant
d714d3ef 94#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 95
d714d3ef 96// When the PM acts as sniffer and is receiving reader data, it takes
97// 2 ticks delay in analogue RF receiver (for the falling edge of the
98// start bit, which marks the start of the communication)
7bc95e2e 99// 3 ticks A/D conversion
d714d3ef 100// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 101// + the delays in transferring data - which is the same for
102// sniffing reader and tag data and therefore not relevant
d714d3ef 103#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 104
105//variables used for timing purposes:
106//these are in ssp_clk cycles:
6a1f2d82 107static uint32_t NextTransferTime;
108static uint32_t LastTimeProxToAirStart;
109static uint32_t LastProxToAirDuration;
7bc95e2e 110
111
112
8f51ddb0 113// CARD TO READER - manchester
72934aa3 114// Sequence D: 11110000 modulation with subcarrier during first half
115// Sequence E: 00001111 modulation with subcarrier during second half
116// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 117// READER TO CARD - miller
72934aa3 118// Sequence X: 00001100 drop after half a period
119// Sequence Y: 00000000 no drop
120// Sequence Z: 11000000 drop at start
121#define SEC_D 0xf0
122#define SEC_E 0x0f
123#define SEC_F 0x00
124#define SEC_X 0x0c
125#define SEC_Y 0x00
126#define SEC_Z 0xc0
15c4dc5a 127
1e262141 128const uint8_t OddByteParity[256] = {
15c4dc5a 129 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
134 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
135 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
136 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
137 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
142 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
143 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
144 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
145};
146
902cb3c0 147void iso14a_set_trigger(bool enable) {
534983d7 148 trigger = enable;
149}
150
902cb3c0 151void iso14a_clear_trace() {
7bc95e2e 152 memset(trace, 0x44, TRACE_SIZE);
8556b852
M
153 traceLen = 0;
154}
d19929cb 155
902cb3c0 156void iso14a_set_tracing(bool enable) {
8556b852
M
157 tracing = enable;
158}
d19929cb 159
b0127e65 160void iso14a_set_timeout(uint32_t timeout) {
161 iso14a_timeout = timeout;
162}
8556b852 163
15c4dc5a 164//-----------------------------------------------------------------------------
165// Generate the parity value for a byte sequence
e30c654b 166//
15c4dc5a 167//-----------------------------------------------------------------------------
20f9a2a1
M
168byte_t oddparity (const byte_t bt)
169{
5f6d6c90 170 return OddByteParity[bt];
20f9a2a1
M
171}
172
6a1f2d82 173void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
15c4dc5a 174{
6a1f2d82 175 uint16_t paritybit_cnt = 0;
176 uint16_t paritybyte_cnt = 0;
177 uint8_t parityBits = 0;
178
179 for (uint16_t i = 0; i < iLen; i++) {
180 // Generate the parity bits
181 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
182 if (paritybit_cnt == 7) {
183 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
184 parityBits = 0; // and advance to next Parity Byte
185 paritybyte_cnt++;
186 paritybit_cnt = 0;
187 } else {
188 paritybit_cnt++;
189 }
5f6d6c90 190 }
6a1f2d82 191
192 // save remaining parity bits
193 par[paritybyte_cnt] = parityBits;
194
15c4dc5a 195}
196
534983d7 197void AppendCrc14443a(uint8_t* data, int len)
15c4dc5a 198{
5f6d6c90 199 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 200}
201
15c4dc5a 202
7bc95e2e 203//=============================================================================
204// ISO 14443 Type A - Miller decoder
205//=============================================================================
206// Basics:
207// This decoder is used when the PM3 acts as a tag.
208// The reader will generate "pauses" by temporarily switching of the field.
209// At the PM3 antenna we will therefore measure a modulated antenna voltage.
210// The FPGA does a comparison with a threshold and would deliver e.g.:
211// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
212// The Miller decoder needs to identify the following sequences:
213// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
214// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
215// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
216// Note 1: the bitstream may start at any time. We therefore need to sync.
217// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 218//-----------------------------------------------------------------------------
b62a5a84 219static tUart Uart;
15c4dc5a 220
d7aa3739 221// Lookup-Table to decide if 4 raw bits are a modulation.
222// We accept two or three consecutive "0" in any position with the rest "1"
223const bool Mod_Miller_LUT[] = {
224 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
225 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
226};
227#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
228#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
229
7bc95e2e 230void UartReset()
15c4dc5a 231{
7bc95e2e 232 Uart.state = STATE_UNSYNCD;
233 Uart.bitCount = 0;
234 Uart.len = 0; // number of decoded data bytes
6a1f2d82 235 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 236 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 237 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 238 Uart.twoBits = 0x0000; // buffer for 2 Bits
239 Uart.highCnt = 0;
240 Uart.startTime = 0;
241 Uart.endTime = 0;
242}
15c4dc5a 243
6a1f2d82 244void UartInit(uint8_t *data, uint8_t *parity)
245{
246 Uart.output = data;
247 Uart.parity = parity;
248 UartReset();
249}
d714d3ef 250
7bc95e2e 251// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
252static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
253{
15c4dc5a 254
7bc95e2e 255 Uart.twoBits = (Uart.twoBits << 8) | bit;
256
257 if (Uart.state == STATE_UNSYNCD) { // not yet synced
3fe4ff4f 258
7bc95e2e 259 if (Uart.highCnt < 7) { // wait for a stable unmodulated signal
260 if (Uart.twoBits == 0xffff) {
261 Uart.highCnt++;
262 } else {
263 Uart.highCnt = 0;
15c4dc5a 264 }
7bc95e2e 265 } else {
266 Uart.syncBit = 0xFFFF; // not set
267 // look for 00xx1111 (the start bit)
268 if ((Uart.twoBits & 0x6780) == 0x0780) Uart.syncBit = 7;
269 else if ((Uart.twoBits & 0x33C0) == 0x03C0) Uart.syncBit = 6;
270 else if ((Uart.twoBits & 0x19E0) == 0x01E0) Uart.syncBit = 5;
271 else if ((Uart.twoBits & 0x0CF0) == 0x00F0) Uart.syncBit = 4;
272 else if ((Uart.twoBits & 0x0678) == 0x0078) Uart.syncBit = 3;
273 else if ((Uart.twoBits & 0x033C) == 0x003C) Uart.syncBit = 2;
274 else if ((Uart.twoBits & 0x019E) == 0x001E) Uart.syncBit = 1;
275 else if ((Uart.twoBits & 0x00CF) == 0x000F) Uart.syncBit = 0;
276 if (Uart.syncBit != 0xFFFF) {
277 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
278 Uart.startTime -= Uart.syncBit;
d7aa3739 279 Uart.endTime = Uart.startTime;
7bc95e2e 280 Uart.state = STATE_START_OF_COMMUNICATION;
15c4dc5a 281 }
7bc95e2e 282 }
15c4dc5a 283
7bc95e2e 284 } else {
15c4dc5a 285
d7aa3739 286 if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
287 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
288 UartReset();
289 Uart.highCnt = 6;
290 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 291 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
292 UartReset();
293 Uart.highCnt = 6;
294 } else {
295 Uart.bitCount++;
296 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
297 Uart.state = STATE_MILLER_Z;
298 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
299 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
300 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
301 Uart.parityBits <<= 1; // make room for the parity bit
302 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
303 Uart.bitCount = 0;
304 Uart.shiftReg = 0;
6a1f2d82 305 if((Uart.len&0x0007) == 0) { // every 8 data bytes
306 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
307 Uart.parityBits = 0;
308 }
15c4dc5a 309 }
7bc95e2e 310 }
d7aa3739 311 }
312 } else {
313 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 314 Uart.bitCount++;
315 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
316 Uart.state = STATE_MILLER_X;
317 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
318 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
319 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
320 Uart.parityBits <<= 1; // make room for the new parity bit
321 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
322 Uart.bitCount = 0;
323 Uart.shiftReg = 0;
6a1f2d82 324 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
325 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
326 Uart.parityBits = 0;
327 }
7bc95e2e 328 }
d7aa3739 329 } else { // no modulation in both halves - Sequence Y
7bc95e2e 330 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 331 Uart.state = STATE_UNSYNCD;
6a1f2d82 332 Uart.bitCount--; // last "0" was part of EOC sequence
333 Uart.shiftReg <<= 1; // drop it
334 if(Uart.bitCount > 0) { // if we decoded some bits
335 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
336 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
337 Uart.parityBits <<= 1; // add a (void) parity bit
338 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
339 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
340 return TRUE;
341 } else if (Uart.len & 0x0007) { // there are some parity bits to store
342 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
343 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 344 }
345 if (Uart.len) {
6a1f2d82 346 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 347 } else {
3fe4ff4f 348 UartReset(); // Nothing receiver - start over
7bc95e2e 349 }
15c4dc5a 350 }
7bc95e2e 351 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
352 UartReset();
353 Uart.highCnt = 6;
354 } else { // a logic "0"
355 Uart.bitCount++;
356 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
357 Uart.state = STATE_MILLER_Y;
358 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
359 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
360 Uart.parityBits <<= 1; // make room for the parity bit
361 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
362 Uart.bitCount = 0;
363 Uart.shiftReg = 0;
6a1f2d82 364 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
365 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
366 Uart.parityBits = 0;
367 }
15c4dc5a 368 }
369 }
d7aa3739 370 }
15c4dc5a 371 }
7bc95e2e 372
373 }
15c4dc5a 374
7bc95e2e 375 return FALSE; // not finished yet, need more data
15c4dc5a 376}
377
7bc95e2e 378
379
15c4dc5a 380//=============================================================================
e691fc45 381// ISO 14443 Type A - Manchester decoder
15c4dc5a 382//=============================================================================
e691fc45 383// Basics:
7bc95e2e 384// This decoder is used when the PM3 acts as a reader.
e691fc45 385// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
386// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
387// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
388// The Manchester decoder needs to identify the following sequences:
389// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
390// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
391// 8 ticks unmodulated: Sequence F = end of communication
392// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 393// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 394// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 395static tDemod Demod;
15c4dc5a 396
d7aa3739 397// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 398// We accept three or four "1" in any position
7bc95e2e 399const bool Mod_Manchester_LUT[] = {
d7aa3739 400 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 401 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 402};
403
404#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
405#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 406
2f2d9fc5 407
7bc95e2e 408void DemodReset()
e691fc45 409{
7bc95e2e 410 Demod.state = DEMOD_UNSYNCD;
411 Demod.len = 0; // number of decoded data bytes
6a1f2d82 412 Demod.parityLen = 0;
7bc95e2e 413 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
414 Demod.parityBits = 0; //
415 Demod.collisionPos = 0; // Position of collision bit
416 Demod.twoBits = 0xffff; // buffer for 2 Bits
417 Demod.highCnt = 0;
418 Demod.startTime = 0;
419 Demod.endTime = 0;
e691fc45 420}
15c4dc5a 421
6a1f2d82 422void DemodInit(uint8_t *data, uint8_t *parity)
423{
424 Demod.output = data;
425 Demod.parity = parity;
426 DemodReset();
427}
428
7bc95e2e 429// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
430static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
e691fc45 431{
7bc95e2e 432
433 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 434
7bc95e2e 435 if (Demod.state == DEMOD_UNSYNCD) {
436
437 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
438 if (Demod.twoBits == 0x0000) {
439 Demod.highCnt++;
440 } else {
441 Demod.highCnt = 0;
442 }
443 } else {
444 Demod.syncBit = 0xFFFF; // not set
445 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
446 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
447 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
448 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
449 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
450 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
451 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
452 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 453 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 454 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
455 Demod.startTime -= Demod.syncBit;
456 Demod.bitCount = offset; // number of decoded data bits
e691fc45 457 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 458 }
7bc95e2e 459 }
15c4dc5a 460
7bc95e2e 461 } else {
15c4dc5a 462
7bc95e2e 463 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
464 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 465 if (!Demod.collisionPos) {
466 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
467 }
468 } // modulation in first half only - Sequence D = 1
7bc95e2e 469 Demod.bitCount++;
470 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
471 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 472 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 473 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 474 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
475 Demod.bitCount = 0;
476 Demod.shiftReg = 0;
6a1f2d82 477 if((Demod.len&0x0007) == 0) { // every 8 data bytes
478 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
479 Demod.parityBits = 0;
480 }
15c4dc5a 481 }
7bc95e2e 482 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
483 } else { // no modulation in first half
484 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 485 Demod.bitCount++;
7bc95e2e 486 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 487 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 488 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 489 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 490 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
491 Demod.bitCount = 0;
492 Demod.shiftReg = 0;
6a1f2d82 493 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
494 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
495 Demod.parityBits = 0;
496 }
15c4dc5a 497 }
7bc95e2e 498 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 499 } else { // no modulation in both halves - End of communication
6a1f2d82 500 if(Demod.bitCount > 0) { // there are some remaining data bits
501 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
502 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
503 Demod.parityBits <<= 1; // add a (void) parity bit
504 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
505 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
506 return TRUE;
507 } else if (Demod.len & 0x0007) { // there are some parity bits to store
508 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
509 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 510 }
511 if (Demod.len) {
d7aa3739 512 return TRUE; // we are finished with decoding the raw data sequence
513 } else { // nothing received. Start over
514 DemodReset();
e691fc45 515 }
15c4dc5a 516 }
7bc95e2e 517 }
e691fc45 518
519 }
15c4dc5a 520
e691fc45 521 return FALSE; // not finished yet, need more data
15c4dc5a 522}
523
524//=============================================================================
525// Finally, a `sniffer' for ISO 14443 Type A
526// Both sides of communication!
527//=============================================================================
528
529//-----------------------------------------------------------------------------
530// Record the sequence of commands sent by the reader to the tag, with
531// triggering so that we start recording at the point that the tag is moved
532// near the reader.
533//-----------------------------------------------------------------------------
5cd9ec01
M
534void RAMFUNC SnoopIso14443a(uint8_t param) {
535 // param:
536 // bit 0 - trigger from first card answer
537 // bit 1 - trigger from first reader 7-bit request
538
539 LEDsoff();
540 // init trace buffer
5f6d6c90 541 iso14a_clear_trace();
991f13f2 542 iso14a_set_tracing(TRUE);
5cd9ec01
M
543
544 // We won't start recording the frames that we acquire until we trigger;
545 // a good trigger condition to get started is probably when we see a
546 // response from the tag.
547 // triggered == FALSE -- to wait first for card
7bc95e2e 548 bool triggered = !(param & 0x03);
549
5cd9ec01 550 // The command (reader -> tag) that we're receiving.
15c4dc5a 551 // The length of a received command will in most cases be no more than 18 bytes.
552 // So 32 should be enough!
6a1f2d82 553 uint8_t *receivedCmd = ((uint8_t *)BigBuf) + RECV_CMD_OFFSET;
554 uint8_t *receivedCmdPar = ((uint8_t *)BigBuf) + RECV_CMD_PAR_OFFSET;
555
5cd9ec01 556 // The response (tag -> reader) that we're receiving.
6a1f2d82 557 uint8_t *receivedResponse = ((uint8_t *)BigBuf) + RECV_RESP_OFFSET;
558 uint8_t *receivedResponsePar = ((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET;
559
5cd9ec01
M
560 // As we receive stuff, we copy it from receivedCmd or receivedResponse
561 // into trace, along with its length and other annotations.
562 //uint8_t *trace = (uint8_t *)BigBuf;
563
564 // The DMA buffer, used to stream samples from the FPGA
7bc95e2e 565 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
566 uint8_t *data = dmaBuf;
567 uint8_t previous_data = 0;
5cd9ec01
M
568 int maxDataLen = 0;
569 int dataLen = 0;
7bc95e2e 570 bool TagIsActive = FALSE;
571 bool ReaderIsActive = FALSE;
572
573 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
15c4dc5a 574
5cd9ec01 575 // Set up the demodulator for tag -> reader responses.
6a1f2d82 576 DemodInit(receivedResponse, receivedResponsePar);
577
5cd9ec01 578 // Set up the demodulator for the reader -> tag commands
6a1f2d82 579 UartInit(receivedCmd, receivedCmdPar);
580
7bc95e2e 581 // Setup and start DMA.
5cd9ec01 582 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 583
5cd9ec01 584 // And now we loop, receiving samples.
7bc95e2e 585 for(uint32_t rsamples = 0; TRUE; ) {
586
5cd9ec01
M
587 if(BUTTON_PRESS()) {
588 DbpString("cancelled by button");
7bc95e2e 589 break;
5cd9ec01 590 }
15c4dc5a 591
5cd9ec01
M
592 LED_A_ON();
593 WDT_HIT();
15c4dc5a 594
5cd9ec01
M
595 int register readBufDataP = data - dmaBuf;
596 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
597 if (readBufDataP <= dmaBufDataP){
598 dataLen = dmaBufDataP - readBufDataP;
599 } else {
7bc95e2e 600 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
601 }
602 // test for length of buffer
603 if(dataLen > maxDataLen) {
604 maxDataLen = dataLen;
605 if(dataLen > 400) {
7bc95e2e 606 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
607 break;
5cd9ec01
M
608 }
609 }
610 if(dataLen < 1) continue;
611
612 // primary buffer was stopped( <-- we lost data!
613 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
614 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
615 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 616 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
617 }
618 // secondary buffer sets as primary, secondary buffer was stopped
619 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
620 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
621 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
622 }
623
624 LED_A_OFF();
7bc95e2e 625
626 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 627
7bc95e2e 628 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
629 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
630 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
631 LED_C_ON();
5cd9ec01 632
7bc95e2e 633 // check - if there is a short 7bit request from reader
634 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 635
7bc95e2e 636 if(triggered) {
6a1f2d82 637 if (!LogTrace(receivedCmd,
638 Uart.len,
639 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
640 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
641 Uart.parity,
642 TRUE)) break;
7bc95e2e 643 }
644 /* And ready to receive another command. */
645 UartReset();
646 /* And also reset the demod code, which might have been */
647 /* false-triggered by the commands from the reader. */
648 DemodReset();
649 LED_B_OFF();
650 }
651 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 652 }
3be2a5ae 653
7bc95e2e 654 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
655 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
656 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
657 LED_B_ON();
5cd9ec01 658
6a1f2d82 659 if (!LogTrace(receivedResponse,
660 Demod.len,
661 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
662 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
663 Demod.parity,
664 FALSE)) break;
5cd9ec01 665
7bc95e2e 666 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 667
7bc95e2e 668 // And ready to receive another response.
669 DemodReset();
670 LED_C_OFF();
671 }
672 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
673 }
5cd9ec01
M
674 }
675
7bc95e2e 676 previous_data = *data;
677 rsamples++;
5cd9ec01 678 data++;
d714d3ef 679 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
680 data = dmaBuf;
681 }
682 } // main cycle
683
684 DbpString("COMMAND FINISHED");
15c4dc5a 685
7bc95e2e 686 FpgaDisableSscDma();
687 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
688 Dbprintf("traceLen=%d, Uart.output[0]=%08x", traceLen, (uint32_t)Uart.output[0]);
5cd9ec01 689 LEDsoff();
15c4dc5a 690}
691
15c4dc5a 692//-----------------------------------------------------------------------------
693// Prepare tag messages
694//-----------------------------------------------------------------------------
6a1f2d82 695static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
15c4dc5a 696{
8f51ddb0 697 ToSendReset();
15c4dc5a 698
699 // Correction bit, might be removed when not needed
700 ToSendStuffBit(0);
701 ToSendStuffBit(0);
702 ToSendStuffBit(0);
703 ToSendStuffBit(0);
704 ToSendStuffBit(1); // 1
705 ToSendStuffBit(0);
706 ToSendStuffBit(0);
707 ToSendStuffBit(0);
8f51ddb0 708
15c4dc5a 709 // Send startbit
72934aa3 710 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 711 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 712
6a1f2d82 713 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 714 uint8_t b = cmd[i];
15c4dc5a 715
716 // Data bits
6a1f2d82 717 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 718 if(b & 1) {
72934aa3 719 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 720 } else {
72934aa3 721 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
722 }
723 b >>= 1;
724 }
15c4dc5a 725
0014cb46 726 // Get the parity bit
6a1f2d82 727 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 728 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 729 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 730 } else {
72934aa3 731 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 732 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 733 }
8f51ddb0 734 }
15c4dc5a 735
8f51ddb0
M
736 // Send stopbit
737 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 738
8f51ddb0
M
739 // Convert from last byte pos to length
740 ToSendMax++;
8f51ddb0
M
741}
742
6a1f2d82 743static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
744{
745 uint8_t par[MAX_PARITY_SIZE];
746
747 GetParity(cmd, len, par);
748 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 749}
750
15c4dc5a 751
8f51ddb0
M
752static void Code4bitAnswerAsTag(uint8_t cmd)
753{
754 int i;
755
5f6d6c90 756 ToSendReset();
8f51ddb0
M
757
758 // Correction bit, might be removed when not needed
759 ToSendStuffBit(0);
760 ToSendStuffBit(0);
761 ToSendStuffBit(0);
762 ToSendStuffBit(0);
763 ToSendStuffBit(1); // 1
764 ToSendStuffBit(0);
765 ToSendStuffBit(0);
766 ToSendStuffBit(0);
767
768 // Send startbit
769 ToSend[++ToSendMax] = SEC_D;
770
771 uint8_t b = cmd;
772 for(i = 0; i < 4; i++) {
773 if(b & 1) {
774 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 775 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
776 } else {
777 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 778 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
779 }
780 b >>= 1;
781 }
782
783 // Send stopbit
784 ToSend[++ToSendMax] = SEC_F;
785
5f6d6c90 786 // Convert from last byte pos to length
787 ToSendMax++;
15c4dc5a 788}
789
790//-----------------------------------------------------------------------------
791// Wait for commands from reader
792// Stop when button is pressed
793// Or return TRUE when command is captured
794//-----------------------------------------------------------------------------
6a1f2d82 795static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
15c4dc5a 796{
797 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
798 // only, since we are receiving, not transmitting).
799 // Signal field is off with the appropriate LED
800 LED_D_OFF();
801 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
802
803 // Now run a `software UART' on the stream of incoming samples.
6a1f2d82 804 UartInit(received, parity);
7bc95e2e 805
806 // clear RXRDY:
807 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 808
809 for(;;) {
810 WDT_HIT();
811
812 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 813
15c4dc5a 814 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 815 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
816 if(MillerDecoding(b, 0)) {
817 *len = Uart.len;
15c4dc5a 818 return TRUE;
819 }
7bc95e2e 820 }
15c4dc5a 821 }
822}
28afbd2b 823
6a1f2d82 824static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
7bc95e2e 825int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
28afbd2b 826int EmSend4bit(uint8_t resp);
6a1f2d82 827int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
828int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
829int EmSendCmd(uint8_t *resp, uint16_t respLen);
830int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
831bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
832 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
15c4dc5a 833
ce02f6f9 834static uint8_t* free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
835
836typedef struct {
837 uint8_t* response;
838 size_t response_n;
839 uint8_t* modulation;
840 size_t modulation_n;
7bc95e2e 841 uint32_t ProxToAirDuration;
ce02f6f9 842} tag_response_info_t;
843
844void reset_free_buffer() {
845 free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
846}
847
848bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 849 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 850 // This will need the following byte array for a modulation sequence
851 // 144 data bits (18 * 8)
852 // 18 parity bits
853 // 2 Start and stop
854 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
855 // 1 just for the case
856 // ----------- +
857 // 166 bytes, since every bit that needs to be send costs us a byte
858 //
859
860 // Prepare the tag modulation bits from the message
861 CodeIso14443aAsTag(response_info->response,response_info->response_n);
862
863 // Make sure we do not exceed the free buffer space
864 if (ToSendMax > max_buffer_size) {
865 Dbprintf("Out of memory, when modulating bits for tag answer:");
866 Dbhexdump(response_info->response_n,response_info->response,false);
867 return false;
868 }
869
870 // Copy the byte array, used for this modulation to the buffer position
871 memcpy(response_info->modulation,ToSend,ToSendMax);
872
7bc95e2e 873 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
ce02f6f9 874 response_info->modulation_n = ToSendMax;
7bc95e2e 875 response_info->ProxToAirDuration = LastProxToAirDuration;
ce02f6f9 876
877 return true;
878}
879
880bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
881 // Retrieve and store the current buffer index
882 response_info->modulation = free_buffer_pointer;
883
884 // Determine the maximum size we can use from our buffer
6a1f2d82 885 size_t max_buffer_size = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + FREE_BUFFER_SIZE) - free_buffer_pointer;
ce02f6f9 886
887 // Forward the prepare tag modulation function to the inner function
888 if (prepare_tag_modulation(response_info,max_buffer_size)) {
889 // Update the free buffer offset
890 free_buffer_pointer += ToSendMax;
891 return true;
892 } else {
893 return false;
894 }
895}
896
15c4dc5a 897//-----------------------------------------------------------------------------
898// Main loop of simulated tag: receive commands from reader, decide what
899// response to send, and send it.
900//-----------------------------------------------------------------------------
28afbd2b 901void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
15c4dc5a 902{
5f6d6c90 903 // Enable and clear the trace
5f6d6c90 904 iso14a_clear_trace();
7bc95e2e 905 iso14a_set_tracing(TRUE);
81cd0474 906
81cd0474 907 uint8_t sak;
908
909 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
910 uint8_t response1[2];
911
912 switch (tagType) {
913 case 1: { // MIFARE Classic
914 // Says: I am Mifare 1k - original line
915 response1[0] = 0x04;
916 response1[1] = 0x00;
917 sak = 0x08;
918 } break;
919 case 2: { // MIFARE Ultralight
920 // Says: I am a stupid memory tag, no crypto
921 response1[0] = 0x04;
922 response1[1] = 0x00;
923 sak = 0x00;
924 } break;
925 case 3: { // MIFARE DESFire
926 // Says: I am a DESFire tag, ph33r me
927 response1[0] = 0x04;
928 response1[1] = 0x03;
929 sak = 0x20;
930 } break;
931 case 4: { // ISO/IEC 14443-4
932 // Says: I am a javacard (JCOP)
933 response1[0] = 0x04;
934 response1[1] = 0x00;
935 sak = 0x28;
936 } break;
3fe4ff4f 937 case 5: { // MIFARE TNP3XXX
938 // Says: I am a toy
939 response1[0] = 0x01;
940 response1[1] = 0x0f;
941 sak = 0x01;
942 } break;
81cd0474 943 default: {
944 Dbprintf("Error: unkown tagtype (%d)",tagType);
945 return;
946 } break;
947 }
948
949 // The second response contains the (mandatory) first 24 bits of the UID
950 uint8_t response2[5];
951
952 // Check if the uid uses the (optional) part
953 uint8_t response2a[5];
954 if (uid_2nd) {
955 response2[0] = 0x88;
956 num_to_bytes(uid_1st,3,response2+1);
957 num_to_bytes(uid_2nd,4,response2a);
958 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
959
960 // Configure the ATQA and SAK accordingly
961 response1[0] |= 0x40;
962 sak |= 0x04;
963 } else {
964 num_to_bytes(uid_1st,4,response2);
965 // Configure the ATQA and SAK accordingly
966 response1[0] &= 0xBF;
967 sak &= 0xFB;
968 }
969
970 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
971 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
972
973 // Prepare the mandatory SAK (for 4 and 7 byte UID)
974 uint8_t response3[3];
975 response3[0] = sak;
976 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
977
978 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
979 uint8_t response3a[3];
980 response3a[0] = sak & 0xFB;
981 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
982
254b70a4 983 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
6a1f2d82 984 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
985 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
986 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
987 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
988 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 989 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
990
7bc95e2e 991 #define TAG_RESPONSE_COUNT 7
992 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
993 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
994 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
995 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
996 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
997 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
998 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
999 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1000 };
1001
1002 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1003 // Such a response is less time critical, so we can prepare them on the fly
1004 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1005 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1006 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1007 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1008 tag_response_info_t dynamic_response_info = {
1009 .response = dynamic_response_buffer,
1010 .response_n = 0,
1011 .modulation = dynamic_modulation_buffer,
1012 .modulation_n = 0
1013 };
ce02f6f9 1014
7bc95e2e 1015 // Reset the offset pointer of the free buffer
1016 reset_free_buffer();
ce02f6f9 1017
7bc95e2e 1018 // Prepare the responses of the anticollision phase
ce02f6f9 1019 // there will be not enough time to do this at the moment the reader sends it REQA
7bc95e2e 1020 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1021 prepare_allocated_tag_modulation(&responses[i]);
1022 }
15c4dc5a 1023
7bc95e2e 1024 int len = 0;
15c4dc5a 1025
1026 // To control where we are in the protocol
1027 int order = 0;
1028 int lastorder;
1029
1030 // Just to allow some checks
1031 int happened = 0;
1032 int happened2 = 0;
81cd0474 1033 int cmdsRecvd = 0;
15c4dc5a 1034
254b70a4 1035 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 1036 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
15c4dc5a 1037
6a1f2d82 1038 // buffers used on software Uart:
1039 uint8_t *receivedCmd = ((uint8_t *)BigBuf) + RECV_CMD_OFFSET;
1040 uint8_t *receivedCmdPar = ((uint8_t *)BigBuf) + RECV_CMD_PAR_OFFSET;
1041
254b70a4 1042 cmdsRecvd = 0;
7bc95e2e 1043 tag_response_info_t* p_response;
15c4dc5a 1044
254b70a4 1045 LED_A_ON();
1046 for(;;) {
7bc95e2e 1047 // Clean receive command buffer
1048
6a1f2d82 1049 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1050 DbpString("Button press");
254b70a4 1051 break;
1052 }
7bc95e2e 1053
1054 p_response = NULL;
1055
254b70a4 1056 // Okay, look at the command now.
1057 lastorder = order;
1058 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1059 p_response = &responses[0]; order = 1;
254b70a4 1060 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1061 p_response = &responses[0]; order = 6;
254b70a4 1062 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1063 p_response = &responses[1]; order = 2;
6a1f2d82 1064 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1065 p_response = &responses[2]; order = 20;
254b70a4 1066 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1067 p_response = &responses[3]; order = 3;
254b70a4 1068 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1069 p_response = &responses[4]; order = 30;
254b70a4 1070 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
6a1f2d82 1071 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
7bc95e2e 1072 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
5f6d6c90 1073 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
7bc95e2e 1074 p_response = NULL;
254b70a4 1075 } else if(receivedCmd[0] == 0x50) { // Received a HALT
3fe4ff4f 1076
7bc95e2e 1077 if (tracing) {
6a1f2d82 1078 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1079 }
1080 p_response = NULL;
254b70a4 1081 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
ce02f6f9 1082 p_response = &responses[5]; order = 7;
254b70a4 1083 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
7bc95e2e 1084 if (tagType == 1 || tagType == 2) { // RATS not supported
1085 EmSend4bit(CARD_NACK_NA);
1086 p_response = NULL;
1087 } else {
1088 p_response = &responses[6]; order = 70;
1089 }
6a1f2d82 1090 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
7bc95e2e 1091 if (tracing) {
6a1f2d82 1092 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1093 }
1094 uint32_t nr = bytes_to_num(receivedCmd,4);
1095 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1096 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1097 } else {
1098 // Check for ISO 14443A-4 compliant commands, look at left nibble
1099 switch (receivedCmd[0]) {
1100
1101 case 0x0B:
1102 case 0x0A: { // IBlock (command)
1103 dynamic_response_info.response[0] = receivedCmd[0];
1104 dynamic_response_info.response[1] = 0x00;
1105 dynamic_response_info.response[2] = 0x90;
1106 dynamic_response_info.response[3] = 0x00;
1107 dynamic_response_info.response_n = 4;
1108 } break;
1109
1110 case 0x1A:
1111 case 0x1B: { // Chaining command
1112 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1113 dynamic_response_info.response_n = 2;
1114 } break;
1115
1116 case 0xaa:
1117 case 0xbb: {
1118 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1119 dynamic_response_info.response_n = 2;
1120 } break;
1121
1122 case 0xBA: { //
1123 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1124 dynamic_response_info.response_n = 2;
1125 } break;
1126
1127 case 0xCA:
1128 case 0xC2: { // Readers sends deselect command
1129 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1130 dynamic_response_info.response_n = 2;
1131 } break;
1132
1133 default: {
1134 // Never seen this command before
1135 if (tracing) {
6a1f2d82 1136 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1137 }
1138 Dbprintf("Received unknown command (len=%d):",len);
1139 Dbhexdump(len,receivedCmd,false);
1140 // Do not respond
1141 dynamic_response_info.response_n = 0;
1142 } break;
1143 }
ce02f6f9 1144
7bc95e2e 1145 if (dynamic_response_info.response_n > 0) {
1146 // Copy the CID from the reader query
1147 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1148
7bc95e2e 1149 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1150 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1151 dynamic_response_info.response_n += 2;
ce02f6f9 1152
7bc95e2e 1153 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1154 Dbprintf("Error preparing tag response");
1155 if (tracing) {
6a1f2d82 1156 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1157 }
1158 break;
1159 }
1160 p_response = &dynamic_response_info;
1161 }
81cd0474 1162 }
15c4dc5a 1163
1164 // Count number of wakeups received after a halt
1165 if(order == 6 && lastorder == 5) { happened++; }
1166
1167 // Count number of other messages after a halt
1168 if(order != 6 && lastorder == 5) { happened2++; }
1169
15c4dc5a 1170 if(cmdsRecvd > 999) {
1171 DbpString("1000 commands later...");
254b70a4 1172 break;
15c4dc5a 1173 }
ce02f6f9 1174 cmdsRecvd++;
1175
1176 if (p_response != NULL) {
7bc95e2e 1177 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1178 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1179 uint8_t par[MAX_PARITY_SIZE];
1180 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1181
7bc95e2e 1182 EmLogTrace(Uart.output,
1183 Uart.len,
1184 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1185 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1186 Uart.parity,
7bc95e2e 1187 p_response->response,
1188 p_response->response_n,
1189 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1190 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1191 par);
7bc95e2e 1192 }
1193
1194 if (!tracing) {
1195 Dbprintf("Trace Full. Simulation stopped.");
1196 break;
1197 }
1198 }
15c4dc5a 1199
1200 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1201 LED_A_OFF();
1202}
1203
9492e0b0 1204
1205// prepare a delayed transfer. This simply shifts ToSend[] by a number
1206// of bits specified in the delay parameter.
1207void PrepareDelayedTransfer(uint16_t delay)
1208{
1209 uint8_t bitmask = 0;
1210 uint8_t bits_to_shift = 0;
1211 uint8_t bits_shifted = 0;
1212
1213 delay &= 0x07;
1214 if (delay) {
1215 for (uint16_t i = 0; i < delay; i++) {
1216 bitmask |= (0x01 << i);
1217 }
7bc95e2e 1218 ToSend[ToSendMax++] = 0x00;
9492e0b0 1219 for (uint16_t i = 0; i < ToSendMax; i++) {
1220 bits_to_shift = ToSend[i] & bitmask;
1221 ToSend[i] = ToSend[i] >> delay;
1222 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1223 bits_shifted = bits_to_shift;
1224 }
1225 }
1226}
1227
7bc95e2e 1228
1229//-------------------------------------------------------------------------------------
15c4dc5a 1230// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1231// Parameter timing:
7bc95e2e 1232// if NULL: transfer at next possible time, taking into account
1233// request guard time and frame delay time
1234// if == 0: transfer immediately and return time of transfer
9492e0b0 1235// if != 0: delay transfer until time specified
7bc95e2e 1236//-------------------------------------------------------------------------------------
6a1f2d82 1237static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1238{
7bc95e2e 1239
9492e0b0 1240 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1241
7bc95e2e 1242 uint32_t ThisTransferTime = 0;
e30c654b 1243
9492e0b0 1244 if (timing) {
1245 if(*timing == 0) { // Measure time
7bc95e2e 1246 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
9492e0b0 1247 } else {
1248 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1249 }
7bc95e2e 1250 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1251 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1252 LastTimeProxToAirStart = *timing;
1253 } else {
1254 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1255 while(GetCountSspClk() < ThisTransferTime);
1256 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1257 }
1258
7bc95e2e 1259 // clear TXRDY
1260 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1261
7bc95e2e 1262 uint16_t c = 0;
9492e0b0 1263 for(;;) {
1264 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1265 AT91C_BASE_SSC->SSC_THR = cmd[c];
1266 c++;
1267 if(c >= len) {
1268 break;
1269 }
1270 }
1271 }
7bc95e2e 1272
1273 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1274}
1275
7bc95e2e 1276
15c4dc5a 1277//-----------------------------------------------------------------------------
195af472 1278// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1279//-----------------------------------------------------------------------------
6a1f2d82 1280void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1281{
7bc95e2e 1282 int i, j;
1283 int last;
1284 uint8_t b;
e30c654b 1285
7bc95e2e 1286 ToSendReset();
e30c654b 1287
7bc95e2e 1288 // Start of Communication (Seq. Z)
1289 ToSend[++ToSendMax] = SEC_Z;
1290 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1291 last = 0;
1292
1293 size_t bytecount = nbytes(bits);
1294 // Generate send structure for the data bits
1295 for (i = 0; i < bytecount; i++) {
1296 // Get the current byte to send
1297 b = cmd[i];
1298 size_t bitsleft = MIN((bits-(i*8)),8);
1299
1300 for (j = 0; j < bitsleft; j++) {
1301 if (b & 1) {
1302 // Sequence X
1303 ToSend[++ToSendMax] = SEC_X;
1304 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1305 last = 1;
1306 } else {
1307 if (last == 0) {
1308 // Sequence Z
1309 ToSend[++ToSendMax] = SEC_Z;
1310 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1311 } else {
1312 // Sequence Y
1313 ToSend[++ToSendMax] = SEC_Y;
1314 last = 0;
1315 }
1316 }
1317 b >>= 1;
1318 }
1319
6a1f2d82 1320 // Only transmit parity bit if we transmitted a complete byte
7bc95e2e 1321 if (j == 8) {
1322 // Get the parity bit
6a1f2d82 1323 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1324 // Sequence X
1325 ToSend[++ToSendMax] = SEC_X;
1326 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1327 last = 1;
1328 } else {
1329 if (last == 0) {
1330 // Sequence Z
1331 ToSend[++ToSendMax] = SEC_Z;
1332 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1333 } else {
1334 // Sequence Y
1335 ToSend[++ToSendMax] = SEC_Y;
1336 last = 0;
1337 }
1338 }
1339 }
1340 }
e30c654b 1341
7bc95e2e 1342 // End of Communication: Logic 0 followed by Sequence Y
1343 if (last == 0) {
1344 // Sequence Z
1345 ToSend[++ToSendMax] = SEC_Z;
1346 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1347 } else {
1348 // Sequence Y
1349 ToSend[++ToSendMax] = SEC_Y;
1350 last = 0;
1351 }
1352 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1353
7bc95e2e 1354 // Convert to length of command:
1355 ToSendMax++;
15c4dc5a 1356}
1357
195af472 1358//-----------------------------------------------------------------------------
1359// Prepare reader command to send to FPGA
1360//-----------------------------------------------------------------------------
6a1f2d82 1361void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
195af472 1362{
6a1f2d82 1363 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1364}
1365
9ca155ba
M
1366//-----------------------------------------------------------------------------
1367// Wait for commands from reader
1368// Stop when button is pressed (return 1) or field was gone (return 2)
1369// Or return 0 when command is captured
1370//-----------------------------------------------------------------------------
6a1f2d82 1371static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
9ca155ba
M
1372{
1373 *len = 0;
1374
1375 uint32_t timer = 0, vtime = 0;
1376 int analogCnt = 0;
1377 int analogAVG = 0;
1378
1379 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1380 // only, since we are receiving, not transmitting).
1381 // Signal field is off with the appropriate LED
1382 LED_D_OFF();
1383 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1384
1385 // Set ADC to read field strength
1386 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1387 AT91C_BASE_ADC->ADC_MR =
1388 ADC_MODE_PRESCALE(32) |
1389 ADC_MODE_STARTUP_TIME(16) |
1390 ADC_MODE_SAMPLE_HOLD_TIME(8);
1391 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1392 // start ADC
1393 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1394
1395 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1396 UartInit(received, parity);
7bc95e2e 1397
1398 // Clear RXRDY:
1399 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba
M
1400
1401 for(;;) {
1402 WDT_HIT();
1403
1404 if (BUTTON_PRESS()) return 1;
1405
1406 // test if the field exists
1407 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1408 analogCnt++;
1409 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1410 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1411 if (analogCnt >= 32) {
1412 if ((33000 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1413 vtime = GetTickCount();
1414 if (!timer) timer = vtime;
1415 // 50ms no field --> card to idle state
1416 if (vtime - timer > 50) return 2;
1417 } else
1418 if (timer) timer = 0;
1419 analogCnt = 0;
1420 analogAVG = 0;
1421 }
1422 }
7bc95e2e 1423
9ca155ba 1424 // receive and test the miller decoding
7bc95e2e 1425 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1426 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1427 if(MillerDecoding(b, 0)) {
1428 *len = Uart.len;
9ca155ba
M
1429 return 0;
1430 }
7bc95e2e 1431 }
1432
9ca155ba
M
1433 }
1434}
1435
9ca155ba 1436
6a1f2d82 1437static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
7bc95e2e 1438{
1439 uint8_t b;
1440 uint16_t i = 0;
1441 uint32_t ThisTransferTime;
1442
9ca155ba
M
1443 // Modulate Manchester
1444 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1445
1446 // include correction bit if necessary
1447 if (Uart.parityBits & 0x01) {
1448 correctionNeeded = TRUE;
1449 }
1450 if(correctionNeeded) {
9ca155ba
M
1451 // 1236, so correction bit needed
1452 i = 0;
7bc95e2e 1453 } else {
1454 i = 1;
9ca155ba 1455 }
7bc95e2e 1456
d714d3ef 1457 // clear receiving shift register and holding register
7bc95e2e 1458 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1459 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1460 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1461 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1462
7bc95e2e 1463 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1464 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1465 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1466 if (AT91C_BASE_SSC->SSC_RHR) break;
1467 }
1468
1469 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1470
1471 // Clear TXRDY:
1472 AT91C_BASE_SSC->SSC_THR = SEC_F;
1473
9ca155ba 1474 // send cycle
7bc95e2e 1475 for(; i <= respLen; ) {
9ca155ba 1476 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1477 AT91C_BASE_SSC->SSC_THR = resp[i++];
1478 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1479 }
7bc95e2e 1480
9ca155ba
M
1481 if(BUTTON_PRESS()) {
1482 break;
1483 }
1484 }
1485
7bc95e2e 1486 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1487 for (i = 0; i < 2 ; ) {
1488 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1489 AT91C_BASE_SSC->SSC_THR = SEC_F;
1490 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1491 i++;
1492 }
1493 }
1494
1495 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1496
9ca155ba
M
1497 return 0;
1498}
1499
7bc95e2e 1500int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1501 Code4bitAnswerAsTag(resp);
0a39986e 1502 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1503 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1504 uint8_t par[1];
1505 GetParity(&resp, 1, par);
7bc95e2e 1506 EmLogTrace(Uart.output,
1507 Uart.len,
1508 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1509 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1510 Uart.parity,
7bc95e2e 1511 &resp,
1512 1,
1513 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1514 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1515 par);
0a39986e 1516 return res;
9ca155ba
M
1517}
1518
8f51ddb0 1519int EmSend4bit(uint8_t resp){
7bc95e2e 1520 return EmSend4bitEx(resp, false);
8f51ddb0
M
1521}
1522
6a1f2d82 1523int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1524 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1525 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1526 // do the tracing for the previous reader request and this tag answer:
1527 EmLogTrace(Uart.output,
1528 Uart.len,
1529 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1530 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1531 Uart.parity,
7bc95e2e 1532 resp,
1533 respLen,
1534 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1535 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1536 par);
8f51ddb0
M
1537 return res;
1538}
1539
6a1f2d82 1540int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1541 uint8_t par[MAX_PARITY_SIZE];
1542 GetParity(resp, respLen, par);
1543 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
8f51ddb0
M
1544}
1545
6a1f2d82 1546int EmSendCmd(uint8_t *resp, uint16_t respLen){
1547 uint8_t par[MAX_PARITY_SIZE];
1548 GetParity(resp, respLen, par);
1549 return EmSendCmdExPar(resp, respLen, false, par);
8f51ddb0
M
1550}
1551
6a1f2d82 1552int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1553 return EmSendCmdExPar(resp, respLen, false, par);
1554}
1555
6a1f2d82 1556bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1557 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1558{
1559 if (tracing) {
1560 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1561 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1562 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1563 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1564 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1565 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1566 reader_EndTime = tag_StartTime - exact_fdt;
1567 reader_StartTime = reader_EndTime - reader_modlen;
6a1f2d82 1568 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
7bc95e2e 1569 return FALSE;
6a1f2d82 1570 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
7bc95e2e 1571 } else {
1572 return TRUE;
1573 }
9ca155ba
M
1574}
1575
15c4dc5a 1576//-----------------------------------------------------------------------------
1577// Wait a certain time for tag response
1578// If a response is captured return TRUE
e691fc45 1579// If it takes too long return FALSE
15c4dc5a 1580//-----------------------------------------------------------------------------
6a1f2d82 1581static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1582{
52bfb955 1583 uint32_t c;
e691fc45 1584
15c4dc5a 1585 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1586 // only, since we are receiving, not transmitting).
1587 // Signal field is on with the appropriate LED
1588 LED_D_ON();
1589 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1590
534983d7 1591 // Now get the answer from the card
6a1f2d82 1592 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1593
7bc95e2e 1594 // clear RXRDY:
1595 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1596
15c4dc5a 1597 c = 0;
1598 for(;;) {
534983d7 1599 WDT_HIT();
15c4dc5a 1600
534983d7 1601 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1602 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1603 if(ManchesterDecoding(b, offset, 0)) {
1604 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1605 return TRUE;
6a1f2d82 1606 } else if (c++ > iso14a_timeout) {
7bc95e2e 1607 return FALSE;
15c4dc5a 1608 }
534983d7 1609 }
1610 }
15c4dc5a 1611}
1612
6a1f2d82 1613void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1614{
6a1f2d82 1615 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1616
7bc95e2e 1617 // Send command to tag
1618 TransmitFor14443a(ToSend, ToSendMax, timing);
1619 if(trigger)
1620 LED_A_ON();
dfc3c505 1621
7bc95e2e 1622 // Log reader command in trace buffer
1623 if (tracing) {
6a1f2d82 1624 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
7bc95e2e 1625 }
15c4dc5a 1626}
1627
6a1f2d82 1628void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1629{
6a1f2d82 1630 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1631}
15c4dc5a 1632
6a1f2d82 1633void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1634{
1635 // Generate parity and redirect
6a1f2d82 1636 uint8_t par[MAX_PARITY_SIZE];
1637 GetParity(frame, len/8, par);
1638 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1639}
1640
6a1f2d82 1641void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1642{
1643 // Generate parity and redirect
6a1f2d82 1644 uint8_t par[MAX_PARITY_SIZE];
1645 GetParity(frame, len, par);
1646 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1647}
1648
6a1f2d82 1649int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1650{
6a1f2d82 1651 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
7bc95e2e 1652 if (tracing) {
6a1f2d82 1653 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1654 }
e691fc45 1655 return Demod.len;
1656}
1657
6a1f2d82 1658int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
15c4dc5a 1659{
6a1f2d82 1660 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
7bc95e2e 1661 if (tracing) {
6a1f2d82 1662 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1663 }
e691fc45 1664 return Demod.len;
f89c7050
M
1665}
1666
e691fc45 1667/* performs iso14443a anticollision procedure
534983d7 1668 * fills the uid pointer unless NULL
1669 * fills resp_data unless NULL */
6a1f2d82 1670int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1671 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1672 uint8_t sel_all[] = { 0x93,0x20 };
1673 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1674 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1675 uint8_t *resp = ((uint8_t *)BigBuf) + RECV_RESP_OFFSET;
1676 uint8_t *resp_par = ((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET;
1677 byte_t uid_resp[4];
1678 size_t uid_resp_len;
1679
1680 uint8_t sak = 0x04; // cascade uid
1681 int cascade_level = 0;
1682 int len;
1683
1684 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
9492e0b0 1685 ReaderTransmitBitsPar(wupa,7,0, NULL);
7bc95e2e 1686
6a1f2d82 1687 // Receive the ATQA
1688 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1689
1690 if(p_hi14a_card) {
1691 memcpy(p_hi14a_card->atqa, resp, 2);
1692 p_hi14a_card->uidlen = 0;
1693 memset(p_hi14a_card->uid,0,10);
1694 }
5f6d6c90 1695
6a1f2d82 1696 // clear uid
1697 if (uid_ptr) {
1698 memset(uid_ptr,0,10);
1699 }
79a73ab2 1700
6a1f2d82 1701 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1702 // which case we need to make a cascade 2 request and select - this is a long UID
1703 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1704 for(; sak & 0x04; cascade_level++) {
1705 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1706 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1707
1708 // SELECT_ALL
1709 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1710 if (!ReaderReceive(resp, resp_par)) return 0;
1711
1712 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1713 memset(uid_resp, 0, 4);
1714 uint16_t uid_resp_bits = 0;
1715 uint16_t collision_answer_offset = 0;
1716 // anti-collision-loop:
1717 while (Demod.collisionPos) {
1718 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1719 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1720 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
758f1fd1 1721 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1722 }
1723 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1724 uid_resp_bits++;
1725 // construct anticollosion command:
1726 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1727 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1728 sel_uid[2+i] = uid_resp[i];
1729 }
1730 collision_answer_offset = uid_resp_bits%8;
1731 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1732 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
e691fc45 1733 }
6a1f2d82 1734 // finally, add the last bits and BCC of the UID
1735 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1736 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1737 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
e691fc45 1738 }
e691fc45 1739
6a1f2d82 1740 } else { // no collision, use the response to SELECT_ALL as current uid
1741 memcpy(uid_resp, resp, 4);
1742 }
1743 uid_resp_len = 4;
5f6d6c90 1744
6a1f2d82 1745 // calculate crypto UID. Always use last 4 Bytes.
1746 if(cuid_ptr) {
1747 *cuid_ptr = bytes_to_num(uid_resp, 4);
1748 }
e30c654b 1749
6a1f2d82 1750 // Construct SELECT UID command
1751 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1752 memcpy(sel_uid+2, uid_resp, 4); // the UID
1753 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1754 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1755 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1756
1757 // Receive the SAK
1758 if (!ReaderReceive(resp, resp_par)) return 0;
1759 sak = resp[0];
1760
52ab55ab 1761 // Test if more parts of the uid are coming
6a1f2d82 1762 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1763 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1764 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1765 uid_resp[0] = uid_resp[1];
1766 uid_resp[1] = uid_resp[2];
1767 uid_resp[2] = uid_resp[3];
1768
1769 uid_resp_len = 3;
1770 }
5f6d6c90 1771
6a1f2d82 1772 if(uid_ptr) {
1773 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1774 }
5f6d6c90 1775
6a1f2d82 1776 if(p_hi14a_card) {
1777 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1778 p_hi14a_card->uidlen += uid_resp_len;
1779 }
1780 }
79a73ab2 1781
6a1f2d82 1782 if(p_hi14a_card) {
1783 p_hi14a_card->sak = sak;
1784 p_hi14a_card->ats_len = 0;
1785 }
534983d7 1786
3fe4ff4f 1787 // non iso14443a compliant tag
1788 if( (sak & 0x20) == 0) return 2;
534983d7 1789
6a1f2d82 1790 // Request for answer to select
1791 AppendCrc14443a(rats, 2);
1792 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1793
6a1f2d82 1794 if (!(len = ReaderReceive(resp, resp_par))) return 0;
5191b3d1 1795
3fe4ff4f 1796
6a1f2d82 1797 if(p_hi14a_card) {
1798 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1799 p_hi14a_card->ats_len = len;
1800 }
5f6d6c90 1801
6a1f2d82 1802 // reset the PCB block number
1803 iso14_pcb_blocknum = 0;
6a1f2d82 1804 return 1;
7e758047 1805}
15c4dc5a 1806
7bc95e2e 1807void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1808 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1809 // Set up the synchronous serial port
1810 FpgaSetupSsc();
7bc95e2e 1811 // connect Demodulated Signal to ADC:
7e758047 1812 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
e30c654b 1813
7e758047 1814 // Signal field is on with the appropriate LED
7bc95e2e 1815 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1816 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1817 LED_D_ON();
1818 } else {
1819 LED_D_OFF();
1820 }
1821 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
534983d7 1822
7bc95e2e 1823 // Start the timer
1824 StartCountSspClk();
1825
1826 DemodReset();
1827 UartReset();
1828 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1829 iso14a_set_timeout(1050); // 10ms default
7e758047 1830}
15c4dc5a 1831
6a1f2d82 1832int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1833 uint8_t parity[MAX_PARITY_SIZE];
534983d7 1834 uint8_t real_cmd[cmd_len+4];
1835 real_cmd[0] = 0x0a; //I-Block
b0127e65 1836 // put block number into the PCB
1837 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 1838 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1839 memcpy(real_cmd+2, cmd, cmd_len);
1840 AppendCrc14443a(real_cmd,cmd_len+2);
1841
9492e0b0 1842 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 1843 size_t len = ReaderReceive(data, parity);
1844 uint8_t *data_bytes = (uint8_t *) data;
b0127e65 1845 if (!len)
1846 return 0; //DATA LINK ERROR
1847 // if we received an I- or R(ACK)-Block with a block number equal to the
1848 // current block number, toggle the current block number
1849 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1850 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1851 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1852 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1853 {
1854 iso14_pcb_blocknum ^= 1;
1855 }
1856
534983d7 1857 return len;
1858}
1859
7e758047 1860//-----------------------------------------------------------------------------
1861// Read an ISO 14443a tag. Send out commands and store answers.
1862//
1863//-----------------------------------------------------------------------------
7bc95e2e 1864void ReaderIso14443a(UsbCommand *c)
7e758047 1865{
534983d7 1866 iso14a_command_t param = c->arg[0];
7bc95e2e 1867 uint8_t *cmd = c->d.asBytes;
534983d7 1868 size_t len = c->arg[1];
5f6d6c90 1869 size_t lenbits = c->arg[2];
9492e0b0 1870 uint32_t arg0 = 0;
1871 byte_t buf[USB_CMD_DATA_SIZE];
6a1f2d82 1872 uint8_t par[MAX_PARITY_SIZE];
902cb3c0 1873
5f6d6c90 1874 if(param & ISO14A_CONNECT) {
1875 iso14a_clear_trace();
1876 }
e691fc45 1877
7bc95e2e 1878 iso14a_set_tracing(TRUE);
e30c654b 1879
79a73ab2 1880 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1881 iso14a_set_trigger(TRUE);
9492e0b0 1882 }
15c4dc5a 1883
534983d7 1884 if(param & ISO14A_CONNECT) {
7bc95e2e 1885 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 1886 if(!(param & ISO14A_NO_SELECT)) {
1887 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1888 arg0 = iso14443a_select_card(NULL,card,NULL);
1889 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1890 }
534983d7 1891 }
e30c654b 1892
534983d7 1893 if(param & ISO14A_SET_TIMEOUT) {
3fe4ff4f 1894 iso14a_set_timeout(c->arg[2]);
534983d7 1895 }
e30c654b 1896
534983d7 1897 if(param & ISO14A_APDU) {
902cb3c0 1898 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 1899 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1900 }
e30c654b 1901
534983d7 1902 if(param & ISO14A_RAW) {
1903 if(param & ISO14A_APPEND_CRC) {
1904 AppendCrc14443a(cmd,len);
1905 len += 2;
c7324bef 1906 if (lenbits) lenbits += 16;
15c4dc5a 1907 }
5f6d6c90 1908 if(lenbits>0) {
6a1f2d82 1909 GetParity(cmd, lenbits/8, par);
1910 ReaderTransmitBitsPar(cmd, lenbits, par, NULL);
5f6d6c90 1911 } else {
1912 ReaderTransmit(cmd,len, NULL);
1913 }
6a1f2d82 1914 arg0 = ReaderReceive(buf, par);
9492e0b0 1915 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1916 }
15c4dc5a 1917
79a73ab2 1918 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1919 iso14a_set_trigger(FALSE);
9492e0b0 1920 }
15c4dc5a 1921
79a73ab2 1922 if(param & ISO14A_NO_DISCONNECT) {
534983d7 1923 return;
9492e0b0 1924 }
15c4dc5a 1925
15c4dc5a 1926 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1927 LEDsoff();
15c4dc5a 1928}
b0127e65 1929
1c611bbd 1930
1c611bbd 1931// Determine the distance between two nonces.
1932// Assume that the difference is small, but we don't know which is first.
1933// Therefore try in alternating directions.
1934int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1935
1936 uint16_t i;
1937 uint32_t nttmp1, nttmp2;
e772353f 1938
1c611bbd 1939 if (nt1 == nt2) return 0;
1940
1941 nttmp1 = nt1;
1942 nttmp2 = nt2;
1943
1944 for (i = 1; i < 32768; i++) {
1945 nttmp1 = prng_successor(nttmp1, 1);
1946 if (nttmp1 == nt2) return i;
1947 nttmp2 = prng_successor(nttmp2, 1);
1948 if (nttmp2 == nt1) return -i;
1949 }
1950
1951 return(-99999); // either nt1 or nt2 are invalid nonces
e772353f 1952}
1953
e772353f 1954
1c611bbd 1955//-----------------------------------------------------------------------------
1956// Recover several bits of the cypher stream. This implements (first stages of)
1957// the algorithm described in "The Dark Side of Security by Obscurity and
1958// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
1959// (article by Nicolas T. Courtois, 2009)
1960//-----------------------------------------------------------------------------
1961void ReaderMifare(bool first_try)
1962{
1963 // Mifare AUTH
1964 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
1965 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
1966 static uint8_t mf_nr_ar3;
e772353f 1967
6a1f2d82 1968 uint8_t* receivedAnswer = (((uint8_t *)BigBuf) + RECV_RESP_OFFSET);
1969 uint8_t* receivedAnswerPar = (((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET);
7bc95e2e 1970
d2f487af 1971 iso14a_clear_trace();
7bc95e2e 1972 iso14a_set_tracing(TRUE);
e772353f 1973
1c611bbd 1974 byte_t nt_diff = 0;
6a1f2d82 1975 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 1976 static byte_t par_low = 0;
1977 bool led_on = TRUE;
ca4714cd 1978 uint8_t uid[10] ={0};
1c611bbd 1979 uint32_t cuid;
e772353f 1980
6a1f2d82 1981 uint32_t nt = 0;
2ed270a8 1982 uint32_t previous_nt = 0;
1c611bbd 1983 static uint32_t nt_attacked = 0;
3fe4ff4f 1984 byte_t par_list[8] = {0x00};
1985 byte_t ks_list[8] = {0x00};
e772353f 1986
1c611bbd 1987 static uint32_t sync_time;
1988 static uint32_t sync_cycles;
1989 int catch_up_cycles = 0;
1990 int last_catch_up = 0;
1991 uint16_t consecutive_resyncs = 0;
1992 int isOK = 0;
e772353f 1993
1c611bbd 1994 if (first_try) {
1c611bbd 1995 mf_nr_ar3 = 0;
7bc95e2e 1996 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
1997 sync_time = GetCountSspClk() & 0xfffffff8;
1c611bbd 1998 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
1999 nt_attacked = 0;
2000 nt = 0;
6a1f2d82 2001 par[0] = 0;
1c611bbd 2002 }
2003 else {
2004 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1c611bbd 2005 mf_nr_ar3++;
2006 mf_nr_ar[3] = mf_nr_ar3;
6a1f2d82 2007 par[0] = par_low;
1c611bbd 2008 }
e30c654b 2009
15c4dc5a 2010 LED_A_ON();
2011 LED_B_OFF();
2012 LED_C_OFF();
1c611bbd 2013
7bc95e2e 2014
1c611bbd 2015 for(uint16_t i = 0; TRUE; i++) {
2016
2017 WDT_HIT();
e30c654b 2018
1c611bbd 2019 // Test if the action was cancelled
2020 if(BUTTON_PRESS()) {
2021 break;
2022 }
2023
2024 LED_C_ON();
e30c654b 2025
1c611bbd 2026 if(!iso14443a_select_card(uid, NULL, &cuid)) {
9492e0b0 2027 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1c611bbd 2028 continue;
2029 }
2030
9492e0b0 2031 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
1c611bbd 2032 catch_up_cycles = 0;
2033
2034 // if we missed the sync time already, advance to the next nonce repeat
7bc95e2e 2035 while(GetCountSspClk() > sync_time) {
9492e0b0 2036 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
1c611bbd 2037 }
e30c654b 2038
9492e0b0 2039 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2040 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2041
1c611bbd 2042 // Receive the (4 Byte) "random" nonce
6a1f2d82 2043 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2044 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
1c611bbd 2045 continue;
2046 }
2047
1c611bbd 2048 previous_nt = nt;
2049 nt = bytes_to_num(receivedAnswer, 4);
2050
2051 // Transmit reader nonce with fake par
9492e0b0 2052 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
1c611bbd 2053
2054 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2055 int nt_distance = dist_nt(previous_nt, nt);
2056 if (nt_distance == 0) {
2057 nt_attacked = nt;
2058 }
2059 else {
2060 if (nt_distance == -99999) { // invalid nonce received, try again
2061 continue;
2062 }
2063 sync_cycles = (sync_cycles - nt_distance);
9492e0b0 2064 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
1c611bbd 2065 continue;
2066 }
2067 }
2068
2069 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2070 catch_up_cycles = -dist_nt(nt_attacked, nt);
2071 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2072 catch_up_cycles = 0;
2073 continue;
2074 }
2075 if (catch_up_cycles == last_catch_up) {
2076 consecutive_resyncs++;
2077 }
2078 else {
2079 last_catch_up = catch_up_cycles;
2080 consecutive_resyncs = 0;
2081 }
2082 if (consecutive_resyncs < 3) {
9492e0b0 2083 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
1c611bbd 2084 }
2085 else {
2086 sync_cycles = sync_cycles + catch_up_cycles;
9492e0b0 2087 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
1c611bbd 2088 }
2089 continue;
2090 }
2091
2092 consecutive_resyncs = 0;
2093
2094 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
6a1f2d82 2095 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2096 {
9492e0b0 2097 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2098
2099 if (nt_diff == 0)
2100 {
6a1f2d82 2101 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2102 }
2103
2104 led_on = !led_on;
2105 if(led_on) LED_B_ON(); else LED_B_OFF();
2106
6a1f2d82 2107 par_list[nt_diff] = SwapBits(par[0], 8);
1c611bbd 2108 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2109
2110 // Test if the information is complete
2111 if (nt_diff == 0x07) {
2112 isOK = 1;
2113 break;
2114 }
2115
2116 nt_diff = (nt_diff + 1) & 0x07;
2117 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2118 par[0] = par_low;
1c611bbd 2119 } else {
2120 if (nt_diff == 0 && first_try)
2121 {
6a1f2d82 2122 par[0]++;
1c611bbd 2123 } else {
6a1f2d82 2124 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2125 }
2126 }
2127 }
2128
1c611bbd 2129
2130 mf_nr_ar[3] &= 0x1F;
2131
2132 byte_t buf[28];
2133 memcpy(buf + 0, uid, 4);
2134 num_to_bytes(nt, 4, buf + 4);
2135 memcpy(buf + 8, par_list, 8);
2136 memcpy(buf + 16, ks_list, 8);
2137 memcpy(buf + 24, mf_nr_ar, 4);
2138
2139 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2140
2141 // Thats it...
2142 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2143 LEDsoff();
7bc95e2e 2144
2145 iso14a_set_tracing(FALSE);
20f9a2a1 2146}
1c611bbd 2147
d2f487af 2148/**
2149 *MIFARE 1K simulate.
2150 *
2151 *@param flags :
2152 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2153 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2154 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2155 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2156 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2157 */
2158void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
20f9a2a1 2159{
50193c1e 2160 int cardSTATE = MFEMUL_NOFIELD;
8556b852 2161 int _7BUID = 0;
9ca155ba 2162 int vHf = 0; // in mV
8f51ddb0 2163 int res;
0a39986e
M
2164 uint32_t selTimer = 0;
2165 uint32_t authTimer = 0;
6a1f2d82 2166 uint16_t len = 0;
8f51ddb0 2167 uint8_t cardWRBL = 0;
9ca155ba
M
2168 uint8_t cardAUTHSC = 0;
2169 uint8_t cardAUTHKEY = 0xff; // no authentication
51969283 2170 uint32_t cardRr = 0;
9ca155ba 2171 uint32_t cuid = 0;
d2f487af 2172 //uint32_t rn_enc = 0;
51969283 2173 uint32_t ans = 0;
0014cb46
M
2174 uint32_t cardINTREG = 0;
2175 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2176 struct Crypto1State mpcs = {0, 0};
2177 struct Crypto1State *pcs;
2178 pcs = &mpcs;
d2f487af 2179 uint32_t numReads = 0;//Counts numer of times reader read a block
6a1f2d82 2180 uint8_t* receivedCmd = get_bigbufptr_recvcmdbuf();
2181 uint8_t* receivedCmd_par = receivedCmd + MAX_FRAME_SIZE;
2182 uint8_t* response = get_bigbufptr_recvrespbuf();
2183 uint8_t* response_par = response + MAX_FRAME_SIZE;
9ca155ba 2184
d2f487af 2185 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2186 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2187 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2188 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2189 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
9ca155ba 2190
d2f487af 2191 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2192 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
7bc95e2e 2193
d2f487af 2194 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2195 // This can be used in a reader-only attack.
2196 // (it can also be retrieved via 'hf 14a list', but hey...
2197 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2198 uint8_t ar_nr_collected = 0;
0014cb46 2199
0a39986e 2200 // clear trace
7bc95e2e 2201 iso14a_clear_trace();
2202 iso14a_set_tracing(TRUE);
51969283 2203
7bc95e2e 2204 // Authenticate response - nonce
51969283 2205 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
7bc95e2e 2206
d2f487af 2207 //-- Determine the UID
2208 // Can be set from emulator memory, incoming data
2209 // and can be 7 or 4 bytes long
7bc95e2e 2210 if (flags & FLAG_4B_UID_IN_DATA)
d2f487af 2211 {
2212 // 4B uid comes from data-portion of packet
2213 memcpy(rUIDBCC1,datain,4);
8556b852 2214 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
8556b852 2215
7bc95e2e 2216 } else if (flags & FLAG_7B_UID_IN_DATA) {
d2f487af 2217 // 7B uid comes from data-portion of packet
2218 memcpy(&rUIDBCC1[1],datain,3);
2219 memcpy(rUIDBCC2, datain+3, 4);
2220 _7BUID = true;
7bc95e2e 2221 } else {
d2f487af 2222 // get UID from emul memory
2223 emlGetMemBt(receivedCmd, 7, 1);
2224 _7BUID = !(receivedCmd[0] == 0x00);
2225 if (!_7BUID) { // ---------- 4BUID
2226 emlGetMemBt(rUIDBCC1, 0, 4);
2227 } else { // ---------- 7BUID
2228 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2229 emlGetMemBt(rUIDBCC2, 3, 4);
2230 }
2231 }
7bc95e2e 2232
d2f487af 2233 /*
2234 * Regardless of what method was used to set the UID, set fifth byte and modify
2235 * the ATQA for 4 or 7-byte UID
2236 */
d2f487af 2237 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
7bc95e2e 2238 if (_7BUID) {
d2f487af 2239 rATQA[0] = 0x44;
8556b852 2240 rUIDBCC1[0] = 0x88;
8556b852
M
2241 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2242 }
2243
9ca155ba 2244 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 2245 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
9ca155ba 2246
9ca155ba 2247
d2f487af 2248 if (MF_DBGLEVEL >= 1) {
2249 if (!_7BUID) {
b03c0f2d 2250 Dbprintf("4B UID: %02x%02x%02x%02x",
2251 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
7bc95e2e 2252 } else {
b03c0f2d 2253 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2254 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2255 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
d2f487af 2256 }
2257 }
7bc95e2e 2258
2259 bool finished = FALSE;
d2f487af 2260 while (!BUTTON_PRESS() && !finished) {
9ca155ba 2261 WDT_HIT();
9ca155ba
M
2262
2263 // find reader field
2264 // Vref = 3300mV, and an 10:1 voltage divider on the input
2265 // can measure voltages up to 33000 mV
2266 if (cardSTATE == MFEMUL_NOFIELD) {
2267 vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;
2268 if (vHf > MF_MINFIELDV) {
0014cb46 2269 cardSTATE_TO_IDLE();
9ca155ba
M
2270 LED_A_ON();
2271 }
2272 }
d2f487af 2273 if(cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2274
d2f487af 2275 //Now, get data
2276
6a1f2d82 2277 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2278 if (res == 2) { //Field is off!
2279 cardSTATE = MFEMUL_NOFIELD;
2280 LEDsoff();
2281 continue;
7bc95e2e 2282 } else if (res == 1) {
2283 break; //return value 1 means button press
2284 }
2285
d2f487af 2286 // REQ or WUP request in ANY state and WUP in HALTED state
2287 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2288 selTimer = GetTickCount();
2289 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2290 cardSTATE = MFEMUL_SELECT1;
2291
2292 // init crypto block
2293 LED_B_OFF();
2294 LED_C_OFF();
2295 crypto1_destroy(pcs);
2296 cardAUTHKEY = 0xff;
2297 continue;
0a39986e 2298 }
7bc95e2e 2299
50193c1e 2300 switch (cardSTATE) {
d2f487af 2301 case MFEMUL_NOFIELD:
2302 case MFEMUL_HALTED:
50193c1e 2303 case MFEMUL_IDLE:{
6a1f2d82 2304 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2305 break;
2306 }
2307 case MFEMUL_SELECT1:{
9ca155ba
M
2308 // select all
2309 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
d2f487af 2310 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2311 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2312 break;
9ca155ba
M
2313 }
2314
d2f487af 2315 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2316 {
2317 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2318 }
9ca155ba 2319 // select card
0a39986e
M
2320 if (len == 9 &&
2321 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
bfb6a143 2322 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
9ca155ba 2323 cuid = bytes_to_num(rUIDBCC1, 4);
8556b852
M
2324 if (!_7BUID) {
2325 cardSTATE = MFEMUL_WORK;
0014cb46
M
2326 LED_B_ON();
2327 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2328 break;
8556b852
M
2329 } else {
2330 cardSTATE = MFEMUL_SELECT2;
8556b852 2331 }
9ca155ba 2332 }
50193c1e
M
2333 break;
2334 }
d2f487af 2335 case MFEMUL_AUTH1:{
2336 if( len != 8)
2337 {
2338 cardSTATE_TO_IDLE();
6a1f2d82 2339 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2340 break;
2341 }
2342 uint32_t ar = bytes_to_num(receivedCmd, 4);
6a1f2d82 2343 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2344
2345 //Collect AR/NR
2346 if(ar_nr_collected < 2){
273b57a7 2347 if(ar_nr_responses[2] != ar)
2348 {// Avoid duplicates... probably not necessary, ar should vary.
d2f487af 2349 ar_nr_responses[ar_nr_collected*4] = cuid;
2350 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2351 ar_nr_responses[ar_nr_collected*4+2] = ar;
2352 ar_nr_responses[ar_nr_collected*4+3] = nr;
273b57a7 2353 ar_nr_collected++;
d2f487af 2354 }
2355 }
2356
2357 // --- crypto
2358 crypto1_word(pcs, ar , 1);
2359 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2360
2361 // test if auth OK
2362 if (cardRr != prng_successor(nonce, 64)){
b03c0f2d 2363 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2364 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2365 cardRr, prng_successor(nonce, 64));
7bc95e2e 2366 // Shouldn't we respond anything here?
d2f487af 2367 // Right now, we don't nack or anything, which causes the
2368 // reader to do a WUPA after a while. /Martin
b03c0f2d 2369 // -- which is the correct response. /piwi
d2f487af 2370 cardSTATE_TO_IDLE();
6a1f2d82 2371 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2372 break;
2373 }
2374
2375 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2376
2377 num_to_bytes(ans, 4, rAUTH_AT);
2378 // --- crypto
2379 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2380 LED_C_ON();
2381 cardSTATE = MFEMUL_WORK;
b03c0f2d 2382 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2383 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2384 GetTickCount() - authTimer);
d2f487af 2385 break;
2386 }
50193c1e 2387 case MFEMUL_SELECT2:{
7bc95e2e 2388 if (!len) {
6a1f2d82 2389 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2390 break;
2391 }
8556b852 2392 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
9ca155ba 2393 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
8556b852
M
2394 break;
2395 }
9ca155ba 2396
8556b852
M
2397 // select 2 card
2398 if (len == 9 &&
2399 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2400 EmSendCmd(rSAK, sizeof(rSAK));
8556b852
M
2401 cuid = bytes_to_num(rUIDBCC2, 4);
2402 cardSTATE = MFEMUL_WORK;
2403 LED_B_ON();
0014cb46 2404 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
8556b852
M
2405 break;
2406 }
0014cb46
M
2407
2408 // i guess there is a command). go into the work state.
7bc95e2e 2409 if (len != 4) {
6a1f2d82 2410 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2411 break;
2412 }
0014cb46 2413 cardSTATE = MFEMUL_WORK;
d2f487af 2414 //goto lbWORK;
2415 //intentional fall-through to the next case-stmt
50193c1e 2416 }
51969283 2417
7bc95e2e 2418 case MFEMUL_WORK:{
2419 if (len == 0) {
6a1f2d82 2420 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2421 break;
2422 }
2423
d2f487af 2424 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2425
7bc95e2e 2426 if(encrypted_data) {
51969283
M
2427 // decrypt seqence
2428 mf_crypto1_decrypt(pcs, receivedCmd, len);
d2f487af 2429 }
7bc95e2e 2430
d2f487af 2431 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2432 authTimer = GetTickCount();
2433 cardAUTHSC = receivedCmd[1] / 4; // received block num
2434 cardAUTHKEY = receivedCmd[0] - 0x60;
2435 crypto1_destroy(pcs);//Added by martin
2436 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2437
d2f487af 2438 if (!encrypted_data) { // first authentication
b03c0f2d 2439 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
51969283 2440
d2f487af 2441 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2442 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
7bc95e2e 2443 } else { // nested authentication
b03c0f2d 2444 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
7bc95e2e 2445 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2446 num_to_bytes(ans, 4, rAUTH_AT);
2447 }
2448 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2449 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2450 cardSTATE = MFEMUL_AUTH1;
2451 break;
51969283 2452 }
7bc95e2e 2453
8f51ddb0
M
2454 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2455 // BUT... ACK --> NACK
2456 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2457 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2458 break;
2459 }
2460
2461 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2462 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2463 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2464 break;
0a39986e
M
2465 }
2466
7bc95e2e 2467 if(len != 4) {
6a1f2d82 2468 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2469 break;
2470 }
d2f487af 2471
2472 if(receivedCmd[0] == 0x30 // read block
2473 || receivedCmd[0] == 0xA0 // write block
b03c0f2d 2474 || receivedCmd[0] == 0xC0 // inc
2475 || receivedCmd[0] == 0xC1 // dec
2476 || receivedCmd[0] == 0xC2 // restore
7bc95e2e 2477 || receivedCmd[0] == 0xB0) { // transfer
2478 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2479 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2480 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2481 break;
2482 }
2483
7bc95e2e 2484 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2485 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
d2f487af 2486 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2487 break;
2488 }
d2f487af 2489 }
2490 // read block
2491 if (receivedCmd[0] == 0x30) {
b03c0f2d 2492 if (MF_DBGLEVEL >= 4) {
d2f487af 2493 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2494 }
8f51ddb0
M
2495 emlGetMem(response, receivedCmd[1], 1);
2496 AppendCrc14443a(response, 16);
6a1f2d82 2497 mf_crypto1_encrypt(pcs, response, 18, response_par);
2498 EmSendCmdPar(response, 18, response_par);
d2f487af 2499 numReads++;
7bc95e2e 2500 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
d2f487af 2501 Dbprintf("%d reads done, exiting", numReads);
2502 finished = true;
2503 }
0a39986e
M
2504 break;
2505 }
0a39986e 2506 // write block
d2f487af 2507 if (receivedCmd[0] == 0xA0) {
b03c0f2d 2508 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
8f51ddb0 2509 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2510 cardSTATE = MFEMUL_WRITEBL2;
2511 cardWRBL = receivedCmd[1];
0a39986e 2512 break;
7bc95e2e 2513 }
0014cb46 2514 // increment, decrement, restore
d2f487af 2515 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
b03c0f2d 2516 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2517 if (emlCheckValBl(receivedCmd[1])) {
2518 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2519 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2520 break;
2521 }
2522 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2523 if (receivedCmd[0] == 0xC1)
2524 cardSTATE = MFEMUL_INTREG_INC;
2525 if (receivedCmd[0] == 0xC0)
2526 cardSTATE = MFEMUL_INTREG_DEC;
2527 if (receivedCmd[0] == 0xC2)
2528 cardSTATE = MFEMUL_INTREG_REST;
2529 cardWRBL = receivedCmd[1];
0014cb46
M
2530 break;
2531 }
0014cb46 2532 // transfer
d2f487af 2533 if (receivedCmd[0] == 0xB0) {
b03c0f2d 2534 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
0014cb46
M
2535 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2536 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2537 else
2538 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2539 break;
2540 }
9ca155ba 2541 // halt
d2f487af 2542 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
9ca155ba 2543 LED_B_OFF();
0a39986e 2544 LED_C_OFF();
0014cb46
M
2545 cardSTATE = MFEMUL_HALTED;
2546 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2547 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2548 break;
9ca155ba 2549 }
d2f487af 2550 // RATS
2551 if (receivedCmd[0] == 0xe0) {//RATS
8f51ddb0
M
2552 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2553 break;
2554 }
d2f487af 2555 // command not allowed
2556 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2557 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2558 break;
8f51ddb0
M
2559 }
2560 case MFEMUL_WRITEBL2:{
2561 if (len == 18){
2562 mf_crypto1_decrypt(pcs, receivedCmd, len);
2563 emlSetMem(receivedCmd, cardWRBL, 1);
2564 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2565 cardSTATE = MFEMUL_WORK;
51969283 2566 } else {
0014cb46 2567 cardSTATE_TO_IDLE();
6a1f2d82 2568 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2569 }
8f51ddb0 2570 break;
50193c1e 2571 }
0014cb46
M
2572
2573 case MFEMUL_INTREG_INC:{
2574 mf_crypto1_decrypt(pcs, receivedCmd, len);
2575 memcpy(&ans, receivedCmd, 4);
2576 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2577 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2578 cardSTATE_TO_IDLE();
2579 break;
7bc95e2e 2580 }
6a1f2d82 2581 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2582 cardINTREG = cardINTREG + ans;
2583 cardSTATE = MFEMUL_WORK;
2584 break;
2585 }
2586 case MFEMUL_INTREG_DEC:{
2587 mf_crypto1_decrypt(pcs, receivedCmd, len);
2588 memcpy(&ans, receivedCmd, 4);
2589 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2590 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2591 cardSTATE_TO_IDLE();
2592 break;
2593 }
6a1f2d82 2594 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2595 cardINTREG = cardINTREG - ans;
2596 cardSTATE = MFEMUL_WORK;
2597 break;
2598 }
2599 case MFEMUL_INTREG_REST:{
2600 mf_crypto1_decrypt(pcs, receivedCmd, len);
2601 memcpy(&ans, receivedCmd, 4);
2602 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2603 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2604 cardSTATE_TO_IDLE();
2605 break;
2606 }
6a1f2d82 2607 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2608 cardSTATE = MFEMUL_WORK;
2609 break;
2610 }
50193c1e 2611 }
50193c1e
M
2612 }
2613
9ca155ba
M
2614 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2615 LEDsoff();
2616
d2f487af 2617 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2618 {
2619 //May just aswell send the collected ar_nr in the response aswell
2620 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2621 }
d714d3ef 2622
d2f487af 2623 if(flags & FLAG_NR_AR_ATTACK)
2624 {
7bc95e2e 2625 if(ar_nr_collected > 1) {
d2f487af 2626 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
d714d3ef 2627 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
d2f487af 2628 ar_nr_responses[0], // UID
2629 ar_nr_responses[1], //NT
2630 ar_nr_responses[2], //AR1
2631 ar_nr_responses[3], //NR1
2632 ar_nr_responses[6], //AR2
2633 ar_nr_responses[7] //NR2
2634 );
7bc95e2e 2635 } else {
d2f487af 2636 Dbprintf("Failed to obtain two AR/NR pairs!");
7bc95e2e 2637 if(ar_nr_collected >0) {
d714d3ef 2638 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
d2f487af 2639 ar_nr_responses[0], // UID
2640 ar_nr_responses[1], //NT
2641 ar_nr_responses[2], //AR1
2642 ar_nr_responses[3] //NR1
2643 );
2644 }
2645 }
2646 }
0014cb46 2647 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, traceLen);
15c4dc5a 2648}
b62a5a84 2649
d2f487af 2650
2651
b62a5a84
M
2652//-----------------------------------------------------------------------------
2653// MIFARE sniffer.
2654//
2655//-----------------------------------------------------------------------------
5cd9ec01
M
2656void RAMFUNC SniffMifare(uint8_t param) {
2657 // param:
2658 // bit 0 - trigger from first card answer
2659 // bit 1 - trigger from first reader 7-bit request
39864b0b
M
2660
2661 // C(red) A(yellow) B(green)
b62a5a84
M
2662 LEDsoff();
2663 // init trace buffer
991f13f2 2664 iso14a_clear_trace();
2665 iso14a_set_tracing(TRUE);
b62a5a84 2666
b62a5a84
M
2667 // The command (reader -> tag) that we're receiving.
2668 // The length of a received command will in most cases be no more than 18 bytes.
2669 // So 32 should be enough!
2670 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
6a1f2d82 2671 uint8_t *receivedCmdPar = ((uint8_t *)BigBuf) + RECV_CMD_PAR_OFFSET;
b62a5a84 2672 // The response (tag -> reader) that we're receiving.
6a1f2d82 2673 uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RESP_OFFSET);
2674 uint8_t *receivedResponsePar = ((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET;
b62a5a84
M
2675
2676 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2677 // into trace, along with its length and other annotations.
2678 //uint8_t *trace = (uint8_t *)BigBuf;
2679
2680 // The DMA buffer, used to stream samples from the FPGA
7bc95e2e 2681 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
2682 uint8_t *data = dmaBuf;
2683 uint8_t previous_data = 0;
5cd9ec01
M
2684 int maxDataLen = 0;
2685 int dataLen = 0;
7bc95e2e 2686 bool ReaderIsActive = FALSE;
2687 bool TagIsActive = FALSE;
2688
2689 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
b62a5a84
M
2690
2691 // Set up the demodulator for tag -> reader responses.
6a1f2d82 2692 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
2693
2694 // Set up the demodulator for the reader -> tag commands
6a1f2d82 2695 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
2696
2697 // Setup for the DMA.
7bc95e2e 2698 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 2699
b62a5a84 2700 LED_D_OFF();
39864b0b
M
2701
2702 // init sniffer
2703 MfSniffInit();
b62a5a84 2704
b62a5a84 2705 // And now we loop, receiving samples.
7bc95e2e 2706 for(uint32_t sniffCounter = 0; TRUE; ) {
2707
5cd9ec01
M
2708 if(BUTTON_PRESS()) {
2709 DbpString("cancelled by button");
7bc95e2e 2710 break;
5cd9ec01
M
2711 }
2712
b62a5a84
M
2713 LED_A_ON();
2714 WDT_HIT();
39864b0b 2715
7bc95e2e 2716 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2717 // check if a transaction is completed (timeout after 2000ms).
2718 // if yes, stop the DMA transfer and send what we have so far to the client
2719 if (MfSniffSend(2000)) {
2720 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2721 sniffCounter = 0;
2722 data = dmaBuf;
2723 maxDataLen = 0;
2724 ReaderIsActive = FALSE;
2725 TagIsActive = FALSE;
2726 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 2727 }
39864b0b 2728 }
7bc95e2e 2729
2730 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2731 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2732 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2733 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2734 } else {
2735 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
5cd9ec01
M
2736 }
2737 // test for length of buffer
7bc95e2e 2738 if(dataLen > maxDataLen) { // we are more behind than ever...
2739 maxDataLen = dataLen;
5cd9ec01
M
2740 if(dataLen > 400) {
2741 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 2742 break;
b62a5a84
M
2743 }
2744 }
5cd9ec01 2745 if(dataLen < 1) continue;
b62a5a84 2746
7bc95e2e 2747 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
2748 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2749 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2750 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
55acbb2a 2751 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
2752 }
2753 // secondary buffer sets as primary, secondary buffer was stopped
2754 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2755 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
2756 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2757 }
5cd9ec01
M
2758
2759 LED_A_OFF();
b62a5a84 2760
7bc95e2e 2761 if (sniffCounter & 0x01) {
b62a5a84 2762
7bc95e2e 2763 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2764 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2765 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2766 LED_C_INV();
6a1f2d82 2767 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 2768
7bc95e2e 2769 /* And ready to receive another command. */
2770 UartReset();
2771
2772 /* And also reset the demod code */
2773 DemodReset();
2774 }
2775 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2776 }
2777
2778 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2779 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2780 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2781 LED_C_INV();
b62a5a84 2782
6a1f2d82 2783 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 2784
7bc95e2e 2785 // And ready to receive another response.
2786 DemodReset();
2787 }
2788 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2789 }
b62a5a84
M
2790 }
2791
7bc95e2e 2792 previous_data = *data;
2793 sniffCounter++;
5cd9ec01 2794 data++;
d714d3ef 2795 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01 2796 data = dmaBuf;
b62a5a84 2797 }
7bc95e2e 2798
b62a5a84
M
2799 } // main cycle
2800
2801 DbpString("COMMAND FINISHED");
2802
55acbb2a 2803 FpgaDisableSscDma();
39864b0b
M
2804 MfSniffEnd();
2805
7bc95e2e 2806 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
b62a5a84 2807 LEDsoff();
3803d529 2808}
Impressum, Datenschutz