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a126332a 1 //-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
534983d7 12#include "iso14443a.h"
f8ada309 13
534983d7 14static uint32_t iso14a_timeout;
1e262141 15int rsamples = 0;
1e262141 16uint8_t trigger = 0;
b0127e65 17// the block number for the ISO14443-4 PCB
18static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 19
0194ce8f 20static uint8_t* free_buffer_pointer;
21
7bc95e2e 22//
23// ISO14443 timing:
24//
25// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
26#define REQUEST_GUARD_TIME (7000/16 + 1)
27// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
28#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
29// bool LastCommandWasRequest = FALSE;
30
31//
32// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
33//
d714d3ef 34// When the PM acts as reader and is receiving tag data, it takes
35// 3 ticks delay in the AD converter
36// 16 ticks until the modulation detector completes and sets curbit
37// 8 ticks until bit_to_arm is assigned from curbit
38// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 39// 4*16 ticks until we measure the time
40// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 41#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 42
43// When the PM acts as a reader and is sending, it takes
44// 4*16 ticks until we can write data to the sending hold register
45// 8*16 ticks until the SHR is transferred to the Sending Shift Register
46// 8 ticks until the first transfer starts
47// 8 ticks later the FPGA samples the data
48// 1 tick to assign mod_sig_coil
49#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
50
51// When the PM acts as tag and is receiving it takes
d714d3ef 52// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 53// 3 ticks for the A/D conversion,
54// 8 ticks on average until the start of the SSC transfer,
55// 8 ticks until the SSC samples the first data
56// 7*16 ticks to complete the transfer from FPGA to ARM
57// 8 ticks until the next ssp_clk rising edge
d714d3ef 58// 4*16 ticks until we measure the time
7bc95e2e 59// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 60#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 61
62// The FPGA will report its internal sending delay in
63uint16_t FpgaSendQueueDelay;
64// the 5 first bits are the number of bits buffered in mod_sig_buf
65// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
66#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
67
68// When the PM acts as tag and is sending, it takes
d714d3ef 69// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 70// 8*16 ticks until the SHR is transferred to the Sending Shift Register
71// 8 ticks until the first transfer starts
72// 8 ticks later the FPGA samples the data
73// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
74// + 1 tick to assign mod_sig_coil
d714d3ef 75#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 76
77// When the PM acts as sniffer and is receiving tag data, it takes
78// 3 ticks A/D conversion
d714d3ef 79// 14 ticks to complete the modulation detection
80// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 81// + the delays in transferring data - which is the same for
82// sniffing reader and tag data and therefore not relevant
d714d3ef 83#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 84
d714d3ef 85// When the PM acts as sniffer and is receiving reader data, it takes
86// 2 ticks delay in analogue RF receiver (for the falling edge of the
87// start bit, which marks the start of the communication)
7bc95e2e 88// 3 ticks A/D conversion
d714d3ef 89// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 90// + the delays in transferring data - which is the same for
91// sniffing reader and tag data and therefore not relevant
d714d3ef 92#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 93
94//variables used for timing purposes:
95//these are in ssp_clk cycles:
6a1f2d82 96static uint32_t NextTransferTime;
97static uint32_t LastTimeProxToAirStart;
98static uint32_t LastProxToAirDuration;
7bc95e2e 99
8f51ddb0 100// CARD TO READER - manchester
72934aa3 101// Sequence D: 11110000 modulation with subcarrier during first half
102// Sequence E: 00001111 modulation with subcarrier during second half
103// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 104// READER TO CARD - miller
72934aa3 105// Sequence X: 00001100 drop after half a period
106// Sequence Y: 00000000 no drop
107// Sequence Z: 11000000 drop at start
108#define SEC_D 0xf0
109#define SEC_E 0x0f
110#define SEC_F 0x00
111#define SEC_X 0x0c
112#define SEC_Y 0x00
113#define SEC_Z 0xc0
15c4dc5a 114
902cb3c0 115void iso14a_set_trigger(bool enable) {
534983d7 116 trigger = enable;
117}
118
b0127e65 119void iso14a_set_timeout(uint32_t timeout) {
120 iso14a_timeout = timeout;
19a700a8 121 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
b0127e65 122}
8556b852 123
19a700a8 124void iso14a_set_ATS_timeout(uint8_t *ats) {
19a700a8 125 uint8_t tb1;
126 uint8_t fwi;
127 uint32_t fwt;
128
129 if (ats[0] > 1) { // there is a format byte T0
130 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
4c0cf2d2 131
132 if ((ats[1] & 0x10) == 0x10) // there is an interface byte TA(1) preceding TB(1)
19a700a8 133 tb1 = ats[3];
4c0cf2d2 134 else
19a700a8 135 tb1 = ats[2];
4c0cf2d2 136
19a700a8 137 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
ca5bad3d 138 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
139 //fwt = 4096 * (1 << fwi);
19a700a8 140
ca5bad3d 141 iso14a_set_timeout(fwt/(8*16));
142 //iso14a_set_timeout(fwt/128);
19a700a8 143 }
144 }
145}
146
15c4dc5a 147//-----------------------------------------------------------------------------
148// Generate the parity value for a byte sequence
e30c654b 149//
15c4dc5a 150//-----------------------------------------------------------------------------
91c7a7cc 151void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par) {
6a1f2d82 152 uint16_t paritybit_cnt = 0;
153 uint16_t paritybyte_cnt = 0;
154 uint8_t parityBits = 0;
155
156 for (uint16_t i = 0; i < iLen; i++) {
157 // Generate the parity bits
f8ada309 158 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
6a1f2d82 159 if (paritybit_cnt == 7) {
160 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
161 parityBits = 0; // and advance to next Parity Byte
162 paritybyte_cnt++;
163 paritybit_cnt = 0;
164 } else {
165 paritybit_cnt++;
166 }
5f6d6c90 167 }
6a1f2d82 168
169 // save remaining parity bits
91c7a7cc 170 par[paritybyte_cnt] = parityBits;
15c4dc5a 171}
172
91c7a7cc 173void AppendCrc14443a(uint8_t* data, int len) {
5f6d6c90 174 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 175}
176
7bc95e2e 177//=============================================================================
178// ISO 14443 Type A - Miller decoder
179//=============================================================================
180// Basics:
181// This decoder is used when the PM3 acts as a tag.
182// The reader will generate "pauses" by temporarily switching of the field.
183// At the PM3 antenna we will therefore measure a modulated antenna voltage.
184// The FPGA does a comparison with a threshold and would deliver e.g.:
185// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
186// The Miller decoder needs to identify the following sequences:
187// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
188// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
189// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
190// Note 1: the bitstream may start at any time. We therefore need to sync.
191// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 192//-----------------------------------------------------------------------------
b62a5a84 193static tUart Uart;
15c4dc5a 194
d7aa3739 195// Lookup-Table to decide if 4 raw bits are a modulation.
0ec548dc 196// We accept the following:
197// 0001 - a 3 tick wide pause
198// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
199// 0111 - a 2 tick wide pause shifted left
200// 1001 - a 2 tick wide pause shifted right
d7aa3739 201const bool Mod_Miller_LUT[] = {
0ec548dc 202 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
203 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
d7aa3739 204};
0ec548dc 205#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
206#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 207
91c7a7cc 208void UartReset() {
7bc95e2e 209 Uart.state = STATE_UNSYNCD;
210 Uart.bitCount = 0;
211 Uart.len = 0; // number of decoded data bytes
6a1f2d82 212 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 213 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 214 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 215 Uart.startTime = 0;
216 Uart.endTime = 0;
46c65fed 217
218 Uart.byteCntMax = 0;
219 Uart.posCnt = 0;
220 Uart.syncBit = 9999;
7bc95e2e 221}
15c4dc5a 222
91c7a7cc 223void UartInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 224 Uart.output = data;
225 Uart.parity = parity;
0ec548dc 226 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
6a1f2d82 227 UartReset();
228}
d714d3ef 229
7bc95e2e 230// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 231static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time) {
0ec548dc 232 Uart.fourBits = (Uart.fourBits << 8) | bit;
7bc95e2e 233
0c8d25eb 234 if (Uart.state == STATE_UNSYNCD) { // not yet synced
91c7a7cc 235 Uart.syncBit = 9999; // not set
46c65fed 236
237 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
238 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
239 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
240
0ec548dc 241 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
46c65fed 242 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
243 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
0ec548dc 244 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
46c65fed 245 //
246#define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
247#define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
248
0ec548dc 249 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
250 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
251 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
252 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
253 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
254 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
255 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
256 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
257
258 if (Uart.syncBit != 9999) { // found a sync bit
91c7a7cc 259 Uart.startTime = non_real_time ? non_real_time : (GetCountSspClk() & 0xfffffff8);
260 Uart.startTime -= Uart.syncBit;
261 Uart.endTime = Uart.startTime;
262 Uart.state = STATE_START_OF_COMMUNICATION;
263 }
7bc95e2e 264 } else {
15c4dc5a 265
0ec548dc 266 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
267 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
d7aa3739 268 UartReset();
d7aa3739 269 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 270 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
271 UartReset();
7bc95e2e 272 } else {
273 Uart.bitCount++;
274 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
275 Uart.state = STATE_MILLER_Z;
276 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
277 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
278 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
279 Uart.parityBits <<= 1; // make room for the parity bit
280 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
281 Uart.bitCount = 0;
282 Uart.shiftReg = 0;
6a1f2d82 283 if((Uart.len&0x0007) == 0) { // every 8 data bytes
284 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
285 Uart.parityBits = 0;
286 }
15c4dc5a 287 }
7bc95e2e 288 }
d7aa3739 289 }
290 } else {
0ec548dc 291 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 292 Uart.bitCount++;
293 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
294 Uart.state = STATE_MILLER_X;
295 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
296 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
297 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
298 Uart.parityBits <<= 1; // make room for the new parity bit
299 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
300 Uart.bitCount = 0;
301 Uart.shiftReg = 0;
6a1f2d82 302 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
303 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
304 Uart.parityBits = 0;
305 }
7bc95e2e 306 }
d7aa3739 307 } else { // no modulation in both halves - Sequence Y
7bc95e2e 308 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 309 Uart.state = STATE_UNSYNCD;
6a1f2d82 310 Uart.bitCount--; // last "0" was part of EOC sequence
311 Uart.shiftReg <<= 1; // drop it
312 if(Uart.bitCount > 0) { // if we decoded some bits
313 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
314 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
315 Uart.parityBits <<= 1; // add a (void) parity bit
316 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
317 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
318 return TRUE;
319 } else if (Uart.len & 0x0007) { // there are some parity bits to store
320 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
321 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 322 }
323 if (Uart.len) {
6a1f2d82 324 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 325 } else {
0c8d25eb 326 UartReset(); // Nothing received - start over
7bc95e2e 327 }
15c4dc5a 328 }
7bc95e2e 329 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
330 UartReset();
7bc95e2e 331 } else { // a logic "0"
332 Uart.bitCount++;
333 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
334 Uart.state = STATE_MILLER_Y;
335 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
336 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
337 Uart.parityBits <<= 1; // make room for the parity bit
338 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
339 Uart.bitCount = 0;
340 Uart.shiftReg = 0;
6a1f2d82 341 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
342 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
343 Uart.parityBits = 0;
344 }
15c4dc5a 345 }
346 }
d7aa3739 347 }
15c4dc5a 348 }
7bc95e2e 349 }
7bc95e2e 350 return FALSE; // not finished yet, need more data
15c4dc5a 351}
352
353//=============================================================================
e691fc45 354// ISO 14443 Type A - Manchester decoder
15c4dc5a 355//=============================================================================
e691fc45 356// Basics:
7bc95e2e 357// This decoder is used when the PM3 acts as a reader.
e691fc45 358// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
359// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
360// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
361// The Manchester decoder needs to identify the following sequences:
362// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
363// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
364// 8 ticks unmodulated: Sequence F = end of communication
365// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 366// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 367// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 368static tDemod Demod;
15c4dc5a 369
d7aa3739 370// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 371// We accept three or four "1" in any position
7bc95e2e 372const bool Mod_Manchester_LUT[] = {
d7aa3739 373 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 374 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 375};
376
377#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
378#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 379
91c7a7cc 380void DemodReset() {
7bc95e2e 381 Demod.state = DEMOD_UNSYNCD;
382 Demod.len = 0; // number of decoded data bytes
6a1f2d82 383 Demod.parityLen = 0;
7bc95e2e 384 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
385 Demod.parityBits = 0; //
386 Demod.collisionPos = 0; // Position of collision bit
387 Demod.twoBits = 0xffff; // buffer for 2 Bits
388 Demod.highCnt = 0;
389 Demod.startTime = 0;
91c7a7cc 390 Demod.endTime = 0;
46c65fed 391 Demod.bitCount = 0;
392 Demod.syncBit = 0xFFFF;
393 Demod.samples = 0;
e691fc45 394}
15c4dc5a 395
91c7a7cc 396void DemodInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 397 Demod.output = data;
398 Demod.parity = parity;
399 DemodReset();
400}
401
7bc95e2e 402// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 403static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time) {
7bc95e2e 404 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 405
7bc95e2e 406 if (Demod.state == DEMOD_UNSYNCD) {
407
408 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
409 if (Demod.twoBits == 0x0000) {
410 Demod.highCnt++;
411 } else {
412 Demod.highCnt = 0;
413 }
414 } else {
415 Demod.syncBit = 0xFFFF; // not set
416 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
417 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
418 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
419 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
420 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
421 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
422 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
423 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 424 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 425 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
426 Demod.startTime -= Demod.syncBit;
427 Demod.bitCount = offset; // number of decoded data bits
e691fc45 428 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 429 }
7bc95e2e 430 }
7bc95e2e 431 } else {
15c4dc5a 432
7bc95e2e 433 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
434 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 435 if (!Demod.collisionPos) {
436 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
437 }
438 } // modulation in first half only - Sequence D = 1
7bc95e2e 439 Demod.bitCount++;
440 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
441 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 442 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 443 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 444 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
445 Demod.bitCount = 0;
446 Demod.shiftReg = 0;
6a1f2d82 447 if((Demod.len&0x0007) == 0) { // every 8 data bytes
448 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
449 Demod.parityBits = 0;
450 }
15c4dc5a 451 }
7bc95e2e 452 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
453 } else { // no modulation in first half
454 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 455 Demod.bitCount++;
7bc95e2e 456 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 457 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 458 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 459 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 460 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
461 Demod.bitCount = 0;
462 Demod.shiftReg = 0;
6a1f2d82 463 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
464 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
465 Demod.parityBits = 0;
466 }
15c4dc5a 467 }
7bc95e2e 468 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 469 } else { // no modulation in both halves - End of communication
6a1f2d82 470 if(Demod.bitCount > 0) { // there are some remaining data bits
471 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
472 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
473 Demod.parityBits <<= 1; // add a (void) parity bit
474 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
475 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
476 return TRUE;
477 } else if (Demod.len & 0x0007) { // there are some parity bits to store
478 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
479 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 480 }
481 if (Demod.len) {
d7aa3739 482 return TRUE; // we are finished with decoding the raw data sequence
483 } else { // nothing received. Start over
484 DemodReset();
e691fc45 485 }
15c4dc5a 486 }
7bc95e2e 487 }
e691fc45 488 }
e691fc45 489 return FALSE; // not finished yet, need more data
15c4dc5a 490}
491
492//=============================================================================
493// Finally, a `sniffer' for ISO 14443 Type A
494// Both sides of communication!
495//=============================================================================
496
497//-----------------------------------------------------------------------------
498// Record the sequence of commands sent by the reader to the tag, with
499// triggering so that we start recording at the point that the tag is moved
500// near the reader.
bc939371 501// "hf 14a sniff"
15c4dc5a 502//-----------------------------------------------------------------------------
d26849d4 503void RAMFUNC SniffIso14443a(uint8_t param) {
5cd9ec01
M
504 // param:
505 // bit 0 - trigger from first card answer
506 // bit 1 - trigger from first reader 7-bit request
5cd9ec01 507 LEDsoff();
5cd9ec01 508
99cf19d9 509 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
7bc95e2e 510
f71f4deb 511 // Allocate memory from BigBuf for some buffers
512 // free all previous allocations first
aaa1a9a2 513 BigBuf_free(); BigBuf_Clear_ext(false);
7838f4be 514 clear_trace();
515 set_tracing(TRUE);
516
5cd9ec01 517 // The command (reader -> tag) that we're receiving.
f71f4deb 518 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
519 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 520
5cd9ec01 521 // The response (tag -> reader) that we're receiving.
f71f4deb 522 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
523 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
524
525 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 526 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
527
7bc95e2e 528 uint8_t *data = dmaBuf;
529 uint8_t previous_data = 0;
5cd9ec01
M
530 int maxDataLen = 0;
531 int dataLen = 0;
7bc95e2e 532 bool TagIsActive = FALSE;
533 bool ReaderIsActive = FALSE;
534
5cd9ec01 535 // Set up the demodulator for tag -> reader responses.
6a1f2d82 536 DemodInit(receivedResponse, receivedResponsePar);
537
5cd9ec01 538 // Set up the demodulator for the reader -> tag commands
6a1f2d82 539 UartInit(receivedCmd, receivedCmdPar);
540
7bc95e2e 541 // Setup and start DMA.
57850d9d 542 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
543 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
544 return;
545 }
7bc95e2e 546
99cf19d9 547 // We won't start recording the frames that we acquire until we trigger;
548 // a good trigger condition to get started is probably when we see a
549 // response from the tag.
550 // triggered == FALSE -- to wait first for card
551 bool triggered = !(param & 0x03);
552
5cd9ec01 553 // And now we loop, receiving samples.
7bc95e2e 554 for(uint32_t rsamples = 0; TRUE; ) {
555
5cd9ec01
M
556 if(BUTTON_PRESS()) {
557 DbpString("cancelled by button");
7bc95e2e 558 break;
5cd9ec01 559 }
15c4dc5a 560
5cd9ec01
M
561 LED_A_ON();
562 WDT_HIT();
15c4dc5a 563
5cd9ec01
M
564 int register readBufDataP = data - dmaBuf;
565 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
566 if (readBufDataP <= dmaBufDataP){
567 dataLen = dmaBufDataP - readBufDataP;
568 } else {
7bc95e2e 569 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
570 }
571 // test for length of buffer
572 if(dataLen > maxDataLen) {
573 maxDataLen = dataLen;
f71f4deb 574 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 575 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
576 break;
5cd9ec01
M
577 }
578 }
579 if(dataLen < 1) continue;
580
581 // primary buffer was stopped( <-- we lost data!
582 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
583 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
584 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 585 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
586 }
587 // secondary buffer sets as primary, secondary buffer was stopped
588 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
589 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
590 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
591 }
592
593 LED_A_OFF();
7bc95e2e 594
595 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 596
7bc95e2e 597 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
598 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
599 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
600 LED_C_ON();
5cd9ec01 601
7bc95e2e 602 // check - if there is a short 7bit request from reader
603 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 604
7bc95e2e 605 if(triggered) {
6a1f2d82 606 if (!LogTrace(receivedCmd,
607 Uart.len,
608 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
609 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
610 Uart.parity,
611 TRUE)) break;
7bc95e2e 612 }
613 /* And ready to receive another command. */
614 UartReset();
615 /* And also reset the demod code, which might have been */
616 /* false-triggered by the commands from the reader. */
617 DemodReset();
618 LED_B_OFF();
619 }
620 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 621 }
3be2a5ae 622
7bc95e2e 623 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
624 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
625 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
626 LED_B_ON();
5cd9ec01 627
6a1f2d82 628 if (!LogTrace(receivedResponse,
629 Demod.len,
630 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
631 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
632 Demod.parity,
633 FALSE)) break;
5cd9ec01 634
7bc95e2e 635 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 636
7bc95e2e 637 // And ready to receive another response.
638 DemodReset();
0ec548dc 639 // And reset the Miller decoder including itS (now outdated) input buffer
640 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 641 LED_C_OFF();
642 }
643 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
644 }
5cd9ec01
M
645 }
646
7bc95e2e 647 previous_data = *data;
648 rsamples++;
5cd9ec01 649 data++;
d714d3ef 650 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
651 data = dmaBuf;
652 }
653 } // main cycle
654
bc939371 655 if (MF_DBGLEVEL >= 1) {
656 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
657 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
658 }
7bc95e2e 659 FpgaDisableSscDma();
91c7a7cc 660 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
bc939371 661 LEDsoff();
5ee53a0e 662 set_tracing(FALSE);
15c4dc5a 663}
664
15c4dc5a 665//-----------------------------------------------------------------------------
666// Prepare tag messages
667//-----------------------------------------------------------------------------
91c7a7cc 668static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity) {
8f51ddb0 669 ToSendReset();
15c4dc5a 670
671 // Correction bit, might be removed when not needed
672 ToSendStuffBit(0);
673 ToSendStuffBit(0);
674 ToSendStuffBit(0);
675 ToSendStuffBit(0);
676 ToSendStuffBit(1); // 1
677 ToSendStuffBit(0);
678 ToSendStuffBit(0);
679 ToSendStuffBit(0);
8f51ddb0 680
15c4dc5a 681 // Send startbit
72934aa3 682 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 683 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 684
6a1f2d82 685 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 686 uint8_t b = cmd[i];
15c4dc5a 687
688 // Data bits
6a1f2d82 689 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 690 if(b & 1) {
72934aa3 691 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 692 } else {
72934aa3 693 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
694 }
695 b >>= 1;
696 }
15c4dc5a 697
0014cb46 698 // Get the parity bit
6a1f2d82 699 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 700 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 701 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 702 } else {
72934aa3 703 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 704 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 705 }
8f51ddb0 706 }
15c4dc5a 707
8f51ddb0
M
708 // Send stopbit
709 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 710
8f51ddb0 711 // Convert from last byte pos to length
6fc68747 712 ++ToSendMax;
8f51ddb0
M
713}
714
91c7a7cc 715static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len) {
7504dc50 716 uint8_t par[MAX_PARITY_SIZE] = {0};
6a1f2d82 717 GetParity(cmd, len, par);
718 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 719}
720
91c7a7cc 721static void Code4bitAnswerAsTag(uint8_t cmd) {
91c7a7cc 722 uint8_t b = cmd;
8f51ddb0 723
5f6d6c90 724 ToSendReset();
8f51ddb0
M
725
726 // Correction bit, might be removed when not needed
727 ToSendStuffBit(0);
728 ToSendStuffBit(0);
729 ToSendStuffBit(0);
730 ToSendStuffBit(0);
731 ToSendStuffBit(1); // 1
732 ToSendStuffBit(0);
733 ToSendStuffBit(0);
734 ToSendStuffBit(0);
735
736 // Send startbit
737 ToSend[++ToSendMax] = SEC_D;
738
0194ce8f 739 for(uint8_t i = 0; i < 4; i++) {
8f51ddb0
M
740 if(b & 1) {
741 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 742 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
743 } else {
744 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 745 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
746 }
747 b >>= 1;
748 }
749
750 // Send stopbit
751 ToSend[++ToSendMax] = SEC_F;
752
5f6d6c90 753 // Convert from last byte pos to length
754 ToSendMax++;
15c4dc5a 755}
756
757//-----------------------------------------------------------------------------
758// Wait for commands from reader
759// Stop when button is pressed
760// Or return TRUE when command is captured
761//-----------------------------------------------------------------------------
91c7a7cc 762static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len) {
15c4dc5a 763 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
764 // only, since we are receiving, not transmitting).
765 // Signal field is off with the appropriate LED
766 LED_D_OFF();
767 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
768
ca5bad3d 769 // Now run a `software UART` on the stream of incoming samples.
6a1f2d82 770 UartInit(received, parity);
7bc95e2e 771
772 // clear RXRDY:
773 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 774
775 for(;;) {
776 WDT_HIT();
777
778 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 779
15c4dc5a 780 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 781 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
782 if(MillerDecoding(b, 0)) {
783 *len = Uart.len;
15c4dc5a 784 return TRUE;
785 }
7bc95e2e 786 }
15c4dc5a 787 }
788}
28afbd2b 789
ce02f6f9 790bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 791 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 792 // This will need the following byte array for a modulation sequence
793 // 144 data bits (18 * 8)
794 // 18 parity bits
795 // 2 Start and stop
796 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
797 // 1 just for the case
798 // ----------- +
799 // 166 bytes, since every bit that needs to be send costs us a byte
800 //
91c7a7cc 801 // Prepare the tag modulation bits from the message
802 CodeIso14443aAsTag(response_info->response,response_info->response_n);
803
804 // Make sure we do not exceed the free buffer space
805 if (ToSendMax > max_buffer_size) {
806 Dbprintf("Out of memory, when modulating bits for tag answer:");
807 Dbhexdump(response_info->response_n,response_info->response,false);
808 return FALSE;
809 }
810
811 // Copy the byte array, used for this modulation to the buffer position
812 memcpy(response_info->modulation,ToSend,ToSendMax);
813
814 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
815 response_info->modulation_n = ToSendMax;
816 response_info->ProxToAirDuration = LastProxToAirDuration;
817 return TRUE;
ce02f6f9 818}
819
f71f4deb 820// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
821// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
822// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
823// -> need 273 bytes buffer
c9216a92 824// 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
825// 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
826#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
f71f4deb 827
ce02f6f9 828bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
ca5bad3d 829 // Retrieve and store the current buffer index
830 response_info->modulation = free_buffer_pointer;
831
832 // Determine the maximum size we can use from our buffer
833 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
834
835 // Forward the prepare tag modulation function to the inner function
836 if (prepare_tag_modulation(response_info, max_buffer_size)) {
837 // Update the free buffer offset
838 free_buffer_pointer += ToSendMax;
839 return true;
840 } else {
841 return false;
842 }
ce02f6f9 843}
844
15c4dc5a 845//-----------------------------------------------------------------------------
846// Main loop of simulated tag: receive commands from reader, decide what
847// response to send, and send it.
0a856e29 848// 'hf 14a sim'
15c4dc5a 849//-----------------------------------------------------------------------------
91c7a7cc 850void SimulateIso14443aTag(int tagType, int flags, byte_t* data) {
0194ce8f 851
bf5d7992 852 #define ATTACK_KEY_COUNT 8 // keep same as define in cmdhfmf.c -> readerAttack()
853
0194ce8f 854 uint8_t sak = 0;
bc939371 855 uint32_t cuid = 0;
856 uint32_t nonce = 0;
857
32719adf 858 // PACK response to PWD AUTH for EV1/NTAG
0194ce8f 859 uint8_t response8[4] = {0,0,0,0};
860 // Counter for EV1/NTAG
861 uint32_t counters[] = {0,0,0};
32719adf 862
81cd0474 863 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
0194ce8f 864 uint8_t response1[] = {0,0};
6b23be6b 865
866 // Here, we collect CUID, block1, keytype1, NT1, NR1, AR1, CUID, block2, keytyp2, NT2, NR2, AR2
867 // it should also collect block, keytype.
868 uint8_t cardAUTHSC = 0;
869 uint8_t cardAUTHKEY = 0xff; // no authentication
870 // allow collecting up to 8 sets of nonces to allow recovery of up to 8 keys
bf5d7992 871
6067df30 872 nonces_t ar_nr_resp[ATTACK_KEY_COUNT*2]; // for 2 separate attack types (nml, moebius)
6b23be6b 873 memset(ar_nr_resp, 0x00, sizeof(ar_nr_resp));
874
6067df30 875 uint8_t ar_nr_collected[ATTACK_KEY_COUNT*2]; // for 2nd attack type (moebius)
6b23be6b 876 memset(ar_nr_collected, 0x00, sizeof(ar_nr_collected));
877 uint8_t nonce1_count = 0;
878 uint8_t nonce2_count = 0;
879 uint8_t moebius_n_count = 0;
880 bool gettingMoebius = false;
f38cfd66 881 uint8_t mM = 0; // moebius_modifier for collection storage
6b23be6b 882
81cd0474 883
884 switch (tagType) {
0194ce8f 885 case 1: { // MIFARE Classic 1k
81cd0474 886 response1[0] = 0x04;
81cd0474 887 sak = 0x08;
888 } break;
889 case 2: { // MIFARE Ultralight
32719adf 890 response1[0] = 0x44;
81cd0474 891 sak = 0x00;
892 } break;
893 case 3: { // MIFARE DESFire
81cd0474 894 response1[0] = 0x04;
895 response1[1] = 0x03;
896 sak = 0x20;
897 } break;
0194ce8f 898 case 4: { // ISO/IEC 14443-4 - javacard (JCOP)
81cd0474 899 response1[0] = 0x04;
81cd0474 900 sak = 0x28;
901 } break;
3fe4ff4f 902 case 5: { // MIFARE TNP3XXX
3fe4ff4f 903 response1[0] = 0x01;
904 response1[1] = 0x0f;
905 sak = 0x01;
d26849d4 906 } break;
0194ce8f 907 case 6: { // MIFARE Mini 320b
d26849d4 908 response1[0] = 0x44;
d26849d4 909 sak = 0x09;
910 } break;
0194ce8f 911 case 7: { // NTAG
32719adf 912 response1[0] = 0x44;
32719adf 913 sak = 0x00;
914 // PACK
915 response8[0] = 0x80;
916 response8[1] = 0x80;
917 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
2b1f4228 918 // uid not supplied then get from emulator memory
919 if (data[0]==0) {
920 uint16_t start = 4 * (0+12);
921 uint8_t emdata[8];
922 emlGetMemBt( emdata, start, sizeof(emdata));
f38cfd66 923 memcpy(data, emdata, 3); // uid bytes 0-2
924 memcpy(data+3, emdata+4, 4); // uid bytes 3-7
2b1f4228 925 flags |= FLAG_7B_UID_IN_DATA;
926 }
32719adf 927 } break;
81cd0474 928 default: {
929 Dbprintf("Error: unkown tagtype (%d)",tagType);
930 return;
931 } break;
932 }
933
934 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 935 uint8_t response2[5] = {0x00};
81cd0474 936
0194ce8f 937 // For UID size 7,
c8b6da22 938 uint8_t response2a[5] = {0x00};
939
bc939371 940 if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA ) {
0194ce8f 941 response2[0] = 0x88; // Cascade Tag marker
d26849d4 942 response2[1] = data[0];
943 response2[2] = data[1];
944 response2[3] = data[2];
945
946 response2a[0] = data[3];
947 response2a[1] = data[4];
948 response2a[2] = data[5];
c3c241f3 949 response2a[3] = data[6]; //??
81cd0474 950 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
951
952 // Configure the ATQA and SAK accordingly
953 response1[0] |= 0x40;
954 sak |= 0x04;
bc939371 955
956 cuid = bytes_to_num(data+3, 4);
81cd0474 957 } else {
d26849d4 958 memcpy(response2, data, 4);
81cd0474 959 // Configure the ATQA and SAK accordingly
960 response1[0] &= 0xBF;
961 sak &= 0xFB;
bc939371 962 cuid = bytes_to_num(data, 4);
81cd0474 963 }
964
965 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
966 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
967
968 // Prepare the mandatory SAK (for 4 and 7 byte UID)
0194ce8f 969 uint8_t response3[3] = {sak, 0x00, 0x00};
81cd0474 970 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
971
972 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 973 uint8_t response3a[3] = {0x00};
81cd0474 974 response3a[0] = sak & 0xFB;
975 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
976
bf5d7992 977 // Tag NONCE.
978 uint8_t response5[4];
979 nonce = prand();
980 num_to_bytes(nonce, 4, response5);
981
0194ce8f 982 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
6a1f2d82 983 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
984 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
985 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
986 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 987 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
bc939371 988
2b1f4228 989 // Prepare GET_VERSION (different for UL EV-1 / NTAG)
f38cfd66 990 // uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
991 // uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
c9216a92 992 // Prepare CHK_TEARING
f38cfd66 993 // uint8_t response9[] = {0xBD,0x90,0x3f};
c9216a92 994
995 #define TAG_RESPONSE_COUNT 10
7bc95e2e 996 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
997 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
998 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
999 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1000 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1001 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1002 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1003 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
4c0cf2d2 1004
495d7f13 1005 { .response = response8, .response_n = sizeof(response8) } // EV1/NTAG PACK response
4c0cf2d2 1006 };
f38cfd66 1007 // { .response = response7_NTAG, .response_n = sizeof(response7_NTAG)}, // EV1/NTAG GET_VERSION response
1008 // { .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
4c0cf2d2 1009
7bc95e2e 1010
1011 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1012 // Such a response is less time critical, so we can prepare them on the fly
1013 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1014 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1015 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1016 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1017 tag_response_info_t dynamic_response_info = {
1018 .response = dynamic_response_buffer,
1019 .response_n = 0,
1020 .modulation = dynamic_modulation_buffer,
1021 .modulation_n = 0
1022 };
ce02f6f9 1023
99cf19d9 1024 // We need to listen to the high-frequency, peak-detected path.
1025 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1026
f71f4deb 1027 BigBuf_free_keep_EM();
0194ce8f 1028 clear_trace();
1029 set_tracing(TRUE);
f71f4deb 1030
1031 // allocate buffers:
1032 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1033 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1034 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1035
7bc95e2e 1036 // Prepare the responses of the anticollision phase
ce02f6f9 1037 // there will be not enough time to do this at the moment the reader sends it REQA
495d7f13 1038 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++)
7bc95e2e 1039 prepare_allocated_tag_modulation(&responses[i]);
15c4dc5a 1040
7bc95e2e 1041 int len = 0;
15c4dc5a 1042
1043 // To control where we are in the protocol
1044 int order = 0;
1045 int lastorder;
1046
1047 // Just to allow some checks
1048 int happened = 0;
1049 int happened2 = 0;
81cd0474 1050 int cmdsRecvd = 0;
7bc95e2e 1051 tag_response_info_t* p_response;
15c4dc5a 1052
254b70a4 1053 LED_A_ON();
0194ce8f 1054 for(;;) {
4c0cf2d2 1055 WDT_HIT();
1056
7bc95e2e 1057 // Clean receive command buffer
6a1f2d82 1058 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1059 DbpString("Button press");
254b70a4 1060 break;
1061 }
bc939371 1062
1063 // incease nonce at every command recieved
bf5d7992 1064 nonce = prand();
bc939371 1065 num_to_bytes(nonce, 4, response5);
1066
7bc95e2e 1067 p_response = NULL;
1068
254b70a4 1069 // Okay, look at the command now.
1070 lastorder = order;
0194ce8f 1071 if(receivedCmd[0] == ISO14443A_CMD_REQA) { // Received a REQUEST
ce02f6f9 1072 p_response = &responses[0]; order = 1;
0194ce8f 1073 } else if(receivedCmd[0] == ISO14443A_CMD_WUPA) { // Received a WAKEUP
ce02f6f9 1074 p_response = &responses[0]; order = 6;
0194ce8f 1075 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received request for UID (cascade 1)
ce02f6f9 1076 p_response = &responses[1]; order = 2;
0194ce8f 1077 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received request for UID (cascade 2)
ce02f6f9 1078 p_response = &responses[2]; order = 20;
0194ce8f 1079 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received a SELECT (cascade 1)
ce02f6f9 1080 p_response = &responses[3]; order = 3;
0194ce8f 1081 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received a SELECT (cascade 2)
1082 p_response = &responses[4]; order = 30;
1083 } else if(receivedCmd[0] == ISO14443A_CMD_READBLOCK) { // Received a (plain) READ
32719adf 1084 uint8_t block = receivedCmd[1];
2b1f4228 1085 // if Ultralight or NTAG (4 byte blocks)
1086 if ( tagType == 7 || tagType == 2 ) {
f38cfd66 1087 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
2b1f4228 1088 uint16_t start = 4 * (block+12);
6b23be6b 1089 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1090 emlGetMemBt( emdata, start, 16);
1091 AppendCrc14443a(emdata, 16);
1092 EmSendCmdEx(emdata, sizeof(emdata), false);
2b1f4228 1093 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
32719adf 1094 p_response = NULL;
2b1f4228 1095 } else { // all other tags (16 byte block tags)
6b23be6b 1096 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1097 emlGetMemBt( emdata, block, 16);
1098 AppendCrc14443a(emdata, 16);
1099 EmSendCmdEx(emdata, sizeof(emdata), false);
f38cfd66 1100 // EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
32719adf 1101 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1102 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1103 p_response = NULL;
1104 }
0194ce8f 1105 } else if(receivedCmd[0] == MIFARE_ULEV1_FASTREAD) { // Received a FAST READ (ranged read)
91c7a7cc 1106 uint8_t emdata[MAX_FRAME_SIZE];
f38cfd66 1107 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
91c7a7cc 1108 int start = (receivedCmd[1]+12) * 4;
1109 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
1110 emlGetMemBt( emdata, start, len);
1111 AppendCrc14443a(emdata, len);
1112 EmSendCmdEx(emdata, len+2, false);
1113 p_response = NULL;
0194ce8f 1114 } else if(receivedCmd[0] == MIFARE_ULEV1_READSIG && tagType == 7) { // Received a READ SIGNATURE --
f38cfd66 1115 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
91c7a7cc 1116 uint16_t start = 4 * 4;
1117 uint8_t emdata[34];
1118 emlGetMemBt( emdata, start, 32);
1119 AppendCrc14443a(emdata, 32);
1120 EmSendCmdEx(emdata, sizeof(emdata), false);
1121 p_response = NULL;
0194ce8f 1122 } else if (receivedCmd[0] == MIFARE_ULEV1_READ_CNT && tagType == 7) { // Received a READ COUNTER --
e9a92fe2 1123 uint8_t index = receivedCmd[1];
a126332a 1124 uint8_t data[] = {0x00,0x00,0x00,0x14,0xa5};
e9a92fe2 1125 if ( counters[index] > 0) {
1126 num_to_bytes(counters[index], 3, data);
1127 AppendCrc14443a(data, sizeof(data)-2);
1128 }
a126332a 1129 EmSendCmdEx(data,sizeof(data),false);
1130 p_response = NULL;
0194ce8f 1131 } else if (receivedCmd[0] == MIFARE_ULEV1_INCR_CNT && tagType == 7) { // Received a INC COUNTER --
ce3d6bd2 1132 // number of counter
a126332a 1133 uint8_t counter = receivedCmd[1];
1134 uint32_t val = bytes_to_num(receivedCmd+2,4);
1135 counters[counter] = val;
1136
ce3d6bd2 1137 // send ACK
1138 uint8_t ack[] = {0x0a};
1139 EmSendCmdEx(ack,sizeof(ack),false);
91c7a7cc 1140 p_response = NULL;
0194ce8f 1141 } else if(receivedCmd[0] == MIFARE_ULEV1_CHECKTEAR && tagType == 7) { // Received a CHECK_TEARING_EVENT --
f38cfd66 1142 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
2b1f4228 1143 uint8_t emdata[3];
1144 uint8_t counter=0;
1145 if (receivedCmd[1]<3) counter = receivedCmd[1];
1146 emlGetMemBt( emdata, 10+counter, 1);
1147 AppendCrc14443a(emdata, sizeof(emdata)-2);
1148 EmSendCmdEx(emdata, sizeof(emdata), false);
b0300679 1149 p_response = NULL;
0194ce8f 1150 } else if(receivedCmd[0] == ISO14443A_CMD_HALT) { // Received a HALT
810f5379 1151 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1152 p_response = NULL;
57850d9d 1153 } else if(receivedCmd[0] == MIFARE_AUTH_KEYA || receivedCmd[0] == MIFARE_AUTH_KEYB) { // Received an authentication request
32719adf 1154 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
2b1f4228 1155 uint8_t emdata[10];
1156 emlGetMemBt( emdata, 0, 8 );
1157 AppendCrc14443a(emdata, sizeof(emdata)-2);
6b23be6b 1158 EmSendCmdEx(emdata, sizeof(emdata), false);
2b1f4228 1159 p_response = NULL;
32719adf 1160 } else {
6b23be6b 1161 cardAUTHSC = receivedCmd[1] / 4; // received block num
1162 cardAUTHKEY = receivedCmd[0] - 0x60;
32719adf 1163 p_response = &responses[5]; order = 7;
1164 }
0194ce8f 1165 } else if(receivedCmd[0] == ISO14443A_CMD_RATS) { // Received a RATS request
7bc95e2e 1166 if (tagType == 1 || tagType == 2) { // RATS not supported
1167 EmSend4bit(CARD_NACK_NA);
1168 p_response = NULL;
1169 } else {
1170 p_response = &responses[6]; order = 70;
1171 }
6a1f2d82 1172 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
810f5379 1173 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1174 uint32_t nr = bytes_to_num(receivedCmd,4);
1175 uint32_t ar = bytes_to_num(receivedCmd+4,4);
d26849d4 1176
6b23be6b 1177 // Collect AR/NR per keytype & sector
bc939371 1178 if ( (flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) {
bf5d7992 1179
6b23be6b 1180 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
bf5d7992 1181
1182 if ( ar_nr_collected[i+mM] == 0 || (
1183 (cardAUTHSC == ar_nr_resp[i+mM].sector) &&
1184 (cardAUTHKEY == ar_nr_resp[i+mM].keytype) &&
1185 (ar_nr_collected[i+mM] > 0)
1186 )
1187 ) {
1188
6b23be6b 1189 // if first auth for sector, or matches sector and keytype of previous auth
1190 if (ar_nr_collected[i+mM] < 2) {
1191 // if we haven't already collected 2 nonces for this sector
1192 if (ar_nr_resp[ar_nr_collected[i+mM]].ar != ar) {
1193 // Avoid duplicates... probably not necessary, ar should vary.
1194 if (ar_nr_collected[i+mM]==0) {
1195 // first nonce collect
1196 ar_nr_resp[i+mM].cuid = cuid;
1197 ar_nr_resp[i+mM].sector = cardAUTHSC;
1198 ar_nr_resp[i+mM].keytype = cardAUTHKEY;
1199 ar_nr_resp[i+mM].nonce = nonce;
1200 ar_nr_resp[i+mM].nr = nr;
1201 ar_nr_resp[i+mM].ar = ar;
1202 nonce1_count++;
1203 // add this nonce to first moebius nonce
1204 ar_nr_resp[i+ATTACK_KEY_COUNT].cuid = cuid;
1205 ar_nr_resp[i+ATTACK_KEY_COUNT].sector = cardAUTHSC;
1206 ar_nr_resp[i+ATTACK_KEY_COUNT].keytype = cardAUTHKEY;
1207 ar_nr_resp[i+ATTACK_KEY_COUNT].nonce = nonce;
1208 ar_nr_resp[i+ATTACK_KEY_COUNT].nr = nr;
1209 ar_nr_resp[i+ATTACK_KEY_COUNT].ar = ar;
1210 ar_nr_collected[i+ATTACK_KEY_COUNT]++;
1211 } else { // second nonce collect (std and moebius)
1212 ar_nr_resp[i+mM].nonce2 = nonce;
1213 ar_nr_resp[i+mM].nr2 = nr;
1214 ar_nr_resp[i+mM].ar2 = ar;
1215 if (!gettingMoebius) {
1216 nonce2_count++;
1217 // check if this was the last second nonce we need for std attack
1218 if ( nonce2_count == nonce1_count ) {
1219 // done collecting std test switch to moebius
1220 // first finish incrementing last sample
1221 ar_nr_collected[i+mM]++;
1222 // switch to moebius collection
1223 gettingMoebius = true;
1224 mM = ATTACK_KEY_COUNT;
1225 break;
1226 }
1227 } else {
1228 moebius_n_count++;
1229 // if we've collected all the nonces we need - finish.
1230 if (nonce1_count == moebius_n_count) {
1231 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_resp,sizeof(ar_nr_resp));
1232 nonce1_count = 0;
1233 nonce2_count = 0;
1234 moebius_n_count = 0;
1235 gettingMoebius = false;
1236 }
1237 }
1238 }
1239 ar_nr_collected[i+mM]++;
1240 }
1241 }
1242 // we found right spot for this nonce stop looking
1243 break;
1244 }
d26849d4 1245 }
d26849d4 1246 }
57850d9d 1247
0194ce8f 1248 } else if (receivedCmd[0] == MIFARE_ULC_AUTH_1 ) { // ULC authentication, or Desfire Authentication
1249 } else if (receivedCmd[0] == MIFARE_ULEV1_AUTH) { // NTAG / EV-1 authentication
32719adf 1250 if ( tagType == 7 ) {
f38cfd66 1251 uint16_t start = 13; // first 4 blocks of emu are [getversion answer - check tearing - pack - 0x00]
2b1f4228 1252 uint8_t emdata[4];
1253 emlGetMemBt( emdata, start, 2);
1254 AppendCrc14443a(emdata, 2);
1255 EmSendCmdEx(emdata, sizeof(emdata), false);
1256 p_response = NULL;
ce3d6bd2 1257 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
e98572a1 1258
91c7a7cc 1259 if ( MF_DBGLEVEL >= 3) Dbprintf("Auth attempt: %08x", pwd);
32719adf 1260 }
2b1f4228 1261 } else {
7bc95e2e 1262 // Check for ISO 14443A-4 compliant commands, look at left nibble
1263 switch (receivedCmd[0]) {
7838f4be 1264 case 0x02:
1265 case 0x03: { // IBlock (command no CID)
1266 dynamic_response_info.response[0] = receivedCmd[0];
1267 dynamic_response_info.response[1] = 0x90;
1268 dynamic_response_info.response[2] = 0x00;
1269 dynamic_response_info.response_n = 3;
1270 } break;
7bc95e2e 1271 case 0x0B:
7838f4be 1272 case 0x0A: { // IBlock (command CID)
7bc95e2e 1273 dynamic_response_info.response[0] = receivedCmd[0];
1274 dynamic_response_info.response[1] = 0x00;
1275 dynamic_response_info.response[2] = 0x90;
1276 dynamic_response_info.response[3] = 0x00;
1277 dynamic_response_info.response_n = 4;
1278 } break;
1279
1280 case 0x1A:
1281 case 0x1B: { // Chaining command
1282 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1283 dynamic_response_info.response_n = 2;
1284 } break;
1285
1286 case 0xaa:
1287 case 0xbb: {
1288 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1289 dynamic_response_info.response_n = 2;
1290 } break;
1291
7838f4be 1292 case 0xBA: { // ping / pong
1293 dynamic_response_info.response[0] = 0xAB;
1294 dynamic_response_info.response[1] = 0x00;
1295 dynamic_response_info.response_n = 2;
7bc95e2e 1296 } break;
1297
1298 case 0xCA:
1299 case 0xC2: { // Readers sends deselect command
7838f4be 1300 dynamic_response_info.response[0] = 0xCA;
1301 dynamic_response_info.response[1] = 0x00;
1302 dynamic_response_info.response_n = 2;
7bc95e2e 1303 } break;
1304
1305 default: {
1306 // Never seen this command before
810f5379 1307 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1308 Dbprintf("Received unknown command (len=%d):",len);
1309 Dbhexdump(len,receivedCmd,false);
1310 // Do not respond
1311 dynamic_response_info.response_n = 0;
1312 } break;
1313 }
ce02f6f9 1314
7bc95e2e 1315 if (dynamic_response_info.response_n > 0) {
1316 // Copy the CID from the reader query
1317 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1318
7bc95e2e 1319 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1320 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1321 dynamic_response_info.response_n += 2;
ce02f6f9 1322
7bc95e2e 1323 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1324 Dbprintf("Error preparing tag response");
810f5379 1325 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1326 break;
1327 }
1328 p_response = &dynamic_response_info;
1329 }
81cd0474 1330 }
15c4dc5a 1331
1332 // Count number of wakeups received after a halt
1333 if(order == 6 && lastorder == 5) { happened++; }
1334
1335 // Count number of other messages after a halt
1336 if(order != 6 && lastorder == 5) { happened2++; }
1337
bc939371 1338 // comment this limit if you want to simulation longer
1339 if (!tracing) {
1340 Dbprintf("Trace Full. Simulation stopped.");
1341 break;
1342 }
91c7a7cc 1343 // comment this limit if you want to simulation longer
15c4dc5a 1344 if(cmdsRecvd > 999) {
1345 DbpString("1000 commands later...");
254b70a4 1346 break;
15c4dc5a 1347 }
ce02f6f9 1348 cmdsRecvd++;
1349
1350 if (p_response != NULL) {
7bc95e2e 1351 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1352 // do the tracing for the previous reader request and this tag answer:
810f5379 1353 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1354 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1355
7bc95e2e 1356 EmLogTrace(Uart.output,
1357 Uart.len,
1358 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1359 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1360 Uart.parity,
7bc95e2e 1361 p_response->response,
1362 p_response->response_n,
1363 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1364 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1365 par);
7bc95e2e 1366 }
7bc95e2e 1367 }
15c4dc5a 1368
d26849d4 1369 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 1370 set_tracing(FALSE);
f71f4deb 1371 BigBuf_free_keep_EM();
c9216a92 1372 LED_A_OFF();
1373
bf5d7992 1374 if(flags & FLAG_NR_AR_ATTACK && MF_DBGLEVEL >= 1) {
6b23be6b 1375 for ( uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
1376 if (ar_nr_collected[i] == 2) {
1377 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
1378 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
1379 ar_nr_resp[i].cuid, //UID
1380 ar_nr_resp[i].nonce, //NT
1381 ar_nr_resp[i].nr, //NR1
1382 ar_nr_resp[i].ar, //AR1
1383 ar_nr_resp[i].nr2, //NR2
1384 ar_nr_resp[i].ar2 //AR2
1385 );
1386 }
1387 }
1388 for ( uint8_t i = ATTACK_KEY_COUNT; i < ATTACK_KEY_COUNT*2; i++) {
1389 if (ar_nr_collected[i] == 2) {
1390 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
1391 Dbprintf("../tools/mfkey/mfkey32v2 %08x %08x %08x %08x %08x %08x %08x",
1392 ar_nr_resp[i].cuid, //UID
1393 ar_nr_resp[i].nonce, //NT
1394 ar_nr_resp[i].nr, //NR1
1395 ar_nr_resp[i].ar, //AR1
1396 ar_nr_resp[i].nonce2,//NT2
1397 ar_nr_resp[i].nr2, //NR2
1398 ar_nr_resp[i].ar2 //AR2
1399 );
1400 }
1401 }
1402 }
1403
0de8e387 1404 if (MF_DBGLEVEL >= 4){
5ee53a0e 1405 Dbprintf("-[ Wake ups after halt [%d]", happened);
1406 Dbprintf("-[ Messages after halt [%d]", happened2);
1407 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
0de8e387 1408 }
15c4dc5a 1409}
1410
9492e0b0 1411// prepare a delayed transfer. This simply shifts ToSend[] by a number
1412// of bits specified in the delay parameter.
0194ce8f 1413void PrepareDelayedTransfer(uint16_t delay) {
7504dc50 1414 delay &= 0x07;
1415 if (!delay) return;
1416
9492e0b0 1417 uint8_t bitmask = 0;
1418 uint8_t bits_to_shift = 0;
1419 uint8_t bits_shifted = 0;
7504dc50 1420 uint16_t i = 0;
1421
1422 for (i = 0; i < delay; ++i)
1423 bitmask |= (0x01 << i);
2285d9dd 1424
6fc68747 1425 ToSend[++ToSendMax] = 0x00;
7504dc50 1426
1427 for (i = 0; i < ToSendMax; ++i) {
9492e0b0 1428 bits_to_shift = ToSend[i] & bitmask;
1429 ToSend[i] = ToSend[i] >> delay;
1430 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1431 bits_shifted = bits_to_shift;
1432 }
1433 }
9492e0b0 1434
7bc95e2e 1435
1436//-------------------------------------------------------------------------------------
15c4dc5a 1437// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1438// Parameter timing:
7bc95e2e 1439// if NULL: transfer at next possible time, taking into account
1440// request guard time and frame delay time
1441// if == 0: transfer immediately and return time of transfer
9492e0b0 1442// if != 0: delay transfer until time specified
7bc95e2e 1443//-------------------------------------------------------------------------------------
0194ce8f 1444static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing) {
9492e0b0 1445 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1446
7bc95e2e 1447 uint32_t ThisTransferTime = 0;
e30c654b 1448
9492e0b0 1449 if (timing) {
ca5bad3d 1450 if(*timing == 0) { // Measure time
7bc95e2e 1451 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
ca5bad3d 1452 } else {
1453 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1454 }
1455 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1456 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
7bc95e2e 1457 LastTimeProxToAirStart = *timing;
1458 } else {
1459 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
7504dc50 1460
7bc95e2e 1461 while(GetCountSspClk() < ThisTransferTime);
7504dc50 1462
7bc95e2e 1463 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1464 }
1465
7bc95e2e 1466 // clear TXRDY
1467 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1468
7bc95e2e 1469 uint16_t c = 0;
9492e0b0 1470 for(;;) {
1471 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1472 AT91C_BASE_SSC->SSC_THR = cmd[c];
4c0cf2d2 1473 ++c;
5ebcb867 1474 if(c >= len)
9492e0b0 1475 break;
9492e0b0 1476 }
1477 }
7bc95e2e 1478
1479 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1480}
1481
15c4dc5a 1482//-----------------------------------------------------------------------------
195af472 1483// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1484//-----------------------------------------------------------------------------
6b23be6b 1485void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity) {
7bc95e2e 1486 int i, j;
5ebcb867 1487 int last = 0;
7bc95e2e 1488 uint8_t b;
e30c654b 1489
7bc95e2e 1490 ToSendReset();
e30c654b 1491
7bc95e2e 1492 // Start of Communication (Seq. Z)
1493 ToSend[++ToSendMax] = SEC_Z;
1494 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
7bc95e2e 1495
1496 size_t bytecount = nbytes(bits);
1497 // Generate send structure for the data bits
1498 for (i = 0; i < bytecount; i++) {
1499 // Get the current byte to send
1500 b = cmd[i];
1501 size_t bitsleft = MIN((bits-(i*8)),8);
1502
1503 for (j = 0; j < bitsleft; j++) {
1504 if (b & 1) {
1505 // Sequence X
1506 ToSend[++ToSendMax] = SEC_X;
1507 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1508 last = 1;
1509 } else {
1510 if (last == 0) {
1511 // Sequence Z
1512 ToSend[++ToSendMax] = SEC_Z;
1513 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1514 } else {
1515 // Sequence Y
1516 ToSend[++ToSendMax] = SEC_Y;
1517 last = 0;
1518 }
1519 }
1520 b >>= 1;
1521 }
1522
6a1f2d82 1523 // Only transmit parity bit if we transmitted a complete byte
0ec548dc 1524 if (j == 8 && parity != NULL) {
7bc95e2e 1525 // Get the parity bit
6a1f2d82 1526 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1527 // Sequence X
1528 ToSend[++ToSendMax] = SEC_X;
1529 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1530 last = 1;
1531 } else {
1532 if (last == 0) {
1533 // Sequence Z
1534 ToSend[++ToSendMax] = SEC_Z;
1535 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1536 } else {
1537 // Sequence Y
1538 ToSend[++ToSendMax] = SEC_Y;
1539 last = 0;
1540 }
1541 }
1542 }
1543 }
e30c654b 1544
7bc95e2e 1545 // End of Communication: Logic 0 followed by Sequence Y
1546 if (last == 0) {
1547 // Sequence Z
1548 ToSend[++ToSendMax] = SEC_Z;
1549 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1550 } else {
1551 // Sequence Y
1552 ToSend[++ToSendMax] = SEC_Y;
1553 last = 0;
1554 }
1555 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1556
7bc95e2e 1557 // Convert to length of command:
4b78d6b3 1558 ++ToSendMax;
15c4dc5a 1559}
1560
195af472 1561//-----------------------------------------------------------------------------
1562// Prepare reader command to send to FPGA
1563//-----------------------------------------------------------------------------
0194ce8f 1564void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity) {
ca5bad3d 1565 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1566}
1567
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1568//-----------------------------------------------------------------------------
1569// Wait for commands from reader
1570// Stop when button is pressed (return 1) or field was gone (return 2)
1571// Or return 0 when command is captured
1572//-----------------------------------------------------------------------------
0194ce8f 1573static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity) {
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1574 *len = 0;
1575
1576 uint32_t timer = 0, vtime = 0;
1577 int analogCnt = 0;
1578 int analogAVG = 0;
1579
1580 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1581 // only, since we are receiving, not transmitting).
1582 // Signal field is off with the appropriate LED
1583 LED_D_OFF();
1584 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1585
1586 // Set ADC to read field strength
1587 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1588 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1589 ADC_MODE_PRESCALE(63) |
1590 ADC_MODE_STARTUP_TIME(1) |
1591 ADC_MODE_SAMPLE_HOLD_TIME(15);
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1592 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1593 // start ADC
1594 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1595
1596 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1597 UartInit(received, parity);
7bc95e2e 1598
1599 // Clear RXRDY:
1600 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1601
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1602 for(;;) {
1603 WDT_HIT();
1604
1605 if (BUTTON_PRESS()) return 1;
1606
1607 // test if the field exists
1608 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1609 analogCnt++;
1610 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1611 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1612 if (analogCnt >= 32) {
0c8d25eb 1613 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
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1614 vtime = GetTickCount();
1615 if (!timer) timer = vtime;
1616 // 50ms no field --> card to idle state
1617 if (vtime - timer > 50) return 2;
1618 } else
1619 if (timer) timer = 0;
1620 analogCnt = 0;
1621 analogAVG = 0;
1622 }
1623 }
7bc95e2e 1624
9ca155ba 1625 // receive and test the miller decoding
7bc95e2e 1626 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1627 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1628 if(MillerDecoding(b, 0)) {
1629 *len = Uart.len;
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1630 return 0;
1631 }
7bc95e2e 1632 }
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1633 }
1634}
1635
0194ce8f 1636int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded) {
7bc95e2e 1637 uint8_t b;
1638 uint16_t i = 0;
1639 uint32_t ThisTransferTime;
1640
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1641 // Modulate Manchester
1642 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1643
1644 // include correction bit if necessary
1645 if (Uart.parityBits & 0x01) {
1646 correctionNeeded = TRUE;
1647 }
0194ce8f 1648 // 1236, so correction bit needed
1649 i = (correctionNeeded) ? 0 : 1;
7bc95e2e 1650
d714d3ef 1651 // clear receiving shift register and holding register
7bc95e2e 1652 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1653 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1654 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1655 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1656
7bc95e2e 1657 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
b070f4e4 1658 for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
7bc95e2e 1659 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1660 if (AT91C_BASE_SSC->SSC_RHR) break;
1661 }
1662
1663 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1664
1665 // Clear TXRDY:
1666 AT91C_BASE_SSC->SSC_THR = SEC_F;
1667
9ca155ba 1668 // send cycle
bb42a03e 1669 for(; i < respLen; ) {
9ca155ba 1670 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1671 AT91C_BASE_SSC->SSC_THR = resp[i++];
1672 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1673 }
7bc95e2e 1674
17ad0e09 1675 if(BUTTON_PRESS()) break;
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1676 }
1677
7bc95e2e 1678 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
4b78d6b3 1679 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3; // twich /8 ?? >>3,
0c8d25eb 1680 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
7bc95e2e 1681 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1682 AT91C_BASE_SSC->SSC_THR = SEC_F;
1683 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1684 i++;
1685 }
1686 }
7bc95e2e 1687 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
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1688 return 0;
1689}
1690
7bc95e2e 1691int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1692 Code4bitAnswerAsTag(resp);
0a39986e 1693 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1694 // do the tracing for the previous reader request and this tag answer:
5ebcb867 1695 uint8_t par[1] = {0x00};
6a1f2d82 1696 GetParity(&resp, 1, par);
7bc95e2e 1697 EmLogTrace(Uart.output,
1698 Uart.len,
1699 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1700 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1701 Uart.parity,
7bc95e2e 1702 &resp,
1703 1,
1704 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1705 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1706 par);
0a39986e 1707 return res;
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1708}
1709
8f51ddb0 1710int EmSend4bit(uint8_t resp){
7bc95e2e 1711 return EmSend4bitEx(resp, false);
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1712}
1713
6a1f2d82 1714int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1715 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1716 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1717 // do the tracing for the previous reader request and this tag answer:
1718 EmLogTrace(Uart.output,
1719 Uart.len,
1720 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1721 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1722 Uart.parity,
7bc95e2e 1723 resp,
1724 respLen,
1725 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1726 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1727 par);
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1728 return res;
1729}
1730
6a1f2d82 1731int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
5ebcb867 1732 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1733 GetParity(resp, respLen, par);
1734 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
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1735}
1736
6a1f2d82 1737int EmSendCmd(uint8_t *resp, uint16_t respLen){
5ebcb867 1738 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1739 GetParity(resp, respLen, par);
1740 return EmSendCmdExPar(resp, respLen, false, par);
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1741}
1742
6a1f2d82 1743int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1744 return EmSendCmdExPar(resp, respLen, false, par);
1745}
1746
6a1f2d82 1747bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1748 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1749{
810f5379 1750 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1751 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1752 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1753 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1754 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1755 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1756 reader_EndTime = tag_StartTime - exact_fdt;
1757 reader_StartTime = reader_EndTime - reader_modlen;
5ebcb867 1758
810f5379 1759 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE))
1760 return FALSE;
1761 else
1762 return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1763
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1764}
1765
15c4dc5a 1766//-----------------------------------------------------------------------------
1767// Wait a certain time for tag response
1768// If a response is captured return TRUE
e691fc45 1769// If it takes too long return FALSE
15c4dc5a 1770//-----------------------------------------------------------------------------
0194ce8f 1771static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset) {
46c65fed 1772 uint32_t c = 0x00;
e691fc45 1773
15c4dc5a 1774 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1775 // only, since we are receiving, not transmitting).
1776 // Signal field is on with the appropriate LED
1777 LED_D_ON();
1778 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1779
534983d7 1780 // Now get the answer from the card
6a1f2d82 1781 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1782
7bc95e2e 1783 // clear RXRDY:
1784 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1785
15c4dc5a 1786 for(;;) {
534983d7 1787 WDT_HIT();
15c4dc5a 1788
534983d7 1789 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1790 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1791 if(ManchesterDecoding(b, offset, 0)) {
1792 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1793 return TRUE;
19a700a8 1794 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
7bc95e2e 1795 return FALSE;
15c4dc5a 1796 }
534983d7 1797 }
1798 }
15c4dc5a 1799}
1800
0194ce8f 1801void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing) {
72e6d462 1802
6a1f2d82 1803 CodeIso14443aBitsAsReaderPar(frame, bits, par);
7bc95e2e 1804 // Send command to tag
1805 TransmitFor14443a(ToSend, ToSendMax, timing);
0194ce8f 1806 if(trigger) LED_A_ON();
dfc3c505 1807
4b78d6b3 1808 LogTrace(frame, nbytes(bits), (LastTimeProxToAirStart<<4) + DELAY_ARM2AIR_AS_READER, ((LastTimeProxToAirStart + LastProxToAirDuration)<<4) + DELAY_ARM2AIR_AS_READER, par, TRUE);
15c4dc5a 1809}
1810
0194ce8f 1811void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing) {
ca5bad3d 1812 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1813}
15c4dc5a 1814
0194ce8f 1815void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing) {
72e6d462 1816 // Generate parity and redirect
1817 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1818 GetParity(frame, len/8, par);
1819 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1820}
1821
0194ce8f 1822void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing) {
72e6d462 1823 // Generate parity and redirect
1824 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1825 GetParity(frame, len, par);
1826 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1827}
1828
0194ce8f 1829int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity) {
1830 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset))
1831 return FALSE;
1832 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
e691fc45 1833 return Demod.len;
1834}
1835
91c7a7cc 1836int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity) {
0194ce8f 1837 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0))
1838 return FALSE;
91c7a7cc 1839 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
e691fc45 1840 return Demod.len;
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M
1841}
1842
c188b1b9 1843// performs iso14443a anticollision (optional) and card select procedure
1844// fills the uid and cuid pointer unless NULL
1845// fills the card info record unless NULL
1846// if anticollision is false, then the UID must be provided in uid_ptr[]
1847// and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1848int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades) {
f8850434 1849 uint8_t wupa[] = { ISO14443A_CMD_WUPA }; // 0x26 - ISO14443A_CMD_REQA 0x52 - ISO14443A_CMD_WUPA
1850 uint8_t sel_all[] = { ISO14443A_CMD_ANTICOLL_OR_SELECT,0x20 };
1851 uint8_t sel_uid[] = { ISO14443A_CMD_ANTICOLL_OR_SELECT,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1852 uint8_t rats[] = { ISO14443A_CMD_RATS,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
4c0cf2d2 1853 uint8_t resp[MAX_FRAME_SIZE] = {0}; // theoretically. A usual RATS will be much smaller
1854 uint8_t resp_par[MAX_PARITY_SIZE] = {0};
1855 byte_t uid_resp[4] = {0};
1856 size_t uid_resp_len = 0;
6a1f2d82 1857
1858 uint8_t sak = 0x04; // cascade uid
1859 int cascade_level = 0;
1860 int len;
1861
1862 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
c188b1b9 1863 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
7bc95e2e 1864
6a1f2d82 1865 // Receive the ATQA
1866 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1867
1868 if(p_hi14a_card) {
1869 memcpy(p_hi14a_card->atqa, resp, 2);
1870 p_hi14a_card->uidlen = 0;
1871 memset(p_hi14a_card->uid,0,10);
1872 }
5f6d6c90 1873
c188b1b9 1874 if (anticollision) {
4c0cf2d2 1875 // clear uid
1876 if (uid_ptr)
1877 memset(uid_ptr,0,10);
c188b1b9 1878 }
79a73ab2 1879
5fba8581 1880 // reset the PCB block number
1881 iso14_pcb_blocknum = 0;
1882
0ec548dc 1883 // check for proprietary anticollision:
4c0cf2d2 1884 if ((resp[0] & 0x1F) == 0) return 3;
0ec548dc 1885
6a1f2d82 1886 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1887 // which case we need to make a cascade 2 request and select - this is a long UID
1888 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1889 for(; sak & 0x04; cascade_level++) {
1890 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1891 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1892
c188b1b9 1893 if (anticollision) {
6a1f2d82 1894 // SELECT_ALL
4c0cf2d2 1895 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1896 if (!ReaderReceive(resp, resp_par)) return 0;
1897
1898 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1899 memset(uid_resp, 0, 4);
1900 uint16_t uid_resp_bits = 0;
1901 uint16_t collision_answer_offset = 0;
1902 // anti-collision-loop:
1903 while (Demod.collisionPos) {
1904 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1905 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1906 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1907 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1908 }
1909 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1910 uid_resp_bits++;
1911 // construct anticollosion command:
1912 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1913 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1914 sel_uid[2+i] = uid_resp[i];
1915 }
1916 collision_answer_offset = uid_resp_bits%8;
1917 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1918 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
6a1f2d82 1919 }
4c0cf2d2 1920 // finally, add the last bits and BCC of the UID
1921 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1922 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1923 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1924 }
e691fc45 1925
4c0cf2d2 1926 } else { // no collision, use the response to SELECT_ALL as current uid
1927 memcpy(uid_resp, resp, 4);
1928 }
1929
c188b1b9 1930 } else {
1931 if (cascade_level < num_cascades - 1) {
1932 uid_resp[0] = 0x88;
1933 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1934 } else {
1935 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1936 }
1937 }
6a1f2d82 1938 uid_resp_len = 4;
5f6d6c90 1939
6a1f2d82 1940 // calculate crypto UID. Always use last 4 Bytes.
4c0cf2d2 1941 if(cuid_ptr)
6a1f2d82 1942 *cuid_ptr = bytes_to_num(uid_resp, 4);
e30c654b 1943
6a1f2d82 1944 // Construct SELECT UID command
1945 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
c188b1b9 1946 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
6a1f2d82 1947 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1948 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1949 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1950
1951 // Receive the SAK
1952 if (!ReaderReceive(resp, resp_par)) return 0;
4c0cf2d2 1953
6a1f2d82 1954 sak = resp[0];
1955
810f5379 1956 // Test if more parts of the uid are coming
6a1f2d82 1957 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1958 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1959 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1960 uid_resp[0] = uid_resp[1];
1961 uid_resp[1] = uid_resp[2];
1962 uid_resp[2] = uid_resp[3];
6a1f2d82 1963 uid_resp_len = 3;
1964 }
5f6d6c90 1965
4c0cf2d2 1966 if(uid_ptr && anticollision)
6a1f2d82 1967 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
5f6d6c90 1968
6a1f2d82 1969 if(p_hi14a_card) {
1970 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1971 p_hi14a_card->uidlen += uid_resp_len;
1972 }
1973 }
79a73ab2 1974
6a1f2d82 1975 if(p_hi14a_card) {
1976 p_hi14a_card->sak = sak;
1977 p_hi14a_card->ats_len = 0;
1978 }
534983d7 1979
3fe4ff4f 1980 // non iso14443a compliant tag
1981 if( (sak & 0x20) == 0) return 2;
534983d7 1982
6a1f2d82 1983 // Request for answer to select
1984 AppendCrc14443a(rats, 2);
1985 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1986
6a1f2d82 1987 if (!(len = ReaderReceive(resp, resp_par))) return 0;
3fe4ff4f 1988
6a1f2d82 1989 if(p_hi14a_card) {
1990 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1991 p_hi14a_card->ats_len = len;
1992 }
5f6d6c90 1993
19a700a8 1994 // set default timeout based on ATS
1995 iso14a_set_ATS_timeout(resp);
6a1f2d82 1996 return 1;
7e758047 1997}
15c4dc5a 1998
7bc95e2e 1999void iso14443a_setup(uint8_t fpga_minor_mode) {
be818b14 2000
7cc204bf 2001 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 2002 // Set up the synchronous serial port
2003 FpgaSetupSsc();
7bc95e2e 2004 // connect Demodulated Signal to ADC:
7e758047 2005 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
91c7a7cc 2006
ca5bad3d 2007 LED_D_OFF();
7e758047 2008 // Signal field is on with the appropriate LED
ca5bad3d 2009 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD ||
2010 fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN)
7bc95e2e 2011 LED_D_ON();
6fc68747 2012
be818b14 2013 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
d5bded10 2014
2015 SpinDelay(20);
6fc68747 2016
2017 // Start the timer
2018 StartCountSspClk();
be818b14 2019
2020 // Prepare the demodulation functions
2021 DemodReset();
2022 UartReset();
2023 NextTransferTime = 2 * DELAY_ARM2AIR_AS_READER;
d5bded10 2024 iso14a_set_timeout(10*106); // 20ms default
7e758047 2025}
15c4dc5a 2026
6a1f2d82 2027int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
810f5379 2028 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
534983d7 2029 uint8_t real_cmd[cmd_len+4];
2030 real_cmd[0] = 0x0a; //I-Block
b0127e65 2031 // put block number into the PCB
2032 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 2033 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
2034 memcpy(real_cmd+2, cmd, cmd_len);
2035 AppendCrc14443a(real_cmd,cmd_len+2);
2036
9492e0b0 2037 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 2038 size_t len = ReaderReceive(data, parity);
ca5bad3d 2039 //DATA LINK ERROR
2040 if (!len) return 0;
2041
6a1f2d82 2042 uint8_t *data_bytes = (uint8_t *) data;
ca5bad3d 2043
b0127e65 2044 // if we received an I- or R(ACK)-Block with a block number equal to the
2045 // current block number, toggle the current block number
ca5bad3d 2046 if (len >= 4 // PCB+CID+CRC = 4 bytes
b0127e65 2047 && ((data_bytes[0] & 0xC0) == 0 // I-Block
2048 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2049 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
2050 {
2051 iso14_pcb_blocknum ^= 1;
2052 }
2053
534983d7 2054 return len;
2055}
2056
be818b14 2057
7e758047 2058//-----------------------------------------------------------------------------
2059// Read an ISO 14443a tag. Send out commands and store answers.
7e758047 2060//-----------------------------------------------------------------------------
91c7a7cc 2061void ReaderIso14443a(UsbCommand *c) {
534983d7 2062 iso14a_command_t param = c->arg[0];
04bc1c66 2063 size_t len = c->arg[1] & 0xffff;
2064 size_t lenbits = c->arg[1] >> 16;
2065 uint32_t timeout = c->arg[2];
91c7a7cc 2066 uint8_t *cmd = c->d.asBytes;
9492e0b0 2067 uint32_t arg0 = 0;
810f5379 2068 byte_t buf[USB_CMD_DATA_SIZE] = {0x00};
2069 uint8_t par[MAX_PARITY_SIZE] = {0x00};
902cb3c0 2070
810f5379 2071 if (param & ISO14A_CONNECT)
3000dc4e 2072 clear_trace();
e691fc45 2073
3000dc4e 2074 set_tracing(TRUE);
e30c654b 2075
810f5379 2076 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 2077 iso14a_set_trigger(TRUE);
15c4dc5a 2078
810f5379 2079 if (param & ISO14A_CONNECT) {
7bc95e2e 2080 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 2081 if(!(param & ISO14A_NO_SELECT)) {
2082 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
c188b1b9 2083 arg0 = iso14443a_select_card(NULL,card,NULL, true, 0);
91c7a7cc 2084 cmd_send(CMD_ACK, arg0, card->uidlen, 0, buf, sizeof(iso14a_card_select_t));
6fc68747 2085 // if it fails, the cmdhf14a.c client quites.. however this one still executes.
2086 if ( arg0 == 0 ) return;
5f6d6c90 2087 }
534983d7 2088 }
e30c654b 2089
810f5379 2090 if (param & ISO14A_SET_TIMEOUT)
04bc1c66 2091 iso14a_set_timeout(timeout);
e30c654b 2092
810f5379 2093 if (param & ISO14A_APDU) {
902cb3c0 2094 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 2095 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2096 }
e30c654b 2097
810f5379 2098 if (param & ISO14A_RAW) {
0f7279b2 2099 if (param & ISO14A_APPEND_CRC) {
2100 if (param & ISO14A_TOPAZMODE)
0ec548dc 2101 AppendCrc14443b(cmd,len);
0f7279b2 2102 else
d26849d4 2103 AppendCrc14443a(cmd,len);
0f7279b2 2104
534983d7 2105 len += 2;
c7324bef 2106 if (lenbits) lenbits += 16;
15c4dc5a 2107 }
0f7279b2 2108 if (lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2109 if (param & ISO14A_TOPAZMODE) {
0ec548dc 2110 int bits_to_send = lenbits;
2111 uint16_t i = 0;
2112 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2113 bits_to_send -= 7;
2114 while (bits_to_send > 0) {
2115 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2116 bits_to_send -= 8;
2117 }
2118 } else {
6a1f2d82 2119 GetParity(cmd, lenbits/8, par);
0ec548dc 2120 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2121 }
2122 } else { // want to send complete bytes only
0f7279b2 2123 if (param & ISO14A_TOPAZMODE) {
0ec548dc 2124 uint16_t i = 0;
2125 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2126 while (i < len) {
2127 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2128 }
5f6d6c90 2129 } else {
0ec548dc 2130 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2131 }
5f6d6c90 2132 }
6a1f2d82 2133 arg0 = ReaderReceive(buf, par);
9492e0b0 2134 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2135 }
15c4dc5a 2136
810f5379 2137 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 2138 iso14a_set_trigger(FALSE);
15c4dc5a 2139
810f5379 2140 if (param & ISO14A_NO_DISCONNECT)
534983d7 2141 return;
15c4dc5a 2142
15c4dc5a 2143 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 2144 set_tracing(FALSE);
15c4dc5a 2145 LEDsoff();
15c4dc5a 2146}
b0127e65 2147
1c611bbd 2148// Determine the distance between two nonces.
2149// Assume that the difference is small, but we don't know which is first.
2150// Therefore try in alternating directions.
2151int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2152
ca5bad3d 2153 if (nt1 == nt2) return 0;
ca5bad3d 2154
91c7a7cc 2155 uint32_t nttmp1 = nt1;
2156 uint32_t nttmp2 = nt2;
2157
30daf914 2158 // 0xFFFF -- Half up and half down to find distance between nonces
2159 for (uint16_t i = 1; i < 32768/8; i += 8) {
bc939371 2160 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i;
be818b14 2161 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+1;
be818b14 2162 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+2;
be818b14 2163 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+3;
be818b14 2164 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+4;
be818b14 2165 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+5;
be818b14 2166 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+6;
be818b14 2167 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+7;
30daf914 2168
2169 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -i;
2170 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+1);
2171 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+2);
2172 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+3);
2173 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+4);
2174 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+5);
2175 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+6);
be818b14 2176 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+7);
2177 }
91c7a7cc 2178 // either nt1 or nt2 are invalid nonces
2179 return(-99999);
e772353f 2180}
2181
1c611bbd 2182//-----------------------------------------------------------------------------
2183// Recover several bits of the cypher stream. This implements (first stages of)
2184// the algorithm described in "The Dark Side of Security by Obscurity and
2185// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2186// (article by Nicolas T. Courtois, 2009)
2187//-----------------------------------------------------------------------------
f38cfd66 2188
df007486 2189void ReaderMifare(bool first_try, uint8_t block, uint8_t keytype ) {
2190
2191 uint8_t mf_auth[] = { keytype, block, 0x00, 0x00 };
b0300679 2192 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2193 uint8_t uid[10] = {0,0,0,0,0,0,0,0,0,0};
2194 uint8_t par_list[8] = {0,0,0,0,0,0,0,0};
2195 uint8_t ks_list[8] = {0,0,0,0,0,0,0,0};
495d7f13 2196 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = {0x00};
2197 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b0300679 2198 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2199 byte_t nt_diff = 0;
6a1f2d82 2200 uint32_t nt = 0;
b0300679 2201 uint32_t previous_nt = 0;
b0300679 2202 uint32_t cuid = 0;
2203
91c7a7cc 2204 int32_t catch_up_cycles = 0;
2205 int32_t last_catch_up = 0;
2206 int32_t isOK = 0;
2207 int32_t nt_distance = 0;
b0300679 2208
4c0cf2d2 2209 uint16_t elapsed_prng_sequences = 1;
1c611bbd 2210 uint16_t consecutive_resyncs = 0;
0de8e387 2211 uint16_t unexpected_random = 0;
2212 uint16_t sync_tries = 0;
b0300679 2213
bc939371 2214 // static variables here, is re-used in the next call
b0300679 2215 static uint32_t nt_attacked = 0;
2216 static uint32_t sync_time = 0;
91c7a7cc 2217 static uint32_t sync_cycles = 0;
b0300679 2218 static uint8_t par_low = 0;
2219 static uint8_t mf_nr_ar3 = 0;
91c7a7cc 2220
b0300679 2221 #define PRNG_SEQUENCE_LENGTH (1 << 16)
2222 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2223 #define MAX_SYNC_TRIES 32
df007486 2224
2225 AppendCrc14443a(mf_auth, 2);
2226
91c7a7cc 2227 BigBuf_free(); BigBuf_Clear_ext(false);
4b78d6b3 2228 clear_trace();
5fba8581 2229 set_tracing(FALSE);
91c7a7cc 2230 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
4c0cf2d2 2231
6067df30 2232 sync_time = GetCountSspClk() & 0xfffffff8;
ed8c2aeb 2233 sync_cycles = PRNG_SEQUENCE_LENGTH; // Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
f38cfd66 2234 nt_attacked = 0;
2235
dd83c457 2236 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare::Sync %u", sync_time);
f38cfd66 2237
6067df30 2238 if (first_try) {
f38cfd66 2239 mf_nr_ar3 = 0;
91c7a7cc 2240 par_low = 0;
4c0cf2d2 2241 } else {
b0300679 2242 // we were unsuccessful on a previous call.
2243 // Try another READER nonce (first 3 parity bits remain the same)
2244 ++mf_nr_ar3;
4c0cf2d2 2245 mf_nr_ar[3] = mf_nr_ar3;
2246 par[0] = par_low;
2247 }
91c7a7cc 2248
2249 bool have_uid = FALSE;
2250 uint8_t cascade_levels = 0;
2251
4c0cf2d2 2252 LED_C_ON();
91c7a7cc 2253 uint16_t i;
2254 for(i = 0; TRUE; ++i) {
4c0cf2d2 2255
1c611bbd 2256 WDT_HIT();
e30c654b 2257
1c611bbd 2258 // Test if the action was cancelled
c830303d 2259 if(BUTTON_PRESS()) {
2260 isOK = -1;
1c611bbd 2261 break;
2262 }
2263
91c7a7cc 2264 // this part is from Piwi's faster nonce collecting part in Hardnested.
2265 if (!have_uid) { // need a full select cycle to get the uid first
2266 iso14a_card_select_t card_info;
2267 if(!iso14443a_select_card(uid, &card_info, &cuid, true, 0)) {
2268 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (ALL)");
2269 break;
2270 }
2271 switch (card_info.uidlen) {
2272 case 4 : cascade_levels = 1; break;
2273 case 7 : cascade_levels = 2; break;
2274 case 10: cascade_levels = 3; break;
2275 default: break;
2276 }
2277 have_uid = TRUE;
2278 } else { // no need for anticollision. We can directly select the card
2279 if(!iso14443a_select_card(uid, NULL, &cuid, false, cascade_levels)) {
2280 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (UID)");
2281 continue;
2282 }
1c611bbd 2283 }
4c0cf2d2 2284
91c7a7cc 2285 // Sending timeslot of ISO14443a frame
2286 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles + catch_up_cycles;
4b78d6b3 2287 catch_up_cycles = 0;
2288
2289 // if we missed the sync time already, advance to the next nonce repeat
91c7a7cc 2290 while( GetCountSspClk() > sync_time) {
4b78d6b3 2291 ++elapsed_prng_sequences;
91c7a7cc 2292 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles;
2293 }
2294
2295 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2296 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2297
91c7a7cc 2298 // Receive the (4 Byte) "random" nonce from TAG
4c0cf2d2 2299 if (!ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2300 continue;
1c611bbd 2301
4b78d6b3 2302 previous_nt = nt;
2303 nt = bytes_to_num(receivedAnswer, 4);
2304
91c7a7cc 2305 // Transmit reader nonce with fake par
2306 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2307
6067df30 2308 // we didn't calibrate our clock yet,
2309 // iceman: has to be calibrated every time.
bcacb316 2310 if (previous_nt && !nt_attacked) {
91c7a7cc 2311
2312 nt_distance = dist_nt(previous_nt, nt);
2313
2314 // if no distance between, then we are in sync.
1c611bbd 2315 if (nt_distance == 0) {
2316 nt_attacked = nt;
0de8e387 2317 } else {
c830303d 2318 if (nt_distance == -99999) { // invalid nonce received
91c7a7cc 2319 ++unexpected_random;
3bc7b13d 2320 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
c830303d 2321 isOK = -3; // Card has an unpredictable PRNG. Give up
2322 break;
91c7a7cc 2323 } else {
2324 if (sync_cycles <= 0) sync_cycles += PRNG_SEQUENCE_LENGTH;
2325 LED_B_OFF();
c830303d 2326 continue; // continue trying...
2327 }
1c611bbd 2328 }
4c0cf2d2 2329
0de8e387 2330 if (++sync_tries > MAX_SYNC_TRIES) {
91c7a7cc 2331 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2332 break;
0de8e387 2333 }
4c0cf2d2 2334
4b78d6b3 2335 sync_cycles = (sync_cycles - nt_distance)/elapsed_prng_sequences;
91c7a7cc 2336
4c0cf2d2 2337 if (sync_cycles <= 0)
0de8e387 2338 sync_cycles += PRNG_SEQUENCE_LENGTH;
4c0cf2d2 2339
91c7a7cc 2340 if (MF_DBGLEVEL >= 4)
3bc7b13d 2341 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
4c0cf2d2 2342
91c7a7cc 2343 LED_B_OFF();
1c611bbd 2344 continue;
2345 }
2346 }
91c7a7cc 2347 LED_B_OFF();
1c611bbd 2348
ed8c2aeb 2349 if ( (nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
4c0cf2d2 2350
91c7a7cc 2351 catch_up_cycles = ABS(dist_nt(nt_attacked, nt));
c830303d 2352 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
1c611bbd 2353 catch_up_cycles = 0;
2354 continue;
91c7a7cc 2355 }
4c0cf2d2 2356 // average?
3bc7b13d 2357 catch_up_cycles /= elapsed_prng_sequences;
4c0cf2d2 2358
1c611bbd 2359 if (catch_up_cycles == last_catch_up) {
4a71da5a 2360 ++consecutive_resyncs;
4c0cf2d2 2361 } else {
1c611bbd 2362 last_catch_up = catch_up_cycles;
2363 consecutive_resyncs = 0;
4b78d6b3 2364 }
4c0cf2d2 2365
1c611bbd 2366 if (consecutive_resyncs < 3) {
91c7a7cc 2367 if (MF_DBGLEVEL >= 4)
2368 Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, catch_up_cycles, consecutive_resyncs);
4c0cf2d2 2369 } else {
2370 sync_cycles += catch_up_cycles;
2371
91c7a7cc 2372 if (MF_DBGLEVEL >= 4)
2373 Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, catch_up_cycles, sync_cycles);
4c0cf2d2 2374
3bc7b13d 2375 last_catch_up = 0;
2376 catch_up_cycles = 0;
2377 consecutive_resyncs = 0;
1c611bbd 2378 }
2379 continue;
2380 }
2381
1c611bbd 2382 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
91c7a7cc 2383 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2384 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2385
495d7f13 2386 if (nt_diff == 0)
6a1f2d82 2387 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2388
6a1f2d82 2389 par_list[nt_diff] = SwapBits(par[0], 8);
91c7a7cc 2390 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; // xor with NACK value to get keystream
1c611bbd 2391
2392 // Test if the information is complete
2393 if (nt_diff == 0x07) {
2394 isOK = 1;
2395 break;
2396 }
2397
2398 nt_diff = (nt_diff + 1) & 0x07;
2399 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2400 par[0] = par_low;
4b78d6b3 2401
1c611bbd 2402 } else {
b0300679 2403 // No NACK.
495d7f13 2404 if (nt_diff == 0 && first_try) {
6a1f2d82 2405 par[0]++;
5ebcb867 2406 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
c830303d 2407 isOK = -2;
2408 break;
2409 }
1c611bbd 2410 } else {
b0300679 2411 // Why this?
6a1f2d82 2412 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2413 }
2414 }
4b78d6b3 2415
91c7a7cc 2416 // reset the resyncs since we got a complete transaction on right time.
4b78d6b3 2417 consecutive_resyncs = 0;
91c7a7cc 2418 } // end for loop
1c611bbd 2419
1c611bbd 2420 mf_nr_ar[3] &= 0x1F;
5ebcb867 2421
bc939371 2422 if (MF_DBGLEVEL >= 4) Dbprintf("Number of sent auth requestes: %u", i);
d26849d4 2423
b0300679 2424 uint8_t buf[28] = {0x00};
91c7a7cc 2425 memset(buf, 0x00, sizeof(buf));
b0300679 2426 num_to_bytes(cuid, 4, buf);
1c611bbd 2427 num_to_bytes(nt, 4, buf + 4);
2428 memcpy(buf + 8, par_list, 8);
2429 memcpy(buf + 16, ks_list, 8);
2430 memcpy(buf + 24, mf_nr_ar, 4);
2431
91c7a7cc 2432 cmd_send(CMD_ACK, isOK, 0, 0, buf, sizeof(buf) );
1c611bbd 2433
1c611bbd 2434 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2435 LEDsoff();
99cf19d9 2436 set_tracing(FALSE);
20f9a2a1 2437}
1c611bbd 2438
f38cfd66 2439
0de8e387 2440/**
d2f487af 2441 *MIFARE 1K simulate.
2442 *
2443 *@param flags :
0194ce8f 2444 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2445 * FLAG_4B_UID_IN_DATA - use 4-byte UID in the data-section
2446 * FLAG_7B_UID_IN_DATA - use 7-byte UID in the data-section
2447 * FLAG_10B_UID_IN_DATA - use 10-byte UID in the data-section
2448 * FLAG_UID_IN_EMUL - use 4-byte UID from emulator memory
2449 * FLAG_NR_AR_ATTACK - collect NR_AR responses for bruteforcing later
d2f487af 2450 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2451 */
91c7a7cc 2452void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain) {
50193c1e 2453 int cardSTATE = MFEMUL_NOFIELD;
0194ce8f 2454 int _UID_LEN = 0; // 4, 7, 10
9ca155ba 2455 int vHf = 0; // in mV
0194ce8f 2456 int res = 0;
0a39986e
M
2457 uint32_t selTimer = 0;
2458 uint32_t authTimer = 0;
6a1f2d82 2459 uint16_t len = 0;
8f51ddb0 2460 uint8_t cardWRBL = 0;
9ca155ba
M
2461 uint8_t cardAUTHSC = 0;
2462 uint8_t cardAUTHKEY = 0xff; // no authentication
2463 uint32_t cuid = 0;
51969283 2464 uint32_t ans = 0;
0014cb46
M
2465 uint32_t cardINTREG = 0;
2466 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2467 struct Crypto1State mpcs = {0, 0};
2468 struct Crypto1State *pcs;
2469 pcs = &mpcs;
f38cfd66 2470 uint32_t numReads = 0; // Counts numer of times reader read a block
5ebcb867 2471 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2472 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2473 uint8_t response[MAX_MIFARE_FRAME_SIZE] = {0x00};
2474 uint8_t response_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
9ca155ba 2475
bc939371 2476 uint8_t atqa[] = {0x04, 0x00}; // Mifare classic 1k
2477 uint8_t sak_4[] = {0x0C, 0x00, 0x00}; // CL1 - 4b uid
2478 uint8_t sak_7[] = {0x0C, 0x00, 0x00}; // CL2 - 7b uid
2479 uint8_t sak_10[] = {0x0C, 0x00, 0x00}; // CL3 - 10b uid
f38cfd66 2480 // uint8_t sak[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
0194ce8f 2481
2482 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2483 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2484 uint8_t rUIDBCC3[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2485
bf5d7992 2486 // TAG Nonce - Authenticate response
2487 uint8_t rAUTH_NT[4];
2488 uint32_t nonce = prand();
2489 num_to_bytes(nonce, 4, rAUTH_NT);
2490
f38cfd66 2491 // uint8_t rAUTH_NT[] = {0x55, 0x41, 0x49, 0x92};// nonce from nested? why this?
d2f487af 2492 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
bf5d7992 2493
bc939371 2494 // Here, we collect CUID, NT, NR, AR, CUID2, NT2, NR2, AR2
d2f487af 2495 // This can be used in a reader-only attack.
b6e05350
MF
2496 nonces_t ar_nr_resp[ATTACK_KEY_COUNT*2]; // for 2 separate attack types (nml, moebius)
2497 memset(ar_nr_resp, 0x00, sizeof(ar_nr_resp));
2498
2499 uint8_t ar_nr_collected[ATTACK_KEY_COUNT*2]; // for 2nd attack type (moebius)
2500 memset(ar_nr_collected, 0x00, sizeof(ar_nr_collected));
2501 uint8_t nonce1_count = 0;
2502 uint8_t nonce2_count = 0;
2503 uint8_t moebius_n_count = 0;
2504 bool gettingMoebius = false;
2505 uint8_t mM = 0; // moebius_modifier for collection storage
2506 bool doBufResetNext = false;
0014cb46 2507
f38cfd66 2508 // -- Determine the UID
0194ce8f 2509 // Can be set from emulator memory or incoming data
2510 // Length: 4,7,or 10 bytes
bc939371 2511 if ( (flags & FLAG_UID_IN_EMUL) == FLAG_UID_IN_EMUL)
2512 emlGetMemBt(datain, 0, 10); // load 10bytes from EMUL to the datain pointer. to be used below.
2513
2514 if ( (flags & FLAG_4B_UID_IN_DATA) == FLAG_4B_UID_IN_DATA) {
0194ce8f 2515 memcpy(rUIDBCC1, datain, 4);
2516 _UID_LEN = 4;
bc939371 2517 } else if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA) {
0194ce8f 2518 memcpy(&rUIDBCC1[1], datain, 3);
2519 memcpy( rUIDBCC2, datain+3, 4);
2520 _UID_LEN = 7;
bc939371 2521 } else if ( (flags & FLAG_10B_UID_IN_DATA) == FLAG_10B_UID_IN_DATA) {
0194ce8f 2522 memcpy(&rUIDBCC1[1], datain, 3);
bc939371 2523 memcpy(&rUIDBCC2[1], datain+3, 3);
2524 memcpy( rUIDBCC3, datain+6, 4);
0194ce8f 2525 _UID_LEN = 10;
d2f487af 2526 }
7bc95e2e 2527
0194ce8f 2528 switch (_UID_LEN) {
2529 case 4:
bc939371 2530 sak_4[0] &= 0xFB;
0194ce8f 2531 // save CUID
b6e05350 2532 cuid = bytes_to_num(rUIDBCC1, 4);
0194ce8f 2533 // BCC
2534 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
bc939371 2535 if (MF_DBGLEVEL >= 2) {
0194ce8f 2536 Dbprintf("4B UID: %02x%02x%02x%02x",
2537 rUIDBCC1[0],
2538 rUIDBCC1[1],
2539 rUIDBCC1[2],
2540 rUIDBCC1[3]
2541 );
2542 }
2543 break;
2544 case 7:
2545 atqa[0] |= 0x40;
bc939371 2546 sak_7[0] &= 0xFB;
0194ce8f 2547 // save CUID
b6e05350 2548 cuid = bytes_to_num(rUIDBCC2, 4);
bc939371 2549 // CascadeTag, CT
2550 rUIDBCC1[0] = 0x88;
0194ce8f 2551 // BCC
2552 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2553 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
bc939371 2554 if (MF_DBGLEVEL >= 2) {
0194ce8f 2555 Dbprintf("7B UID: %02x %02x %02x %02x %02x %02x %02x",
0194ce8f 2556 rUIDBCC1[1],
2557 rUIDBCC1[2],
2558 rUIDBCC1[3],
2559 rUIDBCC2[0],
2560 rUIDBCC2[1],
2561 rUIDBCC2[2],
2562 rUIDBCC2[3]
2563 );
2564 }
2565 break;
2566 case 10:
bc939371 2567 atqa[0] |= 0x80;
2568 sak_10[0] &= 0xFB;
0194ce8f 2569 // save CUID
b6e05350 2570 cuid = bytes_to_num(rUIDBCC3, 4);
bc939371 2571 // CascadeTag, CT
2572 rUIDBCC1[0] = 0x88;
2573 rUIDBCC2[0] = 0x88;
0194ce8f 2574 // BCC
2575 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
0194ce8f 2576 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2577 rUIDBCC3[4] = rUIDBCC3[0] ^ rUIDBCC3[1] ^ rUIDBCC3[2] ^ rUIDBCC3[3];
bc939371 2578
2579 if (MF_DBGLEVEL >= 2) {
0194ce8f 2580 Dbprintf("10B UID: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
0194ce8f 2581 rUIDBCC1[1],
2582 rUIDBCC1[2],
2583 rUIDBCC1[3],
0194ce8f 2584 rUIDBCC2[1],
2585 rUIDBCC2[2],
2586 rUIDBCC2[3],
2587 rUIDBCC3[0],
2588 rUIDBCC3[1],
2589 rUIDBCC3[2],
2590 rUIDBCC3[3]
2591 );
2592 }
2593 break;
2594 default:
2595 break;
d2f487af 2596 }
bc939371 2597 // calc some crcs
2598 ComputeCrc14443(CRC_14443_A, sak_4, 1, &sak_4[1], &sak_4[2]);
2599 ComputeCrc14443(CRC_14443_A, sak_7, 1, &sak_7[1], &sak_7[2]);
2600 ComputeCrc14443(CRC_14443_A, sak_10, 1, &sak_10[1], &sak_10[2]);
2601
99cf19d9 2602 // We need to listen to the high-frequency, peak-detected path.
2603 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2604
2605 // free eventually allocated BigBuf memory but keep Emulator Memory
2606 BigBuf_free_keep_EM();
99cf19d9 2607 clear_trace();
2608 set_tracing(TRUE);
2609
7bc95e2e 2610 bool finished = FALSE;
2b1f4228 2611 while (!BUTTON_PRESS() && !finished && !usb_poll_validate_length()) {
9ca155ba 2612 WDT_HIT();
9ca155ba
M
2613
2614 // find reader field
9ca155ba 2615 if (cardSTATE == MFEMUL_NOFIELD) {
0c8d25eb 2616 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
9ca155ba 2617 if (vHf > MF_MINFIELDV) {
0014cb46 2618 cardSTATE_TO_IDLE();
9ca155ba
M
2619 LED_A_ON();
2620 }
2621 }
0194ce8f 2622 if (cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2623
f38cfd66 2624 // Now, get data
6a1f2d82 2625 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2626 if (res == 2) { //Field is off!
2627 cardSTATE = MFEMUL_NOFIELD;
2628 LEDsoff();
2629 continue;
7bc95e2e 2630 } else if (res == 1) {
f38cfd66 2631 break; // return value 1 means button press
7bc95e2e 2632 }
2633
d2f487af 2634 // REQ or WUP request in ANY state and WUP in HALTED state
57850d9d 2635 // this if-statement doesn't match the specification above. (iceman)
0194ce8f 2636 if (len == 1 && ((receivedCmd[0] == ISO14443A_CMD_REQA && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == ISO14443A_CMD_WUPA)) {
d2f487af 2637 selTimer = GetTickCount();
0194ce8f 2638 EmSendCmdEx(atqa, sizeof(atqa), (receivedCmd[0] == ISO14443A_CMD_WUPA));
d2f487af 2639 cardSTATE = MFEMUL_SELECT1;
d2f487af 2640 crypto1_destroy(pcs);
2641 cardAUTHKEY = 0xff;
0194ce8f 2642 LEDsoff();
bf5d7992 2643 nonce = prand();
d2f487af 2644 continue;
0a39986e 2645 }
7bc95e2e 2646
50193c1e 2647 switch (cardSTATE) {
d2f487af 2648 case MFEMUL_NOFIELD:
2649 case MFEMUL_HALTED:
50193c1e 2650 case MFEMUL_IDLE:{
6a1f2d82 2651 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2652 break;
2653 }
2654 case MFEMUL_SELECT1:{
0194ce8f 2655 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT && receivedCmd[1] == 0x20)) {
d2f487af 2656 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2657 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2658 break;
9ca155ba 2659 }
9ca155ba 2660 // select card
0a39986e 2661 if (len == 9 &&
0194ce8f 2662 ( receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT &&
2663 receivedCmd[1] == 0x70 &&
2664 memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2665
2666 // SAK 4b
2667 EmSendCmd(sak_4, sizeof(sak_4));
2668 switch(_UID_LEN){
2669 case 4:
2670 cardSTATE = MFEMUL_WORK;
2671 LED_B_ON();
2672 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2673 continue;
2674 case 7:
2675 case 10:
2676 cardSTATE = MFEMUL_SELECT2;
2677 continue;
2678 default:break;
8556b852 2679 }
0194ce8f 2680 } else {
2681 cardSTATE_TO_IDLE();
2682 }
2683 break;
2684 }
2685 case MFEMUL_SELECT2:{
2686 if (!len) {
2687 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2688 break;
2689 }
2690 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 && receivedCmd[1] == 0x20)) {
2691 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2692 break;
2693 }
2694 if (len == 9 &&
2695 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 &&
2696 receivedCmd[1] == 0x70 &&
2697 memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0) ) {
2698
2699 EmSendCmd(sak_7, sizeof(sak_7));
2700 switch(_UID_LEN){
2701 case 7:
2702 cardSTATE = MFEMUL_WORK;
2703 LED_B_ON();
2704 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2705 continue;
2706 case 10:
2707 cardSTATE = MFEMUL_SELECT3;
2708 continue;
2709 default:break;
2710 }
bc939371 2711 }
2712 cardSTATE_TO_IDLE();
0194ce8f 2713 break;
2714 }
2715 case MFEMUL_SELECT3:{
2716 if (!len) {
2717 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2718 break;
2719 }
2720 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 && receivedCmd[1] == 0x20)) {
2721 EmSendCmd(rUIDBCC3, sizeof(rUIDBCC3));
2722 break;
2723 }
2724 if (len == 9 &&
2725 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 &&
2726 receivedCmd[1] == 0x70 &&
2727 memcmp(&receivedCmd[2], rUIDBCC3, 4) == 0) ) {
2728
2729 EmSendCmd(sak_10, sizeof(sak_10));
2730 cardSTATE = MFEMUL_WORK;
2731 LED_B_ON();
2732 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol3 time: %d", GetTickCount() - selTimer);
2733 break;
9ca155ba 2734 }
bc939371 2735 cardSTATE_TO_IDLE();
50193c1e
M
2736 break;
2737 }
d2f487af 2738 case MFEMUL_AUTH1:{
495d7f13 2739 if( len != 8) {
d2f487af 2740 cardSTATE_TO_IDLE();
6a1f2d82 2741 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2742 break;
2743 }
0c8d25eb 2744
bc939371 2745 uint32_t nr = bytes_to_num(receivedCmd, 4);
2746 uint32_t ar = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2747
b6e05350
MF
2748 if (doBufResetNext) {
2749 // Reset, lets try again!
2750 Dbprintf("Re-read after previous NR_AR_ATTACK, resetting buffer");
2751 memset(ar_nr_resp, 0x00, sizeof(ar_nr_resp));
2752 memset(ar_nr_collected, 0x00, sizeof(ar_nr_collected));
2753 mM = 0;
2754 doBufResetNext = false;
2755 }
2756
2757 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
bf5d7992 2758
2759 if ( ar_nr_collected[i+mM] == 0 || (
2760 (cardAUTHSC == ar_nr_resp[i+mM].sector) &&
2761 (cardAUTHKEY == ar_nr_resp[i+mM].keytype) &&
2762 (ar_nr_collected[i+mM] > 0)
2763 )
2764 ) {
b6e05350
MF
2765
2766 // if first auth for sector, or matches sector and keytype of previous auth
2767 if (ar_nr_collected[i+mM] < 2) {
2768 // if we haven't already collected 2 nonces for this sector
2769 if (ar_nr_resp[ar_nr_collected[i+mM]].ar != ar) {
2770 // Avoid duplicates... probably not necessary, ar should vary.
2771 if (ar_nr_collected[i+mM]==0) {
2772 // first nonce collect
2773 ar_nr_resp[i+mM].cuid = cuid;
2774 ar_nr_resp[i+mM].sector = cardAUTHSC;
2775 ar_nr_resp[i+mM].keytype = cardAUTHKEY;
2776 ar_nr_resp[i+mM].nonce = nonce;
2777 ar_nr_resp[i+mM].nr = nr;
2778 ar_nr_resp[i+mM].ar = ar;
2779 nonce1_count++;
2780 // add this nonce to first moebius nonce
2781 ar_nr_resp[i+ATTACK_KEY_COUNT].cuid = cuid;
2782 ar_nr_resp[i+ATTACK_KEY_COUNT].sector = cardAUTHSC;
2783 ar_nr_resp[i+ATTACK_KEY_COUNT].keytype = cardAUTHKEY;
2784 ar_nr_resp[i+ATTACK_KEY_COUNT].nonce = nonce;
2785 ar_nr_resp[i+ATTACK_KEY_COUNT].nr = nr;
2786 ar_nr_resp[i+ATTACK_KEY_COUNT].ar = ar;
2787 ar_nr_collected[i+ATTACK_KEY_COUNT]++;
2788 } else { // second nonce collect (std and moebius)
2789 ar_nr_resp[i+mM].nonce2 = nonce;
2790 ar_nr_resp[i+mM].nr2 = nr;
2791 ar_nr_resp[i+mM].ar2 = ar;
2792 if (!gettingMoebius) {
2793 nonce2_count++;
2794 // check if this was the last second nonce we need for std attack
2795 if ( nonce2_count == nonce1_count ) {
2796 // done collecting std test switch to moebius
2797 // first finish incrementing last sample
2798 ar_nr_collected[i+mM]++;
2799 // switch to moebius collection
2800 gettingMoebius = true;
2801 mM = ATTACK_KEY_COUNT;
2802 break;
2803 }
2804 } else {
2805 moebius_n_count++;
2806 // if we've collected all the nonces we need - finish.
2807
2808 if (nonce1_count == moebius_n_count) {
bf5d7992 2809 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, 0, 0, &ar_nr_resp, sizeof(ar_nr_resp));
b6e05350
MF
2810 nonce1_count = 0;
2811 nonce2_count = 0;
2812 moebius_n_count = 0;
2813 gettingMoebius = false;
2814 doBufResetNext = true;
2815 finished = ( ((flags & FLAG_INTERACTIVE) == FLAG_INTERACTIVE));
2816 }
2817 }
2818 }
2819 ar_nr_collected[i+mM]++;
2820 }
2821 }
2822 // we found right spot for this nonce stop looking
2823 break;
2824 }
2825 }
2826
2827
2828 /*
f38cfd66 2829 // Collect AR/NR
2830 // if(ar_nr_collected < 2 && cardAUTHSC == 2){
bc939371 2831 if(ar_nr_collected < 2) {
f38cfd66 2832 // if(ar_nr_responses[2] != nr) {
bc939371 2833 ar_nr_responses[ar_nr_collected*4] = cuid;
2834 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2835 ar_nr_responses[ar_nr_collected*4+2] = nr;
2836 ar_nr_responses[ar_nr_collected*4+3] = ar;
273b57a7 2837 ar_nr_collected++;
f38cfd66 2838 // }
bc939371 2839
12d708fe 2840 // Interactive mode flag, means we need to send ACK
bc939371 2841 finished = ( ((flags & FLAG_INTERACTIVE) == FLAG_INTERACTIVE)&& ar_nr_collected == 2);
d2f487af 2842 }
b6e05350 2843
0194ce8f 2844 crypto1_word(pcs, ar , 1);
2845 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2846
2847 test if auth OK
2848 if (cardRr != prng_successor(nonce, 64)){
c3c241f3 2849
0194ce8f 2850 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2851 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2852 cardRr, prng_successor(nonce, 64));
2853 Shouldn't we respond anything here?
2854 Right now, we don't nack or anything, which causes the
2855 reader to do a WUPA after a while. /Martin
2856 -- which is the correct response. /piwi
2857 cardSTATE_TO_IDLE();
2858 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2859 break;
2860 }
2861 */
2862
d2f487af 2863 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
d2f487af 2864 num_to_bytes(ans, 4, rAUTH_AT);
d2f487af 2865 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2866 LED_C_ON();
bc939371 2867
495d7f13 2868 if (MF_DBGLEVEL >= 4) {
2869 Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2870 cardAUTHSC,
2871 cardAUTHKEY == 0 ? 'A' : 'B',
2872 GetTickCount() - authTimer
2873 );
2874 }
0014cb46 2875 cardSTATE = MFEMUL_WORK;
0194ce8f 2876 break;
50193c1e 2877 }
7bc95e2e 2878 case MFEMUL_WORK:{
2879 if (len == 0) {
6a1f2d82 2880 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2881 break;
0194ce8f 2882 }
d2f487af 2883 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2884
495d7f13 2885 if(encrypted_data)
51969283 2886 mf_crypto1_decrypt(pcs, receivedCmd, len);
7bc95e2e 2887
0194ce8f 2888 if (len == 4 && (receivedCmd[0] == MIFARE_AUTH_KEYA ||
2889 receivedCmd[0] == MIFARE_AUTH_KEYB) ) {
2890
d2f487af 2891 authTimer = GetTickCount();
2892 cardAUTHSC = receivedCmd[1] / 4; // received block num
0194ce8f 2893 cardAUTHKEY = receivedCmd[0] - 0x60; // & 1
2894 crypto1_destroy(pcs);
d2f487af 2895 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2896
0194ce8f 2897 if (!encrypted_data) {
2898 // first authentication
f38cfd66 2899 crypto1_word(pcs, cuid ^ nonce, 0);// Update crypto state
d2f487af 2900 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
0194ce8f 2901
2902 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
2903
2904 } else {
2905 // nested authentication
7bc95e2e 2906 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2907 num_to_bytes(ans, 4, rAUTH_AT);
0194ce8f 2908
2909 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
d2f487af 2910 }
0c8d25eb 2911
d2f487af 2912 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
d2f487af 2913 cardSTATE = MFEMUL_AUTH1;
2914 break;
51969283 2915 }
7bc95e2e 2916
8f51ddb0
M
2917 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2918 // BUT... ACK --> NACK
2919 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2920 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2921 break;
2922 }
2923
2924 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2925 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2926 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2927 break;
0a39986e
M
2928 }
2929
7bc95e2e 2930 if(len != 4) {
6a1f2d82 2931 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2932 break;
2933 }
d2f487af 2934
0194ce8f 2935 if ( receivedCmd[0] == ISO14443A_CMD_READBLOCK ||
2936 receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK ||
2937 receivedCmd[0] == MIFARE_CMD_INC ||
2938 receivedCmd[0] == MIFARE_CMD_DEC ||
2939 receivedCmd[0] == MIFARE_CMD_RESTORE ||
2940 receivedCmd[0] == MIFARE_CMD_TRANSFER ) {
2941
7bc95e2e 2942 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2943 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2944 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2945 break;
2946 }
2947
7bc95e2e 2948 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2949 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2950 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2951 break;
2952 }
d2f487af 2953 }
2954 // read block
0194ce8f 2955 if (receivedCmd[0] == ISO14443A_CMD_READBLOCK) {
2956 if (MF_DBGLEVEL >= 4) Dbprintf("Reader reading block %d (0x%02x)", receivedCmd[1], receivedCmd[1]);
495d7f13 2957
8f51ddb0
M
2958 emlGetMem(response, receivedCmd[1], 1);
2959 AppendCrc14443a(response, 16);
6a1f2d82 2960 mf_crypto1_encrypt(pcs, response, 18, response_par);
2961 EmSendCmdPar(response, 18, response_par);
d2f487af 2962 numReads++;
12d708fe 2963 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
d2f487af 2964 Dbprintf("%d reads done, exiting", numReads);
2965 finished = true;
2966 }
0a39986e
M
2967 break;
2968 }
0a39986e 2969 // write block
0194ce8f 2970 if (receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK) {
2971 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)", receivedCmd[1], receivedCmd[1]);
8f51ddb0 2972 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2973 cardSTATE = MFEMUL_WRITEBL2;
2974 cardWRBL = receivedCmd[1];
0a39986e 2975 break;
7bc95e2e 2976 }
0014cb46 2977 // increment, decrement, restore
0194ce8f 2978 if ( receivedCmd[0] == MIFARE_CMD_INC ||
2979 receivedCmd[0] == MIFARE_CMD_DEC ||
2980 receivedCmd[0] == MIFARE_CMD_RESTORE) {
2981
2982 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2983
d2f487af 2984 if (emlCheckValBl(receivedCmd[1])) {
c3c241f3 2985 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2986 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2987 break;
2988 }
2989 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0194ce8f 2990 if (receivedCmd[0] == MIFARE_CMD_INC) cardSTATE = MFEMUL_INTREG_INC;
2991 if (receivedCmd[0] == MIFARE_CMD_DEC) cardSTATE = MFEMUL_INTREG_DEC;
2992 if (receivedCmd[0] == MIFARE_CMD_RESTORE) cardSTATE = MFEMUL_INTREG_REST;
0014cb46 2993 cardWRBL = receivedCmd[1];
0014cb46
M
2994 break;
2995 }
0014cb46 2996 // transfer
0194ce8f 2997 if (receivedCmd[0] == MIFARE_CMD_TRANSFER) {
2998 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)", receivedCmd[0], receivedCmd[1], receivedCmd[1]);
0014cb46
M
2999 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
3000 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
3001 else
3002 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
3003 break;
3004 }
9ca155ba 3005 // halt
0194ce8f 3006 if (receivedCmd[0] == ISO14443A_CMD_HALT && receivedCmd[1] == 0x00) {
9ca155ba 3007 LED_B_OFF();
0a39986e 3008 LED_C_OFF();
0014cb46
M
3009 cardSTATE = MFEMUL_HALTED;
3010 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 3011 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 3012 break;
9ca155ba 3013 }
d2f487af 3014 // RATS
0194ce8f 3015 if (receivedCmd[0] == ISO14443A_CMD_RATS) {
8f51ddb0
M
3016 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
3017 break;
3018 }
d2f487af 3019 // command not allowed
3020 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
3021 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 3022 break;
8f51ddb0
M
3023 }
3024 case MFEMUL_WRITEBL2:{
495d7f13 3025 if (len == 18) {
8f51ddb0
M
3026 mf_crypto1_decrypt(pcs, receivedCmd, len);
3027 emlSetMem(receivedCmd, cardWRBL, 1);
3028 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
3029 cardSTATE = MFEMUL_WORK;
51969283 3030 } else {
0014cb46 3031 cardSTATE_TO_IDLE();
6a1f2d82 3032 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 3033 }
8f51ddb0 3034 break;
50193c1e 3035 }
0014cb46
M
3036 case MFEMUL_INTREG_INC:{
3037 mf_crypto1_decrypt(pcs, receivedCmd, len);
3038 memcpy(&ans, receivedCmd, 4);
3039 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
3040 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
3041 cardSTATE_TO_IDLE();
3042 break;
7bc95e2e 3043 }
6a1f2d82 3044 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
3045 cardINTREG = cardINTREG + ans;
3046 cardSTATE = MFEMUL_WORK;
3047 break;
3048 }
3049 case MFEMUL_INTREG_DEC:{
3050 mf_crypto1_decrypt(pcs, receivedCmd, len);
3051 memcpy(&ans, receivedCmd, 4);
3052 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
3053 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
3054 cardSTATE_TO_IDLE();
3055 break;
3056 }
6a1f2d82 3057 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
3058 cardINTREG = cardINTREG - ans;
3059 cardSTATE = MFEMUL_WORK;
3060 break;
3061 }
3062 case MFEMUL_INTREG_REST:{
3063 mf_crypto1_decrypt(pcs, receivedCmd, len);
3064 memcpy(&ans, receivedCmd, 4);
3065 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
3066 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
3067 cardSTATE_TO_IDLE();
3068 break;
3069 }
6a1f2d82 3070 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
3071 cardSTATE = MFEMUL_WORK;
3072 break;
3073 }
50193c1e 3074 }
50193c1e
M
3075 }
3076
810f5379 3077 // Interactive mode flag, means we need to send ACK
b6e05350 3078 /*
bf5d7992 3079 if((flags & FLAG_INTERACTIVE) == FLAG_INTERACTIVE && flags & FLAG_NR_AR_ATTACK == FLAG_NR_AR_ATTACK) {
f38cfd66 3080 // May just aswell send the collected ar_nr in the response aswell
bc939371 3081 uint8_t len = ar_nr_collected * 4 * 4;
c3c241f3 3082 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, len, 0, &ar_nr_responses, len);
d2f487af 3083 }
bf5d7992 3084 */
b6e05350 3085
bc939371 3086 if( ((flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) && MF_DBGLEVEL >= 1 ) {
b6e05350
MF
3087 for ( uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
3088 if (ar_nr_collected[i] == 2) {
3089 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
3090 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
3091 ar_nr_resp[i].cuid, //UID
3092 ar_nr_resp[i].nonce, //NT
3093 ar_nr_resp[i].nr, //NR1
3094 ar_nr_resp[i].ar, //AR1
3095 ar_nr_resp[i].nr2, //NR2
3096 ar_nr_resp[i].ar2 //AR2
3097 );
3098 }
3099 }
3100 for ( uint8_t i = ATTACK_KEY_COUNT; i < ATTACK_KEY_COUNT*2; i++) {
3101 if (ar_nr_collected[i] == 2) {
3102 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
3103 Dbprintf("../tools/mfkey/mfkey32v2 %08x %08x %08x %08x %08x %08x %08x",
3104 ar_nr_resp[i].cuid, //UID
3105 ar_nr_resp[i].nonce, //NT
3106 ar_nr_resp[i].nr, //NR1
3107 ar_nr_resp[i].ar, //AR1
3108 ar_nr_resp[i].nonce2,//NT2
3109 ar_nr_resp[i].nr2, //NR2
3110 ar_nr_resp[i].ar2 //AR2
3111 );
d2f487af 3112 }
3113 }
bf5d7992 3114 }
b6e05350 3115
bf5d7992 3116 if (MF_DBGLEVEL >= 1)
3117 Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
5ee53a0e 3118
91c7a7cc 3119 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3120 LEDsoff();
5ee53a0e 3121 set_tracing(FALSE);
15c4dc5a 3122}
b62a5a84 3123
d2f487af 3124
b62a5a84
M
3125//-----------------------------------------------------------------------------
3126// MIFARE sniffer.
3127//
0194ce8f 3128// if no activity for 2sec, it sends the collected data to the client.
b62a5a84 3129//-----------------------------------------------------------------------------
bc939371 3130// "hf mf sniff"
5cd9ec01 3131void RAMFUNC SniffMifare(uint8_t param) {
bc939371 3132
b62a5a84 3133 LEDsoff();
810f5379 3134
aaa1a9a2 3135 // free eventually allocated BigBuf memory
3136 BigBuf_free(); BigBuf_Clear_ext(false);
3000dc4e
MHS
3137 clear_trace();
3138 set_tracing(TRUE);
b62a5a84 3139
b62a5a84 3140 // The command (reader -> tag) that we're receiving.
810f5379 3141 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
495d7f13 3142 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
810f5379 3143
b62a5a84 3144 // The response (tag -> reader) that we're receiving.
495d7f13 3145 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE] = {0x00};
3146 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b62a5a84 3147
99cf19d9 3148 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
3149
f71f4deb 3150 // allocate the DMA buffer, used to stream samples from the FPGA
0194ce8f 3151 // [iceman] is this sniffed data unsigned?
f71f4deb 3152 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 3153 uint8_t *data = dmaBuf;
3154 uint8_t previous_data = 0;
5cd9ec01
M
3155 int maxDataLen = 0;
3156 int dataLen = 0;
7bc95e2e 3157 bool ReaderIsActive = FALSE;
3158 bool TagIsActive = FALSE;
3159
b62a5a84 3160 // Set up the demodulator for tag -> reader responses.
6a1f2d82 3161 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
3162
3163 // Set up the demodulator for the reader -> tag commands
6a1f2d82 3164 UartInit(receivedCmd, receivedCmdPar);
b62a5a84 3165
57850d9d 3166 // Setup and start DMA.
3167 // set transfer address and number of bytes. Start transfer.
3168 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
3169 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
3170 return;
3171 }
b62a5a84 3172
b62a5a84 3173 LED_D_OFF();
0194ce8f 3174
39864b0b 3175 MfSniffInit();
b62a5a84 3176
b62a5a84 3177 // And now we loop, receiving samples.
0194ce8f 3178 for(uint32_t sniffCounter = 0;; ) {
91c7a7cc 3179
3180 LED_A_ON();
3181 WDT_HIT();
7bc95e2e 3182
5cd9ec01
M
3183 if(BUTTON_PRESS()) {
3184 DbpString("cancelled by button");
7bc95e2e 3185 break;
5cd9ec01 3186 }
91c7a7cc 3187
7bc95e2e 3188 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3189 // check if a transaction is completed (timeout after 2000ms).
3190 // if yes, stop the DMA transfer and send what we have so far to the client
3191 if (MfSniffSend(2000)) {
3192 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3193 sniffCounter = 0;
3194 data = dmaBuf;
3195 maxDataLen = 0;
3196 ReaderIsActive = FALSE;
3197 TagIsActive = FALSE;
57850d9d 3198 // Setup and start DMA. set transfer address and number of bytes. Start transfer.
3199 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
3200 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
3201 return;
3202 }
39864b0b 3203 }
39864b0b 3204 }
7bc95e2e 3205
3206 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3207 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
495d7f13 3208
3209 if (readBufDataP <= dmaBufDataP) // we are processing the same block of data which is currently being transferred
7bc95e2e 3210 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
495d7f13 3211 else
7bc95e2e 3212 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
495d7f13 3213
5cd9ec01 3214 // test for length of buffer
7bc95e2e 3215 if(dataLen > maxDataLen) { // we are more behind than ever...
3216 maxDataLen = dataLen;
f71f4deb 3217 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 3218 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 3219 break;
b62a5a84
M
3220 }
3221 }
5cd9ec01 3222 if(dataLen < 1) continue;
b62a5a84 3223
7bc95e2e 3224 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
3225 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3226 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3227 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
91c7a7cc 3228 Dbprintf("RxEmpty ERROR, data length:%d", dataLen); // temporary
5cd9ec01
M
3229 }
3230 // secondary buffer sets as primary, secondary buffer was stopped
3231 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3232 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
3233 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3234 }
5cd9ec01
M
3235
3236 LED_A_OFF();
b62a5a84 3237
7bc95e2e 3238 if (sniffCounter & 0x01) {
b62a5a84 3239
495d7f13 3240 // no need to try decoding tag data if the reader is sending
3241 if(!TagIsActive) {
7bc95e2e 3242 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3243 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3244 LED_C_INV();
495d7f13 3245
6a1f2d82 3246 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 3247
f8ada309 3248 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3249 DemodReset();
3250 }
3251 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3252 }
3253
495d7f13 3254 // no need to try decoding tag data if the reader is sending
3255 if(!ReaderIsActive) {
7bc95e2e 3256 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3257 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3258 LED_C_INV();
b62a5a84 3259
6a1f2d82 3260 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 3261
7bc95e2e 3262 DemodReset();
0ec548dc 3263 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3264 }
3265 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3266 }
b62a5a84
M
3267 }
3268
7bc95e2e 3269 previous_data = *data;
3270 sniffCounter++;
5cd9ec01 3271 data++;
495d7f13 3272
3273 if(data == dmaBuf + DMA_BUFFER_SIZE)
5cd9ec01 3274 data = dmaBuf;
7bc95e2e 3275
b62a5a84 3276 } // main cycle
bc939371 3277
3278 if (MF_DBGLEVEL >= 1) Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3279
55acbb2a 3280 FpgaDisableSscDma();
39864b0b 3281 MfSniffEnd();
91c7a7cc 3282 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3283 LEDsoff();
5ee53a0e 3284 set_tracing(FALSE);
3803d529 3285}
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