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d32691f1 1 //-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
534983d7 12#include "iso14443a.h"
f8ada309 13
534983d7 14static uint32_t iso14a_timeout;
1e262141 15int rsamples = 0;
1e262141 16uint8_t trigger = 0;
b0127e65 17// the block number for the ISO14443-4 PCB
18static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 19
0194ce8f 20static uint8_t* free_buffer_pointer;
21
7bc95e2e 22//
23// ISO14443 timing:
24//
25// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
26#define REQUEST_GUARD_TIME (7000/16 + 1)
27// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
28#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
29// bool LastCommandWasRequest = FALSE;
30
31//
32// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
33//
d714d3ef 34// When the PM acts as reader and is receiving tag data, it takes
35// 3 ticks delay in the AD converter
36// 16 ticks until the modulation detector completes and sets curbit
37// 8 ticks until bit_to_arm is assigned from curbit
38// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 39// 4*16 ticks until we measure the time
40// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 41#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 42
43// When the PM acts as a reader and is sending, it takes
44// 4*16 ticks until we can write data to the sending hold register
45// 8*16 ticks until the SHR is transferred to the Sending Shift Register
46// 8 ticks until the first transfer starts
47// 8 ticks later the FPGA samples the data
48// 1 tick to assign mod_sig_coil
49#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
50
51// When the PM acts as tag and is receiving it takes
d714d3ef 52// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 53// 3 ticks for the A/D conversion,
54// 8 ticks on average until the start of the SSC transfer,
55// 8 ticks until the SSC samples the first data
56// 7*16 ticks to complete the transfer from FPGA to ARM
57// 8 ticks until the next ssp_clk rising edge
d714d3ef 58// 4*16 ticks until we measure the time
7bc95e2e 59// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 60#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 61
62// The FPGA will report its internal sending delay in
63uint16_t FpgaSendQueueDelay;
64// the 5 first bits are the number of bits buffered in mod_sig_buf
65// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
66#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
67
68// When the PM acts as tag and is sending, it takes
d714d3ef 69// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 70// 8*16 ticks until the SHR is transferred to the Sending Shift Register
71// 8 ticks until the first transfer starts
72// 8 ticks later the FPGA samples the data
73// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
74// + 1 tick to assign mod_sig_coil
d714d3ef 75#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 76
77// When the PM acts as sniffer and is receiving tag data, it takes
78// 3 ticks A/D conversion
d714d3ef 79// 14 ticks to complete the modulation detection
80// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 81// + the delays in transferring data - which is the same for
82// sniffing reader and tag data and therefore not relevant
d714d3ef 83#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 84
d714d3ef 85// When the PM acts as sniffer and is receiving reader data, it takes
86// 2 ticks delay in analogue RF receiver (for the falling edge of the
87// start bit, which marks the start of the communication)
7bc95e2e 88// 3 ticks A/D conversion
d714d3ef 89// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 90// + the delays in transferring data - which is the same for
91// sniffing reader and tag data and therefore not relevant
d714d3ef 92#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 93
94//variables used for timing purposes:
95//these are in ssp_clk cycles:
6a1f2d82 96static uint32_t NextTransferTime;
97static uint32_t LastTimeProxToAirStart;
98static uint32_t LastProxToAirDuration;
7bc95e2e 99
8f51ddb0 100// CARD TO READER - manchester
72934aa3 101// Sequence D: 11110000 modulation with subcarrier during first half
102// Sequence E: 00001111 modulation with subcarrier during second half
103// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 104// READER TO CARD - miller
72934aa3 105// Sequence X: 00001100 drop after half a period
106// Sequence Y: 00000000 no drop
107// Sequence Z: 11000000 drop at start
108#define SEC_D 0xf0
109#define SEC_E 0x0f
110#define SEC_F 0x00
111#define SEC_X 0x0c
112#define SEC_Y 0x00
113#define SEC_Z 0xc0
15c4dc5a 114
902cb3c0 115void iso14a_set_trigger(bool enable) {
534983d7 116 trigger = enable;
117}
118
b0127e65 119void iso14a_set_timeout(uint32_t timeout) {
120 iso14a_timeout = timeout;
19a700a8 121 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
b0127e65 122}
8556b852 123
19a700a8 124void iso14a_set_ATS_timeout(uint8_t *ats) {
19a700a8 125 uint8_t tb1;
126 uint8_t fwi;
127 uint32_t fwt;
128
129 if (ats[0] > 1) { // there is a format byte T0
130 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
4c0cf2d2 131
132 if ((ats[1] & 0x10) == 0x10) // there is an interface byte TA(1) preceding TB(1)
19a700a8 133 tb1 = ats[3];
4c0cf2d2 134 else
19a700a8 135 tb1 = ats[2];
4c0cf2d2 136
19a700a8 137 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
ca5bad3d 138 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
139 //fwt = 4096 * (1 << fwi);
19a700a8 140
ca5bad3d 141 iso14a_set_timeout(fwt/(8*16));
142 //iso14a_set_timeout(fwt/128);
19a700a8 143 }
144 }
145}
146
15c4dc5a 147//-----------------------------------------------------------------------------
148// Generate the parity value for a byte sequence
e30c654b 149//
15c4dc5a 150//-----------------------------------------------------------------------------
91c7a7cc 151void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par) {
6a1f2d82 152 uint16_t paritybit_cnt = 0;
153 uint16_t paritybyte_cnt = 0;
154 uint8_t parityBits = 0;
155
156 for (uint16_t i = 0; i < iLen; i++) {
157 // Generate the parity bits
f8ada309 158 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
6a1f2d82 159 if (paritybit_cnt == 7) {
160 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
161 parityBits = 0; // and advance to next Parity Byte
162 paritybyte_cnt++;
163 paritybit_cnt = 0;
164 } else {
165 paritybit_cnt++;
166 }
5f6d6c90 167 }
6a1f2d82 168
169 // save remaining parity bits
91c7a7cc 170 par[paritybyte_cnt] = parityBits;
15c4dc5a 171}
172
91c7a7cc 173void AppendCrc14443a(uint8_t* data, int len) {
5f6d6c90 174 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 175}
176
7bc95e2e 177//=============================================================================
178// ISO 14443 Type A - Miller decoder
179//=============================================================================
180// Basics:
181// This decoder is used when the PM3 acts as a tag.
182// The reader will generate "pauses" by temporarily switching of the field.
183// At the PM3 antenna we will therefore measure a modulated antenna voltage.
184// The FPGA does a comparison with a threshold and would deliver e.g.:
185// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
186// The Miller decoder needs to identify the following sequences:
187// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
188// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
189// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
190// Note 1: the bitstream may start at any time. We therefore need to sync.
191// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 192//-----------------------------------------------------------------------------
b62a5a84 193static tUart Uart;
15c4dc5a 194
d7aa3739 195// Lookup-Table to decide if 4 raw bits are a modulation.
0ec548dc 196// We accept the following:
197// 0001 - a 3 tick wide pause
198// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
199// 0111 - a 2 tick wide pause shifted left
200// 1001 - a 2 tick wide pause shifted right
d7aa3739 201const bool Mod_Miller_LUT[] = {
0ec548dc 202 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
203 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
d7aa3739 204};
0ec548dc 205#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
206#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 207
91c7a7cc 208void UartReset() {
7bc95e2e 209 Uart.state = STATE_UNSYNCD;
210 Uart.bitCount = 0;
211 Uart.len = 0; // number of decoded data bytes
6a1f2d82 212 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 213 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 214 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 215 Uart.startTime = 0;
216 Uart.endTime = 0;
46c65fed 217
218 Uart.byteCntMax = 0;
219 Uart.posCnt = 0;
220 Uart.syncBit = 9999;
7bc95e2e 221}
15c4dc5a 222
91c7a7cc 223void UartInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 224 Uart.output = data;
225 Uart.parity = parity;
0ec548dc 226 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
6a1f2d82 227 UartReset();
228}
d714d3ef 229
7bc95e2e 230// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 231static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time) {
0ec548dc 232 Uart.fourBits = (Uart.fourBits << 8) | bit;
7bc95e2e 233
0c8d25eb 234 if (Uart.state == STATE_UNSYNCD) { // not yet synced
91c7a7cc 235 Uart.syncBit = 9999; // not set
46c65fed 236
237 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
238 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
239 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
240
0ec548dc 241 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
46c65fed 242 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
243 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
0ec548dc 244 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
46c65fed 245 //
246#define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
247#define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
248
0ec548dc 249 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
250 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
251 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
252 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
253 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
254 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
255 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
256 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
257
258 if (Uart.syncBit != 9999) { // found a sync bit
91c7a7cc 259 Uart.startTime = non_real_time ? non_real_time : (GetCountSspClk() & 0xfffffff8);
260 Uart.startTime -= Uart.syncBit;
261 Uart.endTime = Uart.startTime;
262 Uart.state = STATE_START_OF_COMMUNICATION;
263 }
7bc95e2e 264 } else {
15c4dc5a 265
0ec548dc 266 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
267 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
d7aa3739 268 UartReset();
d7aa3739 269 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 270 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
271 UartReset();
7bc95e2e 272 } else {
273 Uart.bitCount++;
274 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
275 Uart.state = STATE_MILLER_Z;
276 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
277 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
278 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
279 Uart.parityBits <<= 1; // make room for the parity bit
280 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
281 Uart.bitCount = 0;
282 Uart.shiftReg = 0;
6a1f2d82 283 if((Uart.len&0x0007) == 0) { // every 8 data bytes
284 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
285 Uart.parityBits = 0;
286 }
15c4dc5a 287 }
7bc95e2e 288 }
d7aa3739 289 }
290 } else {
0ec548dc 291 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 292 Uart.bitCount++;
293 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
294 Uart.state = STATE_MILLER_X;
295 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
296 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
297 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
298 Uart.parityBits <<= 1; // make room for the new parity bit
299 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
300 Uart.bitCount = 0;
301 Uart.shiftReg = 0;
6a1f2d82 302 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
303 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
304 Uart.parityBits = 0;
305 }
7bc95e2e 306 }
d7aa3739 307 } else { // no modulation in both halves - Sequence Y
7bc95e2e 308 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 309 Uart.state = STATE_UNSYNCD;
6a1f2d82 310 Uart.bitCount--; // last "0" was part of EOC sequence
311 Uart.shiftReg <<= 1; // drop it
312 if(Uart.bitCount > 0) { // if we decoded some bits
313 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
314 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
315 Uart.parityBits <<= 1; // add a (void) parity bit
316 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
317 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
318 return TRUE;
319 } else if (Uart.len & 0x0007) { // there are some parity bits to store
320 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
321 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 322 }
323 if (Uart.len) {
6a1f2d82 324 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 325 } else {
0c8d25eb 326 UartReset(); // Nothing received - start over
7bc95e2e 327 }
15c4dc5a 328 }
7bc95e2e 329 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
330 UartReset();
7bc95e2e 331 } else { // a logic "0"
332 Uart.bitCount++;
333 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
334 Uart.state = STATE_MILLER_Y;
335 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
336 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
337 Uart.parityBits <<= 1; // make room for the parity bit
338 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
339 Uart.bitCount = 0;
340 Uart.shiftReg = 0;
6a1f2d82 341 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
342 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
343 Uart.parityBits = 0;
344 }
15c4dc5a 345 }
346 }
d7aa3739 347 }
15c4dc5a 348 }
7bc95e2e 349 }
7bc95e2e 350 return FALSE; // not finished yet, need more data
15c4dc5a 351}
352
353//=============================================================================
e691fc45 354// ISO 14443 Type A - Manchester decoder
15c4dc5a 355//=============================================================================
e691fc45 356// Basics:
7bc95e2e 357// This decoder is used when the PM3 acts as a reader.
e691fc45 358// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
359// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
360// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
361// The Manchester decoder needs to identify the following sequences:
362// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
363// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
364// 8 ticks unmodulated: Sequence F = end of communication
365// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 366// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 367// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 368static tDemod Demod;
15c4dc5a 369
d7aa3739 370// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 371// We accept three or four "1" in any position
7bc95e2e 372const bool Mod_Manchester_LUT[] = {
d7aa3739 373 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 374 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 375};
376
377#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
378#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 379
91c7a7cc 380void DemodReset() {
7bc95e2e 381 Demod.state = DEMOD_UNSYNCD;
382 Demod.len = 0; // number of decoded data bytes
6a1f2d82 383 Demod.parityLen = 0;
7bc95e2e 384 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
385 Demod.parityBits = 0; //
386 Demod.collisionPos = 0; // Position of collision bit
387 Demod.twoBits = 0xffff; // buffer for 2 Bits
388 Demod.highCnt = 0;
389 Demod.startTime = 0;
91c7a7cc 390 Demod.endTime = 0;
46c65fed 391 Demod.bitCount = 0;
392 Demod.syncBit = 0xFFFF;
393 Demod.samples = 0;
e691fc45 394}
15c4dc5a 395
91c7a7cc 396void DemodInit(uint8_t *data, uint8_t *parity) {
6a1f2d82 397 Demod.output = data;
398 Demod.parity = parity;
399 DemodReset();
400}
401
7bc95e2e 402// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
91c7a7cc 403static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time) {
7bc95e2e 404 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 405
7bc95e2e 406 if (Demod.state == DEMOD_UNSYNCD) {
407
408 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
409 if (Demod.twoBits == 0x0000) {
410 Demod.highCnt++;
411 } else {
412 Demod.highCnt = 0;
413 }
414 } else {
415 Demod.syncBit = 0xFFFF; // not set
416 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
417 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
418 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
419 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
420 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
421 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
422 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
423 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 424 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 425 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
426 Demod.startTime -= Demod.syncBit;
427 Demod.bitCount = offset; // number of decoded data bits
e691fc45 428 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 429 }
7bc95e2e 430 }
7bc95e2e 431 } else {
15c4dc5a 432
7bc95e2e 433 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
434 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 435 if (!Demod.collisionPos) {
436 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
437 }
438 } // modulation in first half only - Sequence D = 1
7bc95e2e 439 Demod.bitCount++;
440 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
441 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 442 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 443 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 444 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
445 Demod.bitCount = 0;
446 Demod.shiftReg = 0;
6a1f2d82 447 if((Demod.len&0x0007) == 0) { // every 8 data bytes
448 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
449 Demod.parityBits = 0;
450 }
15c4dc5a 451 }
7bc95e2e 452 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
453 } else { // no modulation in first half
454 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 455 Demod.bitCount++;
7bc95e2e 456 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 457 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 458 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 459 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 460 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
461 Demod.bitCount = 0;
462 Demod.shiftReg = 0;
6a1f2d82 463 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
464 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
465 Demod.parityBits = 0;
466 }
15c4dc5a 467 }
7bc95e2e 468 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 469 } else { // no modulation in both halves - End of communication
6a1f2d82 470 if(Demod.bitCount > 0) { // there are some remaining data bits
471 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
472 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
473 Demod.parityBits <<= 1; // add a (void) parity bit
474 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
475 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
476 return TRUE;
477 } else if (Demod.len & 0x0007) { // there are some parity bits to store
478 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
479 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 480 }
481 if (Demod.len) {
d7aa3739 482 return TRUE; // we are finished with decoding the raw data sequence
483 } else { // nothing received. Start over
484 DemodReset();
e691fc45 485 }
15c4dc5a 486 }
7bc95e2e 487 }
e691fc45 488 }
e691fc45 489 return FALSE; // not finished yet, need more data
15c4dc5a 490}
491
492//=============================================================================
493// Finally, a `sniffer' for ISO 14443 Type A
494// Both sides of communication!
495//=============================================================================
496
497//-----------------------------------------------------------------------------
498// Record the sequence of commands sent by the reader to the tag, with
499// triggering so that we start recording at the point that the tag is moved
500// near the reader.
bc939371 501// "hf 14a sniff"
15c4dc5a 502//-----------------------------------------------------------------------------
d26849d4 503void RAMFUNC SniffIso14443a(uint8_t param) {
5cd9ec01
M
504 // param:
505 // bit 0 - trigger from first card answer
506 // bit 1 - trigger from first reader 7-bit request
5cd9ec01 507 LEDsoff();
5cd9ec01 508
99cf19d9 509 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
7bc95e2e 510
f71f4deb 511 // Allocate memory from BigBuf for some buffers
512 // free all previous allocations first
aaa1a9a2 513 BigBuf_free(); BigBuf_Clear_ext(false);
7838f4be 514 clear_trace();
515 set_tracing(TRUE);
516
5cd9ec01 517 // The command (reader -> tag) that we're receiving.
f71f4deb 518 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
519 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 520
5cd9ec01 521 // The response (tag -> reader) that we're receiving.
f71f4deb 522 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
523 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
524
525 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 526 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
527
7bc95e2e 528 uint8_t *data = dmaBuf;
529 uint8_t previous_data = 0;
5cd9ec01
M
530 int maxDataLen = 0;
531 int dataLen = 0;
7bc95e2e 532 bool TagIsActive = FALSE;
533 bool ReaderIsActive = FALSE;
534
5cd9ec01 535 // Set up the demodulator for tag -> reader responses.
6a1f2d82 536 DemodInit(receivedResponse, receivedResponsePar);
537
5cd9ec01 538 // Set up the demodulator for the reader -> tag commands
6a1f2d82 539 UartInit(receivedCmd, receivedCmdPar);
540
7bc95e2e 541 // Setup and start DMA.
57850d9d 542 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
543 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
544 return;
545 }
7bc95e2e 546
99cf19d9 547 // We won't start recording the frames that we acquire until we trigger;
548 // a good trigger condition to get started is probably when we see a
549 // response from the tag.
550 // triggered == FALSE -- to wait first for card
551 bool triggered = !(param & 0x03);
552
5cd9ec01 553 // And now we loop, receiving samples.
7bc95e2e 554 for(uint32_t rsamples = 0; TRUE; ) {
555
5cd9ec01
M
556 if(BUTTON_PRESS()) {
557 DbpString("cancelled by button");
7bc95e2e 558 break;
5cd9ec01 559 }
15c4dc5a 560
5cd9ec01
M
561 LED_A_ON();
562 WDT_HIT();
15c4dc5a 563
5cd9ec01
M
564 int register readBufDataP = data - dmaBuf;
565 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
566 if (readBufDataP <= dmaBufDataP){
567 dataLen = dmaBufDataP - readBufDataP;
568 } else {
7bc95e2e 569 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
570 }
571 // test for length of buffer
572 if(dataLen > maxDataLen) {
573 maxDataLen = dataLen;
f71f4deb 574 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 575 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
576 break;
5cd9ec01
M
577 }
578 }
579 if(dataLen < 1) continue;
580
581 // primary buffer was stopped( <-- we lost data!
582 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
583 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
584 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 585 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
586 }
587 // secondary buffer sets as primary, secondary buffer was stopped
588 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
589 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
590 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
591 }
592
593 LED_A_OFF();
7bc95e2e 594
595 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 596
7bc95e2e 597 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
598 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
599 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
600 LED_C_ON();
5cd9ec01 601
7bc95e2e 602 // check - if there is a short 7bit request from reader
603 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 604
7bc95e2e 605 if(triggered) {
6a1f2d82 606 if (!LogTrace(receivedCmd,
607 Uart.len,
608 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
609 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
610 Uart.parity,
611 TRUE)) break;
7bc95e2e 612 }
613 /* And ready to receive another command. */
614 UartReset();
615 /* And also reset the demod code, which might have been */
616 /* false-triggered by the commands from the reader. */
617 DemodReset();
618 LED_B_OFF();
619 }
620 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 621 }
3be2a5ae 622
7bc95e2e 623 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
624 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
625 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
626 LED_B_ON();
5cd9ec01 627
6a1f2d82 628 if (!LogTrace(receivedResponse,
629 Demod.len,
630 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
631 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
632 Demod.parity,
633 FALSE)) break;
5cd9ec01 634
7bc95e2e 635 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 636
7bc95e2e 637 // And ready to receive another response.
638 DemodReset();
0ec548dc 639 // And reset the Miller decoder including itS (now outdated) input buffer
640 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 641 LED_C_OFF();
642 }
643 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
644 }
5cd9ec01
M
645 }
646
7bc95e2e 647 previous_data = *data;
648 rsamples++;
5cd9ec01 649 data++;
d714d3ef 650 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
651 data = dmaBuf;
652 }
653 } // main cycle
654
bc939371 655 if (MF_DBGLEVEL >= 1) {
656 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
657 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
658 }
7bc95e2e 659 FpgaDisableSscDma();
91c7a7cc 660 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
bc939371 661 LEDsoff();
5ee53a0e 662 set_tracing(FALSE);
15c4dc5a 663}
664
15c4dc5a 665//-----------------------------------------------------------------------------
666// Prepare tag messages
667//-----------------------------------------------------------------------------
91c7a7cc 668static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity) {
8f51ddb0 669 ToSendReset();
15c4dc5a 670
671 // Correction bit, might be removed when not needed
672 ToSendStuffBit(0);
673 ToSendStuffBit(0);
674 ToSendStuffBit(0);
675 ToSendStuffBit(0);
676 ToSendStuffBit(1); // 1
677 ToSendStuffBit(0);
678 ToSendStuffBit(0);
679 ToSendStuffBit(0);
8f51ddb0 680
15c4dc5a 681 // Send startbit
72934aa3 682 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 683 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 684
6a1f2d82 685 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 686 uint8_t b = cmd[i];
15c4dc5a 687
688 // Data bits
6a1f2d82 689 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 690 if(b & 1) {
72934aa3 691 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 692 } else {
72934aa3 693 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
694 }
695 b >>= 1;
696 }
15c4dc5a 697
0014cb46 698 // Get the parity bit
6a1f2d82 699 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 700 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 701 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 702 } else {
72934aa3 703 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 704 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 705 }
8f51ddb0 706 }
15c4dc5a 707
8f51ddb0
M
708 // Send stopbit
709 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 710
8f51ddb0 711 // Convert from last byte pos to length
6fc68747 712 ++ToSendMax;
8f51ddb0
M
713}
714
91c7a7cc 715static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len) {
7504dc50 716 uint8_t par[MAX_PARITY_SIZE] = {0};
6a1f2d82 717 GetParity(cmd, len, par);
718 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 719}
720
91c7a7cc 721static void Code4bitAnswerAsTag(uint8_t cmd) {
91c7a7cc 722 uint8_t b = cmd;
8f51ddb0 723
5f6d6c90 724 ToSendReset();
8f51ddb0
M
725
726 // Correction bit, might be removed when not needed
727 ToSendStuffBit(0);
728 ToSendStuffBit(0);
729 ToSendStuffBit(0);
730 ToSendStuffBit(0);
731 ToSendStuffBit(1); // 1
732 ToSendStuffBit(0);
733 ToSendStuffBit(0);
734 ToSendStuffBit(0);
735
736 // Send startbit
737 ToSend[++ToSendMax] = SEC_D;
738
0194ce8f 739 for(uint8_t i = 0; i < 4; i++) {
8f51ddb0
M
740 if(b & 1) {
741 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 742 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
743 } else {
744 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 745 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
746 }
747 b >>= 1;
748 }
749
750 // Send stopbit
751 ToSend[++ToSendMax] = SEC_F;
752
5f6d6c90 753 // Convert from last byte pos to length
754 ToSendMax++;
15c4dc5a 755}
756
757//-----------------------------------------------------------------------------
758// Wait for commands from reader
759// Stop when button is pressed
760// Or return TRUE when command is captured
761//-----------------------------------------------------------------------------
99136c6e 762int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len) {
15c4dc5a 763 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
764 // only, since we are receiving, not transmitting).
765 // Signal field is off with the appropriate LED
766 LED_D_OFF();
767 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
768
ca5bad3d 769 // Now run a `software UART` on the stream of incoming samples.
6a1f2d82 770 UartInit(received, parity);
7bc95e2e 771
772 // clear RXRDY:
773 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 774
775 for(;;) {
776 WDT_HIT();
777
778 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 779
15c4dc5a 780 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 781 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
782 if(MillerDecoding(b, 0)) {
783 *len = Uart.len;
15c4dc5a 784 return TRUE;
785 }
7bc95e2e 786 }
15c4dc5a 787 }
788}
28afbd2b 789
ce02f6f9 790bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 791 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 792 // This will need the following byte array for a modulation sequence
793 // 144 data bits (18 * 8)
794 // 18 parity bits
795 // 2 Start and stop
796 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
797 // 1 just for the case
798 // ----------- +
799 // 166 bytes, since every bit that needs to be send costs us a byte
800 //
91c7a7cc 801 // Prepare the tag modulation bits from the message
802 CodeIso14443aAsTag(response_info->response,response_info->response_n);
803
804 // Make sure we do not exceed the free buffer space
805 if (ToSendMax > max_buffer_size) {
806 Dbprintf("Out of memory, when modulating bits for tag answer:");
807 Dbhexdump(response_info->response_n,response_info->response,false);
808 return FALSE;
809 }
810
811 // Copy the byte array, used for this modulation to the buffer position
812 memcpy(response_info->modulation,ToSend,ToSendMax);
813
814 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
815 response_info->modulation_n = ToSendMax;
816 response_info->ProxToAirDuration = LastProxToAirDuration;
817 return TRUE;
ce02f6f9 818}
819
f71f4deb 820// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
821// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
822// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
823// -> need 273 bytes buffer
c9216a92 824// 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
825// 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
826#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
f71f4deb 827
ce02f6f9 828bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
ca5bad3d 829 // Retrieve and store the current buffer index
830 response_info->modulation = free_buffer_pointer;
831
832 // Determine the maximum size we can use from our buffer
833 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
834
835 // Forward the prepare tag modulation function to the inner function
836 if (prepare_tag_modulation(response_info, max_buffer_size)) {
837 // Update the free buffer offset
838 free_buffer_pointer += ToSendMax;
839 return true;
840 } else {
841 return false;
842 }
ce02f6f9 843}
844
15c4dc5a 845//-----------------------------------------------------------------------------
846// Main loop of simulated tag: receive commands from reader, decide what
847// response to send, and send it.
0a856e29 848// 'hf 14a sim'
15c4dc5a 849//-----------------------------------------------------------------------------
91c7a7cc 850void SimulateIso14443aTag(int tagType, int flags, byte_t* data) {
0194ce8f 851
bf5d7992 852 #define ATTACK_KEY_COUNT 8 // keep same as define in cmdhfmf.c -> readerAttack()
e99acd00 853 // init pseudorand
854 fast_prand();
bf5d7992 855
0194ce8f 856 uint8_t sak = 0;
bc939371 857 uint32_t cuid = 0;
858 uint32_t nonce = 0;
859
32719adf 860 // PACK response to PWD AUTH for EV1/NTAG
0194ce8f 861 uint8_t response8[4] = {0,0,0,0};
862 // Counter for EV1/NTAG
863 uint32_t counters[] = {0,0,0};
32719adf 864
81cd0474 865 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
0194ce8f 866 uint8_t response1[] = {0,0};
6b23be6b 867
868 // Here, we collect CUID, block1, keytype1, NT1, NR1, AR1, CUID, block2, keytyp2, NT2, NR2, AR2
869 // it should also collect block, keytype.
870 uint8_t cardAUTHSC = 0;
871 uint8_t cardAUTHKEY = 0xff; // no authentication
872 // allow collecting up to 8 sets of nonces to allow recovery of up to 8 keys
bf5d7992 873
84bdbc19 874 nonces_t ar_nr_nonces[ATTACK_KEY_COUNT]; // for attack types moebius
875 memset(ar_nr_nonces, 0x00, sizeof(ar_nr_nonces));
876 uint8_t moebius_count = 0;
81cd0474 877
878 switch (tagType) {
0194ce8f 879 case 1: { // MIFARE Classic 1k
81cd0474 880 response1[0] = 0x04;
81cd0474 881 sak = 0x08;
882 } break;
883 case 2: { // MIFARE Ultralight
32719adf 884 response1[0] = 0x44;
81cd0474 885 sak = 0x00;
886 } break;
887 case 3: { // MIFARE DESFire
81cd0474 888 response1[0] = 0x04;
889 response1[1] = 0x03;
890 sak = 0x20;
891 } break;
0194ce8f 892 case 4: { // ISO/IEC 14443-4 - javacard (JCOP)
81cd0474 893 response1[0] = 0x04;
81cd0474 894 sak = 0x28;
895 } break;
3fe4ff4f 896 case 5: { // MIFARE TNP3XXX
3fe4ff4f 897 response1[0] = 0x01;
898 response1[1] = 0x0f;
899 sak = 0x01;
d26849d4 900 } break;
0194ce8f 901 case 6: { // MIFARE Mini 320b
d26849d4 902 response1[0] = 0x44;
d26849d4 903 sak = 0x09;
904 } break;
0194ce8f 905 case 7: { // NTAG
32719adf 906 response1[0] = 0x44;
32719adf 907 sak = 0x00;
908 // PACK
909 response8[0] = 0x80;
910 response8[1] = 0x80;
911 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
2b1f4228 912 // uid not supplied then get from emulator memory
913 if (data[0]==0) {
914 uint16_t start = 4 * (0+12);
915 uint8_t emdata[8];
916 emlGetMemBt( emdata, start, sizeof(emdata));
f38cfd66 917 memcpy(data, emdata, 3); // uid bytes 0-2
918 memcpy(data+3, emdata+4, 4); // uid bytes 3-7
2b1f4228 919 flags |= FLAG_7B_UID_IN_DATA;
920 }
4401050b 921 } break;
922 case 8: { // MIFARE Classic 4k
923 response1[0] = 0x02;
924 sak = 0x18;
925 } break;
81cd0474 926 default: {
927 Dbprintf("Error: unkown tagtype (%d)",tagType);
928 return;
929 } break;
930 }
931
932 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 933 uint8_t response2[5] = {0x00};
81cd0474 934
0194ce8f 935 // For UID size 7,
c8b6da22 936 uint8_t response2a[5] = {0x00};
937
bc939371 938 if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA ) {
0194ce8f 939 response2[0] = 0x88; // Cascade Tag marker
d26849d4 940 response2[1] = data[0];
941 response2[2] = data[1];
942 response2[3] = data[2];
943
944 response2a[0] = data[3];
945 response2a[1] = data[4];
946 response2a[2] = data[5];
c3c241f3 947 response2a[3] = data[6]; //??
81cd0474 948 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
949
950 // Configure the ATQA and SAK accordingly
951 response1[0] |= 0x40;
952 sak |= 0x04;
bc939371 953
954 cuid = bytes_to_num(data+3, 4);
81cd0474 955 } else {
d26849d4 956 memcpy(response2, data, 4);
81cd0474 957 // Configure the ATQA and SAK accordingly
958 response1[0] &= 0xBF;
959 sak &= 0xFB;
bc939371 960 cuid = bytes_to_num(data, 4);
81cd0474 961 }
962
963 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
964 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
965
966 // Prepare the mandatory SAK (for 4 and 7 byte UID)
0194ce8f 967 uint8_t response3[3] = {sak, 0x00, 0x00};
81cd0474 968 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
969
970 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 971 uint8_t response3a[3] = {0x00};
81cd0474 972 response3a[0] = sak & 0xFB;
973 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
974
bf5d7992 975 // Tag NONCE.
976 uint8_t response5[4];
bf5d7992 977
0194ce8f 978 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
6a1f2d82 979 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
980 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
981 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
982 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 983 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
bc939371 984
2b1f4228 985 // Prepare GET_VERSION (different for UL EV-1 / NTAG)
f38cfd66 986 // uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
987 // uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
c9216a92 988 // Prepare CHK_TEARING
f38cfd66 989 // uint8_t response9[] = {0xBD,0x90,0x3f};
c9216a92 990
991 #define TAG_RESPONSE_COUNT 10
7bc95e2e 992 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
993 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
994 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
995 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
996 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
997 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
998 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
999 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
4c0cf2d2 1000
495d7f13 1001 { .response = response8, .response_n = sizeof(response8) } // EV1/NTAG PACK response
4c0cf2d2 1002 };
f38cfd66 1003 // { .response = response7_NTAG, .response_n = sizeof(response7_NTAG)}, // EV1/NTAG GET_VERSION response
1004 // { .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
4c0cf2d2 1005
7bc95e2e 1006
1007 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1008 // Such a response is less time critical, so we can prepare them on the fly
1009 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1010 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1011 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1012 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1013 tag_response_info_t dynamic_response_info = {
1014 .response = dynamic_response_buffer,
1015 .response_n = 0,
1016 .modulation = dynamic_modulation_buffer,
1017 .modulation_n = 0
1018 };
ce02f6f9 1019
99cf19d9 1020 // We need to listen to the high-frequency, peak-detected path.
1021 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1022
f71f4deb 1023 BigBuf_free_keep_EM();
0194ce8f 1024 clear_trace();
1025 set_tracing(TRUE);
f71f4deb 1026
1027 // allocate buffers:
1028 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1029 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1030 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1031
7bc95e2e 1032 // Prepare the responses of the anticollision phase
ce02f6f9 1033 // there will be not enough time to do this at the moment the reader sends it REQA
495d7f13 1034 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++)
7bc95e2e 1035 prepare_allocated_tag_modulation(&responses[i]);
15c4dc5a 1036
7bc95e2e 1037 int len = 0;
15c4dc5a 1038
1039 // To control where we are in the protocol
1040 int order = 0;
1041 int lastorder;
1042
1043 // Just to allow some checks
1044 int happened = 0;
1045 int happened2 = 0;
81cd0474 1046 int cmdsRecvd = 0;
7bc95e2e 1047 tag_response_info_t* p_response;
15c4dc5a 1048
254b70a4 1049 LED_A_ON();
0194ce8f 1050 for(;;) {
4c0cf2d2 1051 WDT_HIT();
1052
7bc95e2e 1053 // Clean receive command buffer
6a1f2d82 1054 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
84bdbc19 1055 Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
254b70a4 1056 break;
7e735c13 1057 }
7bc95e2e 1058 p_response = NULL;
1059
254b70a4 1060 // Okay, look at the command now.
1061 lastorder = order;
0194ce8f 1062 if(receivedCmd[0] == ISO14443A_CMD_REQA) { // Received a REQUEST
ce02f6f9 1063 p_response = &responses[0]; order = 1;
0194ce8f 1064 } else if(receivedCmd[0] == ISO14443A_CMD_WUPA) { // Received a WAKEUP
ce02f6f9 1065 p_response = &responses[0]; order = 6;
0194ce8f 1066 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received request for UID (cascade 1)
ce02f6f9 1067 p_response = &responses[1]; order = 2;
0194ce8f 1068 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received request for UID (cascade 2)
ce02f6f9 1069 p_response = &responses[2]; order = 20;
0194ce8f 1070 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received a SELECT (cascade 1)
ce02f6f9 1071 p_response = &responses[3]; order = 3;
0194ce8f 1072 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received a SELECT (cascade 2)
1073 p_response = &responses[4]; order = 30;
1074 } else if(receivedCmd[0] == ISO14443A_CMD_READBLOCK) { // Received a (plain) READ
32719adf 1075 uint8_t block = receivedCmd[1];
2b1f4228 1076 // if Ultralight or NTAG (4 byte blocks)
1077 if ( tagType == 7 || tagType == 2 ) {
f38cfd66 1078 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
2b1f4228 1079 uint16_t start = 4 * (block+12);
6b23be6b 1080 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1081 emlGetMemBt( emdata, start, 16);
1082 AppendCrc14443a(emdata, 16);
1083 EmSendCmdEx(emdata, sizeof(emdata), false);
2b1f4228 1084 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
32719adf 1085 p_response = NULL;
2b1f4228 1086 } else { // all other tags (16 byte block tags)
6b23be6b 1087 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1088 emlGetMemBt( emdata, block, 16);
1089 AppendCrc14443a(emdata, 16);
1090 EmSendCmdEx(emdata, sizeof(emdata), false);
f38cfd66 1091 // EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
32719adf 1092 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1093 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1094 p_response = NULL;
1095 }
0194ce8f 1096 } else if(receivedCmd[0] == MIFARE_ULEV1_FASTREAD) { // Received a FAST READ (ranged read)
91c7a7cc 1097 uint8_t emdata[MAX_FRAME_SIZE];
f38cfd66 1098 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
91c7a7cc 1099 int start = (receivedCmd[1]+12) * 4;
1100 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
1101 emlGetMemBt( emdata, start, len);
1102 AppendCrc14443a(emdata, len);
1103 EmSendCmdEx(emdata, len+2, false);
1104 p_response = NULL;
0194ce8f 1105 } else if(receivedCmd[0] == MIFARE_ULEV1_READSIG && tagType == 7) { // Received a READ SIGNATURE --
f38cfd66 1106 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
91c7a7cc 1107 uint16_t start = 4 * 4;
1108 uint8_t emdata[34];
1109 emlGetMemBt( emdata, start, 32);
1110 AppendCrc14443a(emdata, 32);
1111 EmSendCmdEx(emdata, sizeof(emdata), false);
1112 p_response = NULL;
0194ce8f 1113 } else if (receivedCmd[0] == MIFARE_ULEV1_READ_CNT && tagType == 7) { // Received a READ COUNTER --
e9a92fe2 1114 uint8_t index = receivedCmd[1];
16cfceb6 1115 uint8_t cmd[] = {0x00,0x00,0x00,0x14,0xa5};
e9a92fe2 1116 if ( counters[index] > 0) {
16cfceb6 1117 num_to_bytes(counters[index], 3, cmd);
1118 AppendCrc14443a(cmd, sizeof(cmd)-2);
e9a92fe2 1119 }
16cfceb6 1120 EmSendCmdEx(cmd,sizeof(cmd),false);
a126332a 1121 p_response = NULL;
0194ce8f 1122 } else if (receivedCmd[0] == MIFARE_ULEV1_INCR_CNT && tagType == 7) { // Received a INC COUNTER --
ce3d6bd2 1123 // number of counter
a126332a 1124 uint8_t counter = receivedCmd[1];
1125 uint32_t val = bytes_to_num(receivedCmd+2,4);
1126 counters[counter] = val;
1127
ce3d6bd2 1128 // send ACK
1129 uint8_t ack[] = {0x0a};
1130 EmSendCmdEx(ack,sizeof(ack),false);
91c7a7cc 1131 p_response = NULL;
0194ce8f 1132 } else if(receivedCmd[0] == MIFARE_ULEV1_CHECKTEAR && tagType == 7) { // Received a CHECK_TEARING_EVENT --
f38cfd66 1133 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
2b1f4228 1134 uint8_t emdata[3];
1135 uint8_t counter=0;
1136 if (receivedCmd[1]<3) counter = receivedCmd[1];
1137 emlGetMemBt( emdata, 10+counter, 1);
1138 AppendCrc14443a(emdata, sizeof(emdata)-2);
1139 EmSendCmdEx(emdata, sizeof(emdata), false);
b0300679 1140 p_response = NULL;
0194ce8f 1141 } else if(receivedCmd[0] == ISO14443A_CMD_HALT) { // Received a HALT
810f5379 1142 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1143 p_response = NULL;
57850d9d 1144 } else if(receivedCmd[0] == MIFARE_AUTH_KEYA || receivedCmd[0] == MIFARE_AUTH_KEYB) { // Received an authentication request
32719adf 1145 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
2b1f4228 1146 uint8_t emdata[10];
1147 emlGetMemBt( emdata, 0, 8 );
1148 AppendCrc14443a(emdata, sizeof(emdata)-2);
6b23be6b 1149 EmSendCmdEx(emdata, sizeof(emdata), false);
2b1f4228 1150 p_response = NULL;
32719adf 1151 } else {
84bdbc19 1152
1153 cardAUTHKEY = receivedCmd[0] - 0x60;
1154 cardAUTHSC = receivedCmd[1] / 4; // received block num
7e735c13 1155
84bdbc19 1156 // incease nonce at AUTH requests. this is time consuming.
7e735c13 1157 nonce = prand();
84bdbc19 1158 //num_to_bytes(nonce, 4, response5);
1159 num_to_bytes(nonce, 4, dynamic_response_info.response);
1160 dynamic_response_info.response_n = 4;
1161
1162 //prepare_tag_modulation(&responses[5], DYNAMIC_MODULATION_BUFFER_SIZE);
1163 prepare_tag_modulation(&dynamic_response_info, DYNAMIC_MODULATION_BUFFER_SIZE);
1164 p_response = &dynamic_response_info;
1165 //p_response = &responses[5];
1166 order = 7;
32719adf 1167 }
0194ce8f 1168 } else if(receivedCmd[0] == ISO14443A_CMD_RATS) { // Received a RATS request
7bc95e2e 1169 if (tagType == 1 || tagType == 2) { // RATS not supported
1170 EmSend4bit(CARD_NACK_NA);
1171 p_response = NULL;
1172 } else {
1173 p_response = &responses[6]; order = 70;
1174 }
6a1f2d82 1175 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
810f5379 1176 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1177 uint32_t nr = bytes_to_num(receivedCmd,4);
1178 uint32_t ar = bytes_to_num(receivedCmd+4,4);
7e735c13 1179
6b23be6b 1180 // Collect AR/NR per keytype & sector
bc939371 1181 if ( (flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) {
bf5d7992 1182
84bdbc19 1183 int8_t index = -1;
1184 int8_t empty = -1;
1185 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
1186 // find which index to use
1187 if ( (cardAUTHSC == ar_nr_nonces[i].sector) && (cardAUTHKEY == ar_nr_nonces[i].keytype))
1188 index = i;
1189
1190 // keep track of empty slots.
1191 if ( ar_nr_nonces[i].state == EMPTY)
1192 empty = i;
1193 }
1194 // if no empty slots. Choose first and overwrite.
1195 if ( index == -1 ) {
1196 if ( empty == -1 ) {
1197 index = 0;
1198 ar_nr_nonces[index].state = EMPTY;
1199 } else {
1200 index = empty;
1201 }
1202 }
1203
1204 switch(ar_nr_nonces[index].state) {
1205 case EMPTY: {
1206 // first nonce collect
1207 ar_nr_nonces[index].cuid = cuid;
1208 ar_nr_nonces[index].sector = cardAUTHSC;
1209 ar_nr_nonces[index].keytype = cardAUTHKEY;
1210 ar_nr_nonces[index].nonce = nonce;
1211 ar_nr_nonces[index].nr = nr;
1212 ar_nr_nonces[index].ar = ar;
1213 ar_nr_nonces[index].state = FIRST;
1214 break;
1215 }
1216 case FIRST : {
1217 // second nonce collect
1218 ar_nr_nonces[index].nonce2 = nonce;
1219 ar_nr_nonces[index].nr2 = nr;
1220 ar_nr_nonces[index].ar2 = ar;
1221 ar_nr_nonces[index].state = SECOND;
1222
1223 // send to client
1224 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, 0, 0, &ar_nr_nonces[index], sizeof(nonces_t));
bf5d7992 1225
84bdbc19 1226 ar_nr_nonces[index].state = EMPTY;
1227 ar_nr_nonces[index].sector = 0;
1228 ar_nr_nonces[index].keytype = 0;
1229
1230 moebius_count++;
1231 break;
d26849d4 1232 }
84bdbc19 1233 default: break;
d26849d4 1234 }
84bdbc19 1235 }
1236 p_response = NULL;
57850d9d 1237
0194ce8f 1238 } else if (receivedCmd[0] == MIFARE_ULC_AUTH_1 ) { // ULC authentication, or Desfire Authentication
1239 } else if (receivedCmd[0] == MIFARE_ULEV1_AUTH) { // NTAG / EV-1 authentication
32719adf 1240 if ( tagType == 7 ) {
f38cfd66 1241 uint16_t start = 13; // first 4 blocks of emu are [getversion answer - check tearing - pack - 0x00]
2b1f4228 1242 uint8_t emdata[4];
1243 emlGetMemBt( emdata, start, 2);
1244 AppendCrc14443a(emdata, 2);
1245 EmSendCmdEx(emdata, sizeof(emdata), false);
1246 p_response = NULL;
ce3d6bd2 1247 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
e98572a1 1248
91c7a7cc 1249 if ( MF_DBGLEVEL >= 3) Dbprintf("Auth attempt: %08x", pwd);
32719adf 1250 }
2b1f4228 1251 } else {
7bc95e2e 1252 // Check for ISO 14443A-4 compliant commands, look at left nibble
1253 switch (receivedCmd[0]) {
7838f4be 1254 case 0x02:
1255 case 0x03: { // IBlock (command no CID)
1256 dynamic_response_info.response[0] = receivedCmd[0];
1257 dynamic_response_info.response[1] = 0x90;
1258 dynamic_response_info.response[2] = 0x00;
1259 dynamic_response_info.response_n = 3;
1260 } break;
7bc95e2e 1261 case 0x0B:
7838f4be 1262 case 0x0A: { // IBlock (command CID)
7bc95e2e 1263 dynamic_response_info.response[0] = receivedCmd[0];
1264 dynamic_response_info.response[1] = 0x00;
1265 dynamic_response_info.response[2] = 0x90;
1266 dynamic_response_info.response[3] = 0x00;
1267 dynamic_response_info.response_n = 4;
1268 } break;
1269
1270 case 0x1A:
1271 case 0x1B: { // Chaining command
1272 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1273 dynamic_response_info.response_n = 2;
1274 } break;
1275
7e735c13 1276 case 0xAA:
1277 case 0xBB: {
7bc95e2e 1278 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1279 dynamic_response_info.response_n = 2;
1280 } break;
1281
7838f4be 1282 case 0xBA: { // ping / pong
1283 dynamic_response_info.response[0] = 0xAB;
1284 dynamic_response_info.response[1] = 0x00;
1285 dynamic_response_info.response_n = 2;
7bc95e2e 1286 } break;
1287
1288 case 0xCA:
1289 case 0xC2: { // Readers sends deselect command
7838f4be 1290 dynamic_response_info.response[0] = 0xCA;
1291 dynamic_response_info.response[1] = 0x00;
1292 dynamic_response_info.response_n = 2;
7bc95e2e 1293 } break;
1294
1295 default: {
1296 // Never seen this command before
810f5379 1297 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1298 Dbprintf("Received unknown command (len=%d):",len);
1299 Dbhexdump(len,receivedCmd,false);
1300 // Do not respond
1301 dynamic_response_info.response_n = 0;
1302 } break;
1303 }
ce02f6f9 1304
7bc95e2e 1305 if (dynamic_response_info.response_n > 0) {
1306 // Copy the CID from the reader query
1307 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1308
7bc95e2e 1309 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
7e735c13 1310 AppendCrc14443a(dynamic_response_info.response, dynamic_response_info.response_n);
7bc95e2e 1311 dynamic_response_info.response_n += 2;
ce02f6f9 1312
7bc95e2e 1313 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
84bdbc19 1314 DbpString("Error preparing tag response");
810f5379 1315 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1316 break;
1317 }
1318 p_response = &dynamic_response_info;
1319 }
81cd0474 1320 }
15c4dc5a 1321
1322 // Count number of wakeups received after a halt
1323 if(order == 6 && lastorder == 5) { happened++; }
1324
1325 // Count number of other messages after a halt
1326 if(order != 6 && lastorder == 5) { happened2++; }
1327
bc939371 1328 // comment this limit if you want to simulation longer
1329 if (!tracing) {
7e735c13 1330 DbpString("Trace Full. Simulation stopped.");
bc939371 1331 break;
1332 }
91c7a7cc 1333 // comment this limit if you want to simulation longer
15c4dc5a 1334 if(cmdsRecvd > 999) {
1335 DbpString("1000 commands later...");
254b70a4 1336 break;
15c4dc5a 1337 }
ce02f6f9 1338 cmdsRecvd++;
1339
1340 if (p_response != NULL) {
7bc95e2e 1341 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1342 // do the tracing for the previous reader request and this tag answer:
810f5379 1343 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1344 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1345
7bc95e2e 1346 EmLogTrace(Uart.output,
1347 Uart.len,
1348 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1349 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1350 Uart.parity,
7bc95e2e 1351 p_response->response,
1352 p_response->response_n,
1353 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1354 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1355 par);
7bc95e2e 1356 }
7bc95e2e 1357 }
15c4dc5a 1358
d26849d4 1359 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 1360 set_tracing(FALSE);
f71f4deb 1361 BigBuf_free_keep_EM();
c9216a92 1362 LED_A_OFF();
7e735c13 1363
0de8e387 1364 if (MF_DBGLEVEL >= 4){
84bdbc19 1365 Dbprintf("-[ Wake ups after halt [%d]", happened);
1366 Dbprintf("-[ Messages after halt [%d]", happened2);
1367 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
1368 Dbprintf("-[ Num of moebius tries [%d]", moebius_count);
0de8e387 1369 }
e99acd00 1370
1371 cmd_send(CMD_ACK,1,0,0,0,0);
15c4dc5a 1372}
1373
9492e0b0 1374// prepare a delayed transfer. This simply shifts ToSend[] by a number
1375// of bits specified in the delay parameter.
0194ce8f 1376void PrepareDelayedTransfer(uint16_t delay) {
7504dc50 1377 delay &= 0x07;
1378 if (!delay) return;
1379
9492e0b0 1380 uint8_t bitmask = 0;
1381 uint8_t bits_to_shift = 0;
1382 uint8_t bits_shifted = 0;
7504dc50 1383 uint16_t i = 0;
1384
1385 for (i = 0; i < delay; ++i)
1386 bitmask |= (0x01 << i);
2285d9dd 1387
6fc68747 1388 ToSend[++ToSendMax] = 0x00;
7504dc50 1389
1390 for (i = 0; i < ToSendMax; ++i) {
9492e0b0 1391 bits_to_shift = ToSend[i] & bitmask;
1392 ToSend[i] = ToSend[i] >> delay;
1393 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1394 bits_shifted = bits_to_shift;
1395 }
1396 }
9492e0b0 1397
7bc95e2e 1398
1399//-------------------------------------------------------------------------------------
15c4dc5a 1400// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1401// Parameter timing:
7bc95e2e 1402// if NULL: transfer at next possible time, taking into account
1403// request guard time and frame delay time
1404// if == 0: transfer immediately and return time of transfer
9492e0b0 1405// if != 0: delay transfer until time specified
7bc95e2e 1406//-------------------------------------------------------------------------------------
0194ce8f 1407static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing) {
9492e0b0 1408 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1409
7bc95e2e 1410 uint32_t ThisTransferTime = 0;
e30c654b 1411
9492e0b0 1412 if (timing) {
ca5bad3d 1413 if(*timing == 0) { // Measure time
7bc95e2e 1414 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
ca5bad3d 1415 } else {
1416 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1417 }
1418 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1419 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
7bc95e2e 1420 LastTimeProxToAirStart = *timing;
1421 } else {
1422 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
7504dc50 1423
7bc95e2e 1424 while(GetCountSspClk() < ThisTransferTime);
7504dc50 1425
7bc95e2e 1426 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1427 }
1428
7bc95e2e 1429 // clear TXRDY
1430 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1431
7bc95e2e 1432 uint16_t c = 0;
9492e0b0 1433 for(;;) {
1434 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1435 AT91C_BASE_SSC->SSC_THR = cmd[c];
4c0cf2d2 1436 ++c;
5ebcb867 1437 if(c >= len)
9492e0b0 1438 break;
9492e0b0 1439 }
1440 }
7bc95e2e 1441
1442 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1443}
1444
15c4dc5a 1445//-----------------------------------------------------------------------------
195af472 1446// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1447//-----------------------------------------------------------------------------
6b23be6b 1448void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity) {
7bc95e2e 1449 int i, j;
5ebcb867 1450 int last = 0;
7bc95e2e 1451 uint8_t b;
e30c654b 1452
7bc95e2e 1453 ToSendReset();
e30c654b 1454
7bc95e2e 1455 // Start of Communication (Seq. Z)
1456 ToSend[++ToSendMax] = SEC_Z;
1457 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
7bc95e2e 1458
1459 size_t bytecount = nbytes(bits);
1460 // Generate send structure for the data bits
1461 for (i = 0; i < bytecount; i++) {
1462 // Get the current byte to send
1463 b = cmd[i];
1464 size_t bitsleft = MIN((bits-(i*8)),8);
1465
1466 for (j = 0; j < bitsleft; j++) {
1467 if (b & 1) {
1468 // Sequence X
1469 ToSend[++ToSendMax] = SEC_X;
1470 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1471 last = 1;
1472 } else {
1473 if (last == 0) {
1474 // Sequence Z
1475 ToSend[++ToSendMax] = SEC_Z;
1476 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1477 } else {
1478 // Sequence Y
1479 ToSend[++ToSendMax] = SEC_Y;
1480 last = 0;
1481 }
1482 }
1483 b >>= 1;
1484 }
1485
6a1f2d82 1486 // Only transmit parity bit if we transmitted a complete byte
0ec548dc 1487 if (j == 8 && parity != NULL) {
7bc95e2e 1488 // Get the parity bit
6a1f2d82 1489 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1490 // Sequence X
1491 ToSend[++ToSendMax] = SEC_X;
1492 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1493 last = 1;
1494 } else {
1495 if (last == 0) {
1496 // Sequence Z
1497 ToSend[++ToSendMax] = SEC_Z;
1498 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1499 } else {
1500 // Sequence Y
1501 ToSend[++ToSendMax] = SEC_Y;
1502 last = 0;
1503 }
1504 }
1505 }
1506 }
e30c654b 1507
7bc95e2e 1508 // End of Communication: Logic 0 followed by Sequence Y
1509 if (last == 0) {
1510 // Sequence Z
1511 ToSend[++ToSendMax] = SEC_Z;
1512 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1513 } else {
1514 // Sequence Y
1515 ToSend[++ToSendMax] = SEC_Y;
1516 last = 0;
1517 }
1518 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1519
7bc95e2e 1520 // Convert to length of command:
4b78d6b3 1521 ++ToSendMax;
15c4dc5a 1522}
1523
195af472 1524//-----------------------------------------------------------------------------
1525// Prepare reader command to send to FPGA
1526//-----------------------------------------------------------------------------
0194ce8f 1527void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity) {
ca5bad3d 1528 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1529}
1530
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1531//-----------------------------------------------------------------------------
1532// Wait for commands from reader
1533// Stop when button is pressed (return 1) or field was gone (return 2)
1534// Or return 0 when command is captured
1535//-----------------------------------------------------------------------------
99136c6e 1536int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity) {
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1537 *len = 0;
1538
1539 uint32_t timer = 0, vtime = 0;
1540 int analogCnt = 0;
1541 int analogAVG = 0;
1542
1543 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1544 // only, since we are receiving, not transmitting).
1545 // Signal field is off with the appropriate LED
1546 LED_D_OFF();
1547 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1548
1549 // Set ADC to read field strength
1550 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1551 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1552 ADC_MODE_PRESCALE(63) |
1553 ADC_MODE_STARTUP_TIME(1) |
1554 ADC_MODE_SAMPLE_HOLD_TIME(15);
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1555 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1556 // start ADC
1557 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1558
1559 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1560 UartInit(received, parity);
7bc95e2e 1561
1562 // Clear RXRDY:
1563 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1564
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1565 for(;;) {
1566 WDT_HIT();
1567
1568 if (BUTTON_PRESS()) return 1;
1569
1570 // test if the field exists
1571 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1572 analogCnt++;
1573 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1574 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1575 if (analogCnt >= 32) {
0c8d25eb 1576 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
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1577 vtime = GetTickCount();
1578 if (!timer) timer = vtime;
1579 // 50ms no field --> card to idle state
1580 if (vtime - timer > 50) return 2;
1581 } else
1582 if (timer) timer = 0;
1583 analogCnt = 0;
1584 analogAVG = 0;
1585 }
1586 }
7bc95e2e 1587
9ca155ba 1588 // receive and test the miller decoding
7bc95e2e 1589 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1590 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1591 if(MillerDecoding(b, 0)) {
1592 *len = Uart.len;
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1593 return 0;
1594 }
7bc95e2e 1595 }
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1596 }
1597}
1598
0194ce8f 1599int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded) {
7bc95e2e 1600 uint8_t b;
1601 uint16_t i = 0;
1602 uint32_t ThisTransferTime;
1603
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1604 // Modulate Manchester
1605 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1606
1607 // include correction bit if necessary
1608 if (Uart.parityBits & 0x01) {
1609 correctionNeeded = TRUE;
1610 }
0194ce8f 1611 // 1236, so correction bit needed
1612 i = (correctionNeeded) ? 0 : 1;
7bc95e2e 1613
d714d3ef 1614 // clear receiving shift register and holding register
7bc95e2e 1615 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1616 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1617 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1618 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1619
7bc95e2e 1620 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
b070f4e4 1621 for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
7bc95e2e 1622 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1623 if (AT91C_BASE_SSC->SSC_RHR) break;
1624 }
1625
1626 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1627
1628 // Clear TXRDY:
1629 AT91C_BASE_SSC->SSC_THR = SEC_F;
1630
9ca155ba 1631 // send cycle
bb42a03e 1632 for(; i < respLen; ) {
9ca155ba 1633 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1634 AT91C_BASE_SSC->SSC_THR = resp[i++];
1635 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1636 }
7bc95e2e 1637
17ad0e09 1638 if(BUTTON_PRESS()) break;
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1639 }
1640
7bc95e2e 1641 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
4b78d6b3 1642 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3; // twich /8 ?? >>3,
0c8d25eb 1643 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
7bc95e2e 1644 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1645 AT91C_BASE_SSC->SSC_THR = SEC_F;
1646 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1647 i++;
1648 }
1649 }
7bc95e2e 1650 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
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1651 return 0;
1652}
1653
7bc95e2e 1654int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1655 Code4bitAnswerAsTag(resp);
0a39986e 1656 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1657 // do the tracing for the previous reader request and this tag answer:
5ebcb867 1658 uint8_t par[1] = {0x00};
6a1f2d82 1659 GetParity(&resp, 1, par);
7bc95e2e 1660 EmLogTrace(Uart.output,
1661 Uart.len,
1662 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1663 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1664 Uart.parity,
7bc95e2e 1665 &resp,
1666 1,
1667 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1668 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1669 par);
0a39986e 1670 return res;
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1671}
1672
8f51ddb0 1673int EmSend4bit(uint8_t resp){
7bc95e2e 1674 return EmSend4bitEx(resp, false);
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1675}
1676
6a1f2d82 1677int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1678 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1679 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1680 // do the tracing for the previous reader request and this tag answer:
1681 EmLogTrace(Uart.output,
1682 Uart.len,
1683 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1684 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1685 Uart.parity,
7bc95e2e 1686 resp,
1687 respLen,
1688 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1689 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1690 par);
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1691 return res;
1692}
1693
6a1f2d82 1694int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
5ebcb867 1695 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1696 GetParity(resp, respLen, par);
1697 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
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1698}
1699
6a1f2d82 1700int EmSendCmd(uint8_t *resp, uint16_t respLen){
5ebcb867 1701 uint8_t par[MAX_PARITY_SIZE] = {0x00};
6a1f2d82 1702 GetParity(resp, respLen, par);
1703 return EmSendCmdExPar(resp, respLen, false, par);
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1704}
1705
6a1f2d82 1706int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1707 return EmSendCmdExPar(resp, respLen, false, par);
1708}
1709
6a1f2d82 1710bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1711 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1712{
810f5379 1713 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1714 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1715 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1716 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1717 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1718 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1719 reader_EndTime = tag_StartTime - exact_fdt;
1720 reader_StartTime = reader_EndTime - reader_modlen;
5ebcb867 1721
810f5379 1722 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE))
1723 return FALSE;
1724 else
1725 return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1726
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1727}
1728
15c4dc5a 1729//-----------------------------------------------------------------------------
1730// Wait a certain time for tag response
1731// If a response is captured return TRUE
e691fc45 1732// If it takes too long return FALSE
15c4dc5a 1733//-----------------------------------------------------------------------------
0194ce8f 1734static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset) {
46c65fed 1735 uint32_t c = 0x00;
e691fc45 1736
15c4dc5a 1737 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1738 // only, since we are receiving, not transmitting).
1739 // Signal field is on with the appropriate LED
1740 LED_D_ON();
1741 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1742
534983d7 1743 // Now get the answer from the card
6a1f2d82 1744 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1745
7bc95e2e 1746 // clear RXRDY:
1747 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1748
15c4dc5a 1749 for(;;) {
534983d7 1750 WDT_HIT();
15c4dc5a 1751
534983d7 1752 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1753 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1754 if(ManchesterDecoding(b, offset, 0)) {
1755 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1756 return TRUE;
19a700a8 1757 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
7bc95e2e 1758 return FALSE;
15c4dc5a 1759 }
534983d7 1760 }
1761 }
15c4dc5a 1762}
1763
0194ce8f 1764void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing) {
72e6d462 1765
6a1f2d82 1766 CodeIso14443aBitsAsReaderPar(frame, bits, par);
7bc95e2e 1767 // Send command to tag
1768 TransmitFor14443a(ToSend, ToSendMax, timing);
0194ce8f 1769 if(trigger) LED_A_ON();
dfc3c505 1770
4b78d6b3 1771 LogTrace(frame, nbytes(bits), (LastTimeProxToAirStart<<4) + DELAY_ARM2AIR_AS_READER, ((LastTimeProxToAirStart + LastProxToAirDuration)<<4) + DELAY_ARM2AIR_AS_READER, par, TRUE);
15c4dc5a 1772}
1773
0194ce8f 1774void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing) {
ca5bad3d 1775 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1776}
15c4dc5a 1777
0194ce8f 1778void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing) {
72e6d462 1779 // Generate parity and redirect
1780 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1781 GetParity(frame, len/8, par);
1782 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1783}
1784
0194ce8f 1785void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing) {
72e6d462 1786 // Generate parity and redirect
1787 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1788 GetParity(frame, len, par);
1789 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1790}
1791
0194ce8f 1792int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity) {
1793 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset))
1794 return FALSE;
1795 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
e691fc45 1796 return Demod.len;
1797}
1798
91c7a7cc 1799int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity) {
0194ce8f 1800 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0))
1801 return FALSE;
91c7a7cc 1802 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
e691fc45 1803 return Demod.len;
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1804}
1805
c188b1b9 1806// performs iso14443a anticollision (optional) and card select procedure
1807// fills the uid and cuid pointer unless NULL
1808// fills the card info record unless NULL
1809// if anticollision is false, then the UID must be provided in uid_ptr[]
1810// and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1811int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades) {
f8850434 1812 uint8_t wupa[] = { ISO14443A_CMD_WUPA }; // 0x26 - ISO14443A_CMD_REQA 0x52 - ISO14443A_CMD_WUPA
1813 uint8_t sel_all[] = { ISO14443A_CMD_ANTICOLL_OR_SELECT,0x20 };
1814 uint8_t sel_uid[] = { ISO14443A_CMD_ANTICOLL_OR_SELECT,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1815 uint8_t rats[] = { ISO14443A_CMD_RATS,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
4c0cf2d2 1816 uint8_t resp[MAX_FRAME_SIZE] = {0}; // theoretically. A usual RATS will be much smaller
1817 uint8_t resp_par[MAX_PARITY_SIZE] = {0};
1818 byte_t uid_resp[4] = {0};
1819 size_t uid_resp_len = 0;
6a1f2d82 1820
1821 uint8_t sak = 0x04; // cascade uid
1822 int cascade_level = 0;
1823 int len;
1824
1825 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
c188b1b9 1826 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
7bc95e2e 1827
6a1f2d82 1828 // Receive the ATQA
1829 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1830
1831 if(p_hi14a_card) {
1832 memcpy(p_hi14a_card->atqa, resp, 2);
1833 p_hi14a_card->uidlen = 0;
1834 memset(p_hi14a_card->uid,0,10);
1835 }
5f6d6c90 1836
c188b1b9 1837 if (anticollision) {
4c0cf2d2 1838 // clear uid
1839 if (uid_ptr)
1840 memset(uid_ptr,0,10);
c188b1b9 1841 }
79a73ab2 1842
5fba8581 1843 // reset the PCB block number
1844 iso14_pcb_blocknum = 0;
1845
0ec548dc 1846 // check for proprietary anticollision:
4c0cf2d2 1847 if ((resp[0] & 0x1F) == 0) return 3;
0ec548dc 1848
6a1f2d82 1849 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1850 // which case we need to make a cascade 2 request and select - this is a long UID
1851 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1852 for(; sak & 0x04; cascade_level++) {
1853 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1854 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1855
c188b1b9 1856 if (anticollision) {
6a1f2d82 1857 // SELECT_ALL
4c0cf2d2 1858 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1859 if (!ReaderReceive(resp, resp_par)) return 0;
1860
1861 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1862 memset(uid_resp, 0, 4);
1863 uint16_t uid_resp_bits = 0;
1864 uint16_t collision_answer_offset = 0;
1865 // anti-collision-loop:
1866 while (Demod.collisionPos) {
1867 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1868 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1869 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1870 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1871 }
1872 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1873 uid_resp_bits++;
1874 // construct anticollosion command:
1875 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1876 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1877 sel_uid[2+i] = uid_resp[i];
1878 }
1879 collision_answer_offset = uid_resp_bits%8;
1880 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1881 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
6a1f2d82 1882 }
4c0cf2d2 1883 // finally, add the last bits and BCC of the UID
1884 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1885 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1886 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1887 }
e691fc45 1888
4c0cf2d2 1889 } else { // no collision, use the response to SELECT_ALL as current uid
1890 memcpy(uid_resp, resp, 4);
1891 }
1892
c188b1b9 1893 } else {
1894 if (cascade_level < num_cascades - 1) {
1895 uid_resp[0] = 0x88;
1896 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1897 } else {
1898 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1899 }
1900 }
6a1f2d82 1901 uid_resp_len = 4;
5f6d6c90 1902
6a1f2d82 1903 // calculate crypto UID. Always use last 4 Bytes.
4c0cf2d2 1904 if(cuid_ptr)
6a1f2d82 1905 *cuid_ptr = bytes_to_num(uid_resp, 4);
e30c654b 1906
6a1f2d82 1907 // Construct SELECT UID command
1908 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
c188b1b9 1909 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
6a1f2d82 1910 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1911 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1912 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1913
1914 // Receive the SAK
1915 if (!ReaderReceive(resp, resp_par)) return 0;
4c0cf2d2 1916
6a1f2d82 1917 sak = resp[0];
1918
810f5379 1919 // Test if more parts of the uid are coming
6a1f2d82 1920 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1921 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1922 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1923 uid_resp[0] = uid_resp[1];
1924 uid_resp[1] = uid_resp[2];
1925 uid_resp[2] = uid_resp[3];
6a1f2d82 1926 uid_resp_len = 3;
1927 }
5f6d6c90 1928
4c0cf2d2 1929 if(uid_ptr && anticollision)
6a1f2d82 1930 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
5f6d6c90 1931
6a1f2d82 1932 if(p_hi14a_card) {
1933 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1934 p_hi14a_card->uidlen += uid_resp_len;
1935 }
1936 }
79a73ab2 1937
6a1f2d82 1938 if(p_hi14a_card) {
1939 p_hi14a_card->sak = sak;
1940 p_hi14a_card->ats_len = 0;
1941 }
534983d7 1942
3fe4ff4f 1943 // non iso14443a compliant tag
1944 if( (sak & 0x20) == 0) return 2;
534983d7 1945
6a1f2d82 1946 // Request for answer to select
1947 AppendCrc14443a(rats, 2);
1948 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1949
6a1f2d82 1950 if (!(len = ReaderReceive(resp, resp_par))) return 0;
3fe4ff4f 1951
6a1f2d82 1952 if(p_hi14a_card) {
1953 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1954 p_hi14a_card->ats_len = len;
1955 }
5f6d6c90 1956
19a700a8 1957 // set default timeout based on ATS
1958 iso14a_set_ATS_timeout(resp);
6a1f2d82 1959 return 1;
7e758047 1960}
15c4dc5a 1961
7bc95e2e 1962void iso14443a_setup(uint8_t fpga_minor_mode) {
be818b14 1963
7cc204bf 1964 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1965 // Set up the synchronous serial port
1966 FpgaSetupSsc();
7bc95e2e 1967 // connect Demodulated Signal to ADC:
7e758047 1968 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
91c7a7cc 1969
ca5bad3d 1970 LED_D_OFF();
7e758047 1971 // Signal field is on with the appropriate LED
ca5bad3d 1972 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD ||
1973 fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN)
7bc95e2e 1974 LED_D_ON();
6fc68747 1975
be818b14 1976 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
d5bded10 1977
1978 SpinDelay(20);
6fc68747 1979
1980 // Start the timer
1981 StartCountSspClk();
be818b14 1982
1983 // Prepare the demodulation functions
1984 DemodReset();
1985 UartReset();
1986 NextTransferTime = 2 * DELAY_ARM2AIR_AS_READER;
d5bded10 1987 iso14a_set_timeout(10*106); // 20ms default
7e758047 1988}
15c4dc5a 1989
6a1f2d82 1990int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
810f5379 1991 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
534983d7 1992 uint8_t real_cmd[cmd_len+4];
1993 real_cmd[0] = 0x0a; //I-Block
b0127e65 1994 // put block number into the PCB
1995 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 1996 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1997 memcpy(real_cmd+2, cmd, cmd_len);
1998 AppendCrc14443a(real_cmd,cmd_len+2);
1999
9492e0b0 2000 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 2001 size_t len = ReaderReceive(data, parity);
ca5bad3d 2002 //DATA LINK ERROR
2003 if (!len) return 0;
2004
6a1f2d82 2005 uint8_t *data_bytes = (uint8_t *) data;
ca5bad3d 2006
b0127e65 2007 // if we received an I- or R(ACK)-Block with a block number equal to the
2008 // current block number, toggle the current block number
ca5bad3d 2009 if (len >= 4 // PCB+CID+CRC = 4 bytes
b0127e65 2010 && ((data_bytes[0] & 0xC0) == 0 // I-Block
2011 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2012 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
2013 {
2014 iso14_pcb_blocknum ^= 1;
2015 }
534983d7 2016 return len;
2017}
2018
be818b14 2019
7e758047 2020//-----------------------------------------------------------------------------
2021// Read an ISO 14443a tag. Send out commands and store answers.
7e758047 2022//-----------------------------------------------------------------------------
91c7a7cc 2023void ReaderIso14443a(UsbCommand *c) {
534983d7 2024 iso14a_command_t param = c->arg[0];
04bc1c66 2025 size_t len = c->arg[1] & 0xffff;
2026 size_t lenbits = c->arg[1] >> 16;
2027 uint32_t timeout = c->arg[2];
91c7a7cc 2028 uint8_t *cmd = c->d.asBytes;
9492e0b0 2029 uint32_t arg0 = 0;
810f5379 2030 byte_t buf[USB_CMD_DATA_SIZE] = {0x00};
2031 uint8_t par[MAX_PARITY_SIZE] = {0x00};
902cb3c0 2032
810f5379 2033 if (param & ISO14A_CONNECT)
3000dc4e 2034 clear_trace();
e691fc45 2035
3000dc4e 2036 set_tracing(TRUE);
e30c654b 2037
810f5379 2038 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 2039 iso14a_set_trigger(TRUE);
15c4dc5a 2040
810f5379 2041 if (param & ISO14A_CONNECT) {
7bc95e2e 2042 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 2043 if(!(param & ISO14A_NO_SELECT)) {
2044 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
c188b1b9 2045 arg0 = iso14443a_select_card(NULL,card,NULL, true, 0);
91c7a7cc 2046 cmd_send(CMD_ACK, arg0, card->uidlen, 0, buf, sizeof(iso14a_card_select_t));
6fc68747 2047 // if it fails, the cmdhf14a.c client quites.. however this one still executes.
2048 if ( arg0 == 0 ) return;
5f6d6c90 2049 }
534983d7 2050 }
e30c654b 2051
810f5379 2052 if (param & ISO14A_SET_TIMEOUT)
04bc1c66 2053 iso14a_set_timeout(timeout);
e30c654b 2054
810f5379 2055 if (param & ISO14A_APDU) {
902cb3c0 2056 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 2057 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2058 }
e30c654b 2059
810f5379 2060 if (param & ISO14A_RAW) {
0f7279b2 2061 if (param & ISO14A_APPEND_CRC) {
2062 if (param & ISO14A_TOPAZMODE)
0ec548dc 2063 AppendCrc14443b(cmd,len);
0f7279b2 2064 else
d26849d4 2065 AppendCrc14443a(cmd,len);
0f7279b2 2066
534983d7 2067 len += 2;
c7324bef 2068 if (lenbits) lenbits += 16;
15c4dc5a 2069 }
0f7279b2 2070 if (lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2071 if (param & ISO14A_TOPAZMODE) {
0ec548dc 2072 int bits_to_send = lenbits;
2073 uint16_t i = 0;
2074 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2075 bits_to_send -= 7;
2076 while (bits_to_send > 0) {
2077 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2078 bits_to_send -= 8;
2079 }
2080 } else {
6a1f2d82 2081 GetParity(cmd, lenbits/8, par);
0ec548dc 2082 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2083 }
2084 } else { // want to send complete bytes only
0f7279b2 2085 if (param & ISO14A_TOPAZMODE) {
0ec548dc 2086 uint16_t i = 0;
2087 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2088 while (i < len) {
2089 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2090 }
5f6d6c90 2091 } else {
0ec548dc 2092 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2093 }
5f6d6c90 2094 }
6a1f2d82 2095 arg0 = ReaderReceive(buf, par);
9492e0b0 2096 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 2097 }
15c4dc5a 2098
810f5379 2099 if (param & ISO14A_REQUEST_TRIGGER)
7bc95e2e 2100 iso14a_set_trigger(FALSE);
15c4dc5a 2101
810f5379 2102 if (param & ISO14A_NO_DISCONNECT)
534983d7 2103 return;
15c4dc5a 2104
15c4dc5a 2105 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
5ee53a0e 2106 set_tracing(FALSE);
15c4dc5a 2107 LEDsoff();
15c4dc5a 2108}
b0127e65 2109
1c611bbd 2110// Determine the distance between two nonces.
2111// Assume that the difference is small, but we don't know which is first.
2112// Therefore try in alternating directions.
2113int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2114
ca5bad3d 2115 if (nt1 == nt2) return 0;
ca5bad3d 2116
91c7a7cc 2117 uint32_t nttmp1 = nt1;
2118 uint32_t nttmp2 = nt2;
2119
30daf914 2120 // 0xFFFF -- Half up and half down to find distance between nonces
2121 for (uint16_t i = 1; i < 32768/8; i += 8) {
bc939371 2122 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i;
be818b14 2123 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+1;
be818b14 2124 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+2;
be818b14 2125 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+3;
be818b14 2126 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+4;
be818b14 2127 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+5;
be818b14 2128 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+6;
be818b14 2129 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+7;
30daf914 2130
2131 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -i;
2132 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+1);
2133 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+2);
2134 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+3);
2135 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+4);
2136 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+5);
2137 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+6);
be818b14 2138 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+7);
2139 }
91c7a7cc 2140 // either nt1 or nt2 are invalid nonces
2141 return(-99999);
e772353f 2142}
2143
1c611bbd 2144//-----------------------------------------------------------------------------
2145// Recover several bits of the cypher stream. This implements (first stages of)
2146// the algorithm described in "The Dark Side of Security by Obscurity and
2147// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2148// (article by Nicolas T. Courtois, 2009)
2149//-----------------------------------------------------------------------------
f38cfd66 2150
df007486 2151void ReaderMifare(bool first_try, uint8_t block, uint8_t keytype ) {
2152
2153 uint8_t mf_auth[] = { keytype, block, 0x00, 0x00 };
b0300679 2154 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2155 uint8_t uid[10] = {0,0,0,0,0,0,0,0,0,0};
2156 uint8_t par_list[8] = {0,0,0,0,0,0,0,0};
2157 uint8_t ks_list[8] = {0,0,0,0,0,0,0,0};
495d7f13 2158 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = {0x00};
2159 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b0300679 2160 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2161 byte_t nt_diff = 0;
6a1f2d82 2162 uint32_t nt = 0;
b0300679 2163 uint32_t previous_nt = 0;
b0300679 2164 uint32_t cuid = 0;
2165
91c7a7cc 2166 int32_t catch_up_cycles = 0;
2167 int32_t last_catch_up = 0;
2168 int32_t isOK = 0;
2169 int32_t nt_distance = 0;
b0300679 2170
4c0cf2d2 2171 uint16_t elapsed_prng_sequences = 1;
1c611bbd 2172 uint16_t consecutive_resyncs = 0;
0de8e387 2173 uint16_t unexpected_random = 0;
2174 uint16_t sync_tries = 0;
b0300679 2175
bc939371 2176 // static variables here, is re-used in the next call
b0300679 2177 static uint32_t nt_attacked = 0;
2178 static uint32_t sync_time = 0;
91c7a7cc 2179 static uint32_t sync_cycles = 0;
b0300679 2180 static uint8_t par_low = 0;
2181 static uint8_t mf_nr_ar3 = 0;
91c7a7cc 2182
b0300679 2183 #define PRNG_SEQUENCE_LENGTH (1 << 16)
2184 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2185 #define MAX_SYNC_TRIES 32
df007486 2186
2187 AppendCrc14443a(mf_auth, 2);
2188
91c7a7cc 2189 BigBuf_free(); BigBuf_Clear_ext(false);
4b78d6b3 2190 clear_trace();
5fba8581 2191 set_tracing(FALSE);
91c7a7cc 2192 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
4c0cf2d2 2193
6067df30 2194 sync_time = GetCountSspClk() & 0xfffffff8;
ed8c2aeb 2195 sync_cycles = PRNG_SEQUENCE_LENGTH; // Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
f38cfd66 2196 nt_attacked = 0;
2197
dd83c457 2198 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare::Sync %u", sync_time);
f38cfd66 2199
6067df30 2200 if (first_try) {
f38cfd66 2201 mf_nr_ar3 = 0;
91c7a7cc 2202 par_low = 0;
4c0cf2d2 2203 } else {
b0300679 2204 // we were unsuccessful on a previous call.
2205 // Try another READER nonce (first 3 parity bits remain the same)
2206 ++mf_nr_ar3;
4c0cf2d2 2207 mf_nr_ar[3] = mf_nr_ar3;
2208 par[0] = par_low;
2209 }
91c7a7cc 2210
2211 bool have_uid = FALSE;
2212 uint8_t cascade_levels = 0;
2213
4c0cf2d2 2214 LED_C_ON();
91c7a7cc 2215 uint16_t i;
2216 for(i = 0; TRUE; ++i) {
4c0cf2d2 2217
1c611bbd 2218 WDT_HIT();
e30c654b 2219
1c611bbd 2220 // Test if the action was cancelled
c830303d 2221 if(BUTTON_PRESS()) {
2222 isOK = -1;
1c611bbd 2223 break;
2224 }
2225
91c7a7cc 2226 // this part is from Piwi's faster nonce collecting part in Hardnested.
2227 if (!have_uid) { // need a full select cycle to get the uid first
2228 iso14a_card_select_t card_info;
2229 if(!iso14443a_select_card(uid, &card_info, &cuid, true, 0)) {
2230 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (ALL)");
2231 break;
2232 }
2233 switch (card_info.uidlen) {
2234 case 4 : cascade_levels = 1; break;
2235 case 7 : cascade_levels = 2; break;
2236 case 10: cascade_levels = 3; break;
2237 default: break;
2238 }
2239 have_uid = TRUE;
2240 } else { // no need for anticollision. We can directly select the card
2241 if(!iso14443a_select_card(uid, NULL, &cuid, false, cascade_levels)) {
2242 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (UID)");
2243 continue;
2244 }
1c611bbd 2245 }
4c0cf2d2 2246
91c7a7cc 2247 // Sending timeslot of ISO14443a frame
2248 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles + catch_up_cycles;
4b78d6b3 2249 catch_up_cycles = 0;
2250
2251 // if we missed the sync time already, advance to the next nonce repeat
91c7a7cc 2252 while( GetCountSspClk() > sync_time) {
4b78d6b3 2253 ++elapsed_prng_sequences;
91c7a7cc 2254 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles;
2255 }
2256
2257 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2258 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2259
91c7a7cc 2260 // Receive the (4 Byte) "random" nonce from TAG
4c0cf2d2 2261 if (!ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2262 continue;
1c611bbd 2263
4b78d6b3 2264 previous_nt = nt;
2265 nt = bytes_to_num(receivedAnswer, 4);
2266
91c7a7cc 2267 // Transmit reader nonce with fake par
2268 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2269
6067df30 2270 // we didn't calibrate our clock yet,
2271 // iceman: has to be calibrated every time.
bcacb316 2272 if (previous_nt && !nt_attacked) {
91c7a7cc 2273
2274 nt_distance = dist_nt(previous_nt, nt);
2275
2276 // if no distance between, then we are in sync.
1c611bbd 2277 if (nt_distance == 0) {
2278 nt_attacked = nt;
0de8e387 2279 } else {
c830303d 2280 if (nt_distance == -99999) { // invalid nonce received
91c7a7cc 2281 ++unexpected_random;
3bc7b13d 2282 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
c830303d 2283 isOK = -3; // Card has an unpredictable PRNG. Give up
2284 break;
91c7a7cc 2285 } else {
2286 if (sync_cycles <= 0) sync_cycles += PRNG_SEQUENCE_LENGTH;
2287 LED_B_OFF();
c830303d 2288 continue; // continue trying...
2289 }
1c611bbd 2290 }
4c0cf2d2 2291
0de8e387 2292 if (++sync_tries > MAX_SYNC_TRIES) {
91c7a7cc 2293 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2294 break;
0de8e387 2295 }
4c0cf2d2 2296
4b78d6b3 2297 sync_cycles = (sync_cycles - nt_distance)/elapsed_prng_sequences;
91c7a7cc 2298
4c0cf2d2 2299 if (sync_cycles <= 0)
0de8e387 2300 sync_cycles += PRNG_SEQUENCE_LENGTH;
4c0cf2d2 2301
91c7a7cc 2302 if (MF_DBGLEVEL >= 4)
3bc7b13d 2303 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
4c0cf2d2 2304
91c7a7cc 2305 LED_B_OFF();
1c611bbd 2306 continue;
2307 }
2308 }
91c7a7cc 2309 LED_B_OFF();
1c611bbd 2310
ed8c2aeb 2311 if ( (nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
4c0cf2d2 2312
91c7a7cc 2313 catch_up_cycles = ABS(dist_nt(nt_attacked, nt));
c830303d 2314 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
1c611bbd 2315 catch_up_cycles = 0;
2316 continue;
91c7a7cc 2317 }
4c0cf2d2 2318 // average?
3bc7b13d 2319 catch_up_cycles /= elapsed_prng_sequences;
4c0cf2d2 2320
1c611bbd 2321 if (catch_up_cycles == last_catch_up) {
4a71da5a 2322 ++consecutive_resyncs;
4c0cf2d2 2323 } else {
1c611bbd 2324 last_catch_up = catch_up_cycles;
2325 consecutive_resyncs = 0;
4b78d6b3 2326 }
4c0cf2d2 2327
1c611bbd 2328 if (consecutive_resyncs < 3) {
91c7a7cc 2329 if (MF_DBGLEVEL >= 4)
2330 Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, catch_up_cycles, consecutive_resyncs);
4c0cf2d2 2331 } else {
2332 sync_cycles += catch_up_cycles;
2333
91c7a7cc 2334 if (MF_DBGLEVEL >= 4)
2335 Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, catch_up_cycles, sync_cycles);
4c0cf2d2 2336
3bc7b13d 2337 last_catch_up = 0;
2338 catch_up_cycles = 0;
2339 consecutive_resyncs = 0;
1c611bbd 2340 }
2341 continue;
2342 }
2343
1c611bbd 2344 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
91c7a7cc 2345 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2346 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2347
495d7f13 2348 if (nt_diff == 0)
6a1f2d82 2349 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2350
6a1f2d82 2351 par_list[nt_diff] = SwapBits(par[0], 8);
91c7a7cc 2352 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; // xor with NACK value to get keystream
1c611bbd 2353
2354 // Test if the information is complete
2355 if (nt_diff == 0x07) {
2356 isOK = 1;
2357 break;
2358 }
2359
2360 nt_diff = (nt_diff + 1) & 0x07;
2361 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2362 par[0] = par_low;
4b78d6b3 2363
1c611bbd 2364 } else {
b0300679 2365 // No NACK.
495d7f13 2366 if (nt_diff == 0 && first_try) {
6a1f2d82 2367 par[0]++;
5ebcb867 2368 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
c830303d 2369 isOK = -2;
2370 break;
2371 }
1c611bbd 2372 } else {
b0300679 2373 // Why this?
6a1f2d82 2374 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2375 }
2376 }
4b78d6b3 2377
91c7a7cc 2378 // reset the resyncs since we got a complete transaction on right time.
4b78d6b3 2379 consecutive_resyncs = 0;
91c7a7cc 2380 } // end for loop
1c611bbd 2381
1c611bbd 2382 mf_nr_ar[3] &= 0x1F;
5ebcb867 2383
bc939371 2384 if (MF_DBGLEVEL >= 4) Dbprintf("Number of sent auth requestes: %u", i);
d26849d4 2385
b0300679 2386 uint8_t buf[28] = {0x00};
91c7a7cc 2387 memset(buf, 0x00, sizeof(buf));
b0300679 2388 num_to_bytes(cuid, 4, buf);
1c611bbd 2389 num_to_bytes(nt, 4, buf + 4);
2390 memcpy(buf + 8, par_list, 8);
2391 memcpy(buf + 16, ks_list, 8);
2392 memcpy(buf + 24, mf_nr_ar, 4);
2393
91c7a7cc 2394 cmd_send(CMD_ACK, isOK, 0, 0, buf, sizeof(buf) );
1c611bbd 2395
1c611bbd 2396 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2397 LEDsoff();
99cf19d9 2398 set_tracing(FALSE);
20f9a2a1 2399}
1c611bbd 2400
f38cfd66 2401
0de8e387 2402/**
d2f487af 2403 *MIFARE 1K simulate.
2404 *
2405 *@param flags :
0194ce8f 2406 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2407 * FLAG_4B_UID_IN_DATA - use 4-byte UID in the data-section
2408 * FLAG_7B_UID_IN_DATA - use 7-byte UID in the data-section
2409 * FLAG_10B_UID_IN_DATA - use 10-byte UID in the data-section
2410 * FLAG_UID_IN_EMUL - use 4-byte UID from emulator memory
2411 * FLAG_NR_AR_ATTACK - collect NR_AR responses for bruteforcing later
d2f487af 2412 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2413 */
91c7a7cc 2414void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain) {
e99acd00 2415
2416 // init pseudorand
2417 fast_prand( GetTickCount() );
2418
50193c1e 2419 int cardSTATE = MFEMUL_NOFIELD;
0194ce8f 2420 int _UID_LEN = 0; // 4, 7, 10
9ca155ba 2421 int vHf = 0; // in mV
0194ce8f 2422 int res = 0;
0a39986e
M
2423 uint32_t selTimer = 0;
2424 uint32_t authTimer = 0;
6a1f2d82 2425 uint16_t len = 0;
8f51ddb0 2426 uint8_t cardWRBL = 0;
9ca155ba
M
2427 uint8_t cardAUTHSC = 0;
2428 uint8_t cardAUTHKEY = 0xff; // no authentication
2429 uint32_t cuid = 0;
51969283 2430 uint32_t ans = 0;
0014cb46
M
2431 uint32_t cardINTREG = 0;
2432 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2433 struct Crypto1State mpcs = {0, 0};
2434 struct Crypto1State *pcs;
2435 pcs = &mpcs;
f38cfd66 2436 uint32_t numReads = 0; // Counts numer of times reader read a block
5ebcb867 2437 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2438 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2439 uint8_t response[MAX_MIFARE_FRAME_SIZE] = {0x00};
2440 uint8_t response_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
9ca155ba 2441
bc939371 2442 uint8_t atqa[] = {0x04, 0x00}; // Mifare classic 1k
2443 uint8_t sak_4[] = {0x0C, 0x00, 0x00}; // CL1 - 4b uid
2444 uint8_t sak_7[] = {0x0C, 0x00, 0x00}; // CL2 - 7b uid
2445 uint8_t sak_10[] = {0x0C, 0x00, 0x00}; // CL3 - 10b uid
f38cfd66 2446 // uint8_t sak[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
0194ce8f 2447
2448 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2449 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2450 uint8_t rUIDBCC3[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2451
bf5d7992 2452 // TAG Nonce - Authenticate response
2453 uint8_t rAUTH_NT[4];
2454 uint32_t nonce = prand();
2455 num_to_bytes(nonce, 4, rAUTH_NT);
2456
f38cfd66 2457 // uint8_t rAUTH_NT[] = {0x55, 0x41, 0x49, 0x92};// nonce from nested? why this?
d2f487af 2458 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
bf5d7992 2459
bc939371 2460 // Here, we collect CUID, NT, NR, AR, CUID2, NT2, NR2, AR2
d2f487af 2461 // This can be used in a reader-only attack.
84bdbc19 2462 nonces_t ar_nr_nonces[ATTACK_KEY_COUNT];
2463 memset(ar_nr_nonces, 0x00, sizeof(ar_nr_nonces));
0014cb46 2464
f38cfd66 2465 // -- Determine the UID
0194ce8f 2466 // Can be set from emulator memory or incoming data
2467 // Length: 4,7,or 10 bytes
bc939371 2468 if ( (flags & FLAG_UID_IN_EMUL) == FLAG_UID_IN_EMUL)
2469 emlGetMemBt(datain, 0, 10); // load 10bytes from EMUL to the datain pointer. to be used below.
2470
2471 if ( (flags & FLAG_4B_UID_IN_DATA) == FLAG_4B_UID_IN_DATA) {
0194ce8f 2472 memcpy(rUIDBCC1, datain, 4);
2473 _UID_LEN = 4;
bc939371 2474 } else if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA) {
0194ce8f 2475 memcpy(&rUIDBCC1[1], datain, 3);
2476 memcpy( rUIDBCC2, datain+3, 4);
2477 _UID_LEN = 7;
bc939371 2478 } else if ( (flags & FLAG_10B_UID_IN_DATA) == FLAG_10B_UID_IN_DATA) {
0194ce8f 2479 memcpy(&rUIDBCC1[1], datain, 3);
bc939371 2480 memcpy(&rUIDBCC2[1], datain+3, 3);
2481 memcpy( rUIDBCC3, datain+6, 4);
0194ce8f 2482 _UID_LEN = 10;
d2f487af 2483 }
7bc95e2e 2484
0194ce8f 2485 switch (_UID_LEN) {
2486 case 4:
bc939371 2487 sak_4[0] &= 0xFB;
0194ce8f 2488 // save CUID
b6e05350 2489 cuid = bytes_to_num(rUIDBCC1, 4);
0194ce8f 2490 // BCC
2491 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
bc939371 2492 if (MF_DBGLEVEL >= 2) {
0194ce8f 2493 Dbprintf("4B UID: %02x%02x%02x%02x",
2494 rUIDBCC1[0],
2495 rUIDBCC1[1],
2496 rUIDBCC1[2],
2497 rUIDBCC1[3]
2498 );
2499 }
2500 break;
2501 case 7:
2502 atqa[0] |= 0x40;
bc939371 2503 sak_7[0] &= 0xFB;
0194ce8f 2504 // save CUID
b6e05350 2505 cuid = bytes_to_num(rUIDBCC2, 4);
bc939371 2506 // CascadeTag, CT
2507 rUIDBCC1[0] = 0x88;
0194ce8f 2508 // BCC
2509 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2510 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
bc939371 2511 if (MF_DBGLEVEL >= 2) {
0194ce8f 2512 Dbprintf("7B UID: %02x %02x %02x %02x %02x %02x %02x",
0194ce8f 2513 rUIDBCC1[1],
2514 rUIDBCC1[2],
2515 rUIDBCC1[3],
2516 rUIDBCC2[0],
2517 rUIDBCC2[1],
2518 rUIDBCC2[2],
2519 rUIDBCC2[3]
2520 );
2521 }
2522 break;
2523 case 10:
bc939371 2524 atqa[0] |= 0x80;
2525 sak_10[0] &= 0xFB;
0194ce8f 2526 // save CUID
b6e05350 2527 cuid = bytes_to_num(rUIDBCC3, 4);
bc939371 2528 // CascadeTag, CT
2529 rUIDBCC1[0] = 0x88;
2530 rUIDBCC2[0] = 0x88;
0194ce8f 2531 // BCC
2532 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
0194ce8f 2533 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2534 rUIDBCC3[4] = rUIDBCC3[0] ^ rUIDBCC3[1] ^ rUIDBCC3[2] ^ rUIDBCC3[3];
bc939371 2535
2536 if (MF_DBGLEVEL >= 2) {
0194ce8f 2537 Dbprintf("10B UID: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
0194ce8f 2538 rUIDBCC1[1],
2539 rUIDBCC1[2],
2540 rUIDBCC1[3],
0194ce8f 2541 rUIDBCC2[1],
2542 rUIDBCC2[2],
2543 rUIDBCC2[3],
2544 rUIDBCC3[0],
2545 rUIDBCC3[1],
2546 rUIDBCC3[2],
2547 rUIDBCC3[3]
2548 );
2549 }
2550 break;
2551 default:
2552 break;
d2f487af 2553 }
bc939371 2554 // calc some crcs
2555 ComputeCrc14443(CRC_14443_A, sak_4, 1, &sak_4[1], &sak_4[2]);
2556 ComputeCrc14443(CRC_14443_A, sak_7, 1, &sak_7[1], &sak_7[2]);
2557 ComputeCrc14443(CRC_14443_A, sak_10, 1, &sak_10[1], &sak_10[2]);
2558
99cf19d9 2559 // We need to listen to the high-frequency, peak-detected path.
2560 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2561
2562 // free eventually allocated BigBuf memory but keep Emulator Memory
2563 BigBuf_free_keep_EM();
99cf19d9 2564 clear_trace();
2565 set_tracing(TRUE);
2566
7bc95e2e 2567 bool finished = FALSE;
2b1f4228 2568 while (!BUTTON_PRESS() && !finished && !usb_poll_validate_length()) {
9ca155ba 2569 WDT_HIT();
9ca155ba
M
2570
2571 // find reader field
9ca155ba 2572 if (cardSTATE == MFEMUL_NOFIELD) {
0c8d25eb 2573 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
9ca155ba 2574 if (vHf > MF_MINFIELDV) {
0014cb46 2575 cardSTATE_TO_IDLE();
9ca155ba
M
2576 LED_A_ON();
2577 }
2578 }
0194ce8f 2579 if (cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2580
f38cfd66 2581 // Now, get data
6a1f2d82 2582 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2583 if (res == 2) { //Field is off!
2584 cardSTATE = MFEMUL_NOFIELD;
2585 LEDsoff();
2586 continue;
7bc95e2e 2587 } else if (res == 1) {
f38cfd66 2588 break; // return value 1 means button press
7bc95e2e 2589 }
2590
d2f487af 2591 // REQ or WUP request in ANY state and WUP in HALTED state
57850d9d 2592 // this if-statement doesn't match the specification above. (iceman)
0194ce8f 2593 if (len == 1 && ((receivedCmd[0] == ISO14443A_CMD_REQA && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == ISO14443A_CMD_WUPA)) {
d2f487af 2594 selTimer = GetTickCount();
0194ce8f 2595 EmSendCmdEx(atqa, sizeof(atqa), (receivedCmd[0] == ISO14443A_CMD_WUPA));
d2f487af 2596 cardSTATE = MFEMUL_SELECT1;
d2f487af 2597 crypto1_destroy(pcs);
2598 cardAUTHKEY = 0xff;
0194ce8f 2599 LEDsoff();
bf5d7992 2600 nonce = prand();
d2f487af 2601 continue;
0a39986e 2602 }
7bc95e2e 2603
50193c1e 2604 switch (cardSTATE) {
d2f487af 2605 case MFEMUL_NOFIELD:
2606 case MFEMUL_HALTED:
50193c1e 2607 case MFEMUL_IDLE:{
6a1f2d82 2608 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2609 break;
2610 }
2611 case MFEMUL_SELECT1:{
0194ce8f 2612 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT && receivedCmd[1] == 0x20)) {
d2f487af 2613 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2614 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2615 break;
9ca155ba 2616 }
9ca155ba 2617 // select card
0a39986e 2618 if (len == 9 &&
0194ce8f 2619 ( receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT &&
2620 receivedCmd[1] == 0x70 &&
2621 memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2622
2623 // SAK 4b
2624 EmSendCmd(sak_4, sizeof(sak_4));
2625 switch(_UID_LEN){
2626 case 4:
2627 cardSTATE = MFEMUL_WORK;
2628 LED_B_ON();
2629 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2630 continue;
2631 case 7:
2632 case 10:
2633 cardSTATE = MFEMUL_SELECT2;
2634 continue;
2635 default:break;
8556b852 2636 }
0194ce8f 2637 } else {
2638 cardSTATE_TO_IDLE();
2639 }
2640 break;
2641 }
2642 case MFEMUL_SELECT2:{
2643 if (!len) {
2644 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2645 break;
2646 }
2647 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 && receivedCmd[1] == 0x20)) {
2648 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2649 break;
2650 }
2651 if (len == 9 &&
2652 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 &&
2653 receivedCmd[1] == 0x70 &&
2654 memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0) ) {
2655
2656 EmSendCmd(sak_7, sizeof(sak_7));
2657 switch(_UID_LEN){
2658 case 7:
2659 cardSTATE = MFEMUL_WORK;
2660 LED_B_ON();
2661 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2662 continue;
2663 case 10:
2664 cardSTATE = MFEMUL_SELECT3;
2665 continue;
2666 default:break;
2667 }
bc939371 2668 }
2669 cardSTATE_TO_IDLE();
0194ce8f 2670 break;
2671 }
2672 case MFEMUL_SELECT3:{
2673 if (!len) {
2674 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2675 break;
2676 }
2677 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 && receivedCmd[1] == 0x20)) {
2678 EmSendCmd(rUIDBCC3, sizeof(rUIDBCC3));
2679 break;
2680 }
2681 if (len == 9 &&
2682 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 &&
2683 receivedCmd[1] == 0x70 &&
2684 memcmp(&receivedCmd[2], rUIDBCC3, 4) == 0) ) {
2685
2686 EmSendCmd(sak_10, sizeof(sak_10));
2687 cardSTATE = MFEMUL_WORK;
2688 LED_B_ON();
2689 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol3 time: %d", GetTickCount() - selTimer);
2690 break;
9ca155ba 2691 }
bc939371 2692 cardSTATE_TO_IDLE();
50193c1e
M
2693 break;
2694 }
d2f487af 2695 case MFEMUL_AUTH1:{
495d7f13 2696 if( len != 8) {
d2f487af 2697 cardSTATE_TO_IDLE();
6a1f2d82 2698 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2699 break;
2700 }
0c8d25eb 2701
bc939371 2702 uint32_t nr = bytes_to_num(receivedCmd, 4);
2703 uint32_t ar = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2704
84bdbc19 2705 // Collect AR/NR per keytype & sector
2706 if ( (flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) {
bf5d7992 2707
84bdbc19 2708 int8_t index = -1;
2709 int8_t empty = -1;
2710 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
2711 // find which index to use
2712 if ( (cardAUTHSC == ar_nr_nonces[i].sector) && (cardAUTHKEY == ar_nr_nonces[i].keytype))
2713 index = i;
2714
2715 // keep track of empty slots.
2716 if ( ar_nr_nonces[i].state == EMPTY)
2717 empty = i;
2718 }
2719 // if no empty slots. Choose first and overwrite.
2720 if ( index == -1 ) {
2721 if ( empty == -1 ) {
2722 index = 0;
2723 ar_nr_nonces[index].state = EMPTY;
2724 } else {
2725 index = empty;
b6e05350 2726 }
b6e05350 2727 }
b6e05350 2728
84bdbc19 2729 switch(ar_nr_nonces[index].state) {
2730 case EMPTY: {
2731 // first nonce collect
2732 ar_nr_nonces[index].cuid = cuid;
2733 ar_nr_nonces[index].sector = cardAUTHSC;
2734 ar_nr_nonces[index].keytype = cardAUTHKEY;
2735 ar_nr_nonces[index].nonce = nonce;
2736 ar_nr_nonces[index].nr = nr;
2737 ar_nr_nonces[index].ar = ar;
2738 ar_nr_nonces[index].state = FIRST;
2739 break;
2740 }
2741 case FIRST : {
2742 // second nonce collect
2743 ar_nr_nonces[index].nonce2 = nonce;
2744 ar_nr_nonces[index].nr2 = nr;
2745 ar_nr_nonces[index].ar2 = ar;
2746 ar_nr_nonces[index].state = SECOND;
2747
2748 // send to client
2749 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, 0, 0, &ar_nr_nonces[index], sizeof(nonces_t));
2750
2751 ar_nr_nonces[index].state = EMPTY;
2752 ar_nr_nonces[index].sector = 0;
2753 ar_nr_nonces[index].keytype = 0;
2754 break;
2755 }
2756 default: break;
2757 }
2758 }
b6e05350 2759
d32691f1 2760 crypto1_word(pcs, nr , 1);
2761 uint32_t cardRr = ar ^ crypto1_word(pcs, 0, 0);
b6e05350 2762
d32691f1 2763 //test if auth OK
0194ce8f 2764 if (cardRr != prng_successor(nonce, 64)){
c3c241f3 2765
d24026ad 2766 if (MF_DBGLEVEL >= 3) {
d32691f1 2767 Dbprintf("AUTH FAILED for sector %d with key %c. [nr=%08x cardRr=%08x] [nt=%08x succ=%08x]"
2768 , cardAUTHSC
2769 , (cardAUTHKEY == 0) ? 'A' : 'B'
2770 , nr
2771 , cardRr
2772 , nonce // nt
2773 , prng_successor(nonce, 64)
d32691f1 2774 );
d24026ad 2775 }
d32691f1 2776 // Shouldn't we respond anything here?
2777 // Right now, we don't nack or anything, which causes the
2778 // reader to do a WUPA after a while. /Martin
2779 // -- which is the correct response. /piwi
0194ce8f 2780 cardSTATE_TO_IDLE();
2781 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2782 break;
2783 }
0194ce8f 2784
d2f487af 2785 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
d2f487af 2786 num_to_bytes(ans, 4, rAUTH_AT);
d2f487af 2787 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2788 LED_C_ON();
bc939371 2789
d32691f1 2790 if (MF_DBGLEVEL >= 1) {
495d7f13 2791 Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2792 cardAUTHSC,
2793 cardAUTHKEY == 0 ? 'A' : 'B',
2794 GetTickCount() - authTimer
2795 );
2796 }
0014cb46 2797 cardSTATE = MFEMUL_WORK;
0194ce8f 2798 break;
50193c1e 2799 }
7bc95e2e 2800 case MFEMUL_WORK:{
2801 if (len == 0) {
6a1f2d82 2802 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2803 break;
0194ce8f 2804 }
d2f487af 2805 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2806
495d7f13 2807 if(encrypted_data)
51969283 2808 mf_crypto1_decrypt(pcs, receivedCmd, len);
7bc95e2e 2809
0194ce8f 2810 if (len == 4 && (receivedCmd[0] == MIFARE_AUTH_KEYA ||
2811 receivedCmd[0] == MIFARE_AUTH_KEYB) ) {
2812
d2f487af 2813 authTimer = GetTickCount();
d32691f1 2814 cardAUTHSC = receivedCmd[1] / 4; // received block -> sector
2815 cardAUTHKEY = receivedCmd[0] & 0x1;
0194ce8f 2816 crypto1_destroy(pcs);
d32691f1 2817
2818 // load key into crypto
d2f487af 2819 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2820
d24026ad 2821 if (!encrypted_data) {
0194ce8f 2822 // first authentication
d32691f1 2823 // Update crypto state init (UID ^ NONCE)
2824 crypto1_word(pcs, cuid ^ nonce, 0);
2825 num_to_bytes(nonce, 4, rAUTH_AT);
0194ce8f 2826 } else {
2827 // nested authentication
7bc95e2e 2828 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2829 num_to_bytes(ans, 4, rAUTH_AT);
0194ce8f 2830
d32691f1 2831 if (MF_DBGLEVEL >= 3) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %c", receivedCmd[1], receivedCmd[1], cardAUTHKEY == 0 ? 'A' : 'B');
d2f487af 2832 }
0c8d25eb 2833
d2f487af 2834 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
d2f487af 2835 cardSTATE = MFEMUL_AUTH1;
2836 break;
51969283 2837 }
7bc95e2e 2838
8f51ddb0
M
2839 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2840 // BUT... ACK --> NACK
2841 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2842 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2843 break;
2844 }
2845
2846 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2847 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2848 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2849 break;
0a39986e
M
2850 }
2851
7bc95e2e 2852 if(len != 4) {
6a1f2d82 2853 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2854 break;
2855 }
d2f487af 2856
0194ce8f 2857 if ( receivedCmd[0] == ISO14443A_CMD_READBLOCK ||
2858 receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK ||
2859 receivedCmd[0] == MIFARE_CMD_INC ||
2860 receivedCmd[0] == MIFARE_CMD_DEC ||
2861 receivedCmd[0] == MIFARE_CMD_RESTORE ||
2862 receivedCmd[0] == MIFARE_CMD_TRANSFER ) {
2863
7bc95e2e 2864 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2865 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2866 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2867 break;
2868 }
2869
7bc95e2e 2870 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2871 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
c3c241f3 2872 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2873 break;
2874 }
d2f487af 2875 }
2876 // read block
0194ce8f 2877 if (receivedCmd[0] == ISO14443A_CMD_READBLOCK) {
2878 if (MF_DBGLEVEL >= 4) Dbprintf("Reader reading block %d (0x%02x)", receivedCmd[1], receivedCmd[1]);
495d7f13 2879
8f51ddb0
M
2880 emlGetMem(response, receivedCmd[1], 1);
2881 AppendCrc14443a(response, 16);
6a1f2d82 2882 mf_crypto1_encrypt(pcs, response, 18, response_par);
2883 EmSendCmdPar(response, 18, response_par);
d2f487af 2884 numReads++;
12d708fe 2885 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
d2f487af 2886 Dbprintf("%d reads done, exiting", numReads);
2887 finished = true;
2888 }
0a39986e
M
2889 break;
2890 }
0a39986e 2891 // write block
0194ce8f 2892 if (receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK) {
2893 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)", receivedCmd[1], receivedCmd[1]);
8f51ddb0 2894 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2895 cardSTATE = MFEMUL_WRITEBL2;
2896 cardWRBL = receivedCmd[1];
0a39986e 2897 break;
7bc95e2e 2898 }
0014cb46 2899 // increment, decrement, restore
0194ce8f 2900 if ( receivedCmd[0] == MIFARE_CMD_INC ||
2901 receivedCmd[0] == MIFARE_CMD_DEC ||
2902 receivedCmd[0] == MIFARE_CMD_RESTORE) {
2903
2904 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2905
d2f487af 2906 if (emlCheckValBl(receivedCmd[1])) {
c3c241f3 2907 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2908 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2909 break;
2910 }
2911 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0194ce8f 2912 if (receivedCmd[0] == MIFARE_CMD_INC) cardSTATE = MFEMUL_INTREG_INC;
2913 if (receivedCmd[0] == MIFARE_CMD_DEC) cardSTATE = MFEMUL_INTREG_DEC;
2914 if (receivedCmd[0] == MIFARE_CMD_RESTORE) cardSTATE = MFEMUL_INTREG_REST;
0014cb46 2915 cardWRBL = receivedCmd[1];
0014cb46
M
2916 break;
2917 }
0014cb46 2918 // transfer
0194ce8f 2919 if (receivedCmd[0] == MIFARE_CMD_TRANSFER) {
2920 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)", receivedCmd[0], receivedCmd[1], receivedCmd[1]);
0014cb46
M
2921 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2922 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2923 else
2924 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2925 break;
2926 }
9ca155ba 2927 // halt
0194ce8f 2928 if (receivedCmd[0] == ISO14443A_CMD_HALT && receivedCmd[1] == 0x00) {
9ca155ba 2929 LED_B_OFF();
0a39986e 2930 LED_C_OFF();
0014cb46
M
2931 cardSTATE = MFEMUL_HALTED;
2932 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2933 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2934 break;
9ca155ba 2935 }
d2f487af 2936 // RATS
0194ce8f 2937 if (receivedCmd[0] == ISO14443A_CMD_RATS) {
8f51ddb0
M
2938 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2939 break;
2940 }
d2f487af 2941 // command not allowed
2942 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2943 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2944 break;
8f51ddb0
M
2945 }
2946 case MFEMUL_WRITEBL2:{
495d7f13 2947 if (len == 18) {
8f51ddb0
M
2948 mf_crypto1_decrypt(pcs, receivedCmd, len);
2949 emlSetMem(receivedCmd, cardWRBL, 1);
2950 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2951 cardSTATE = MFEMUL_WORK;
51969283 2952 } else {
0014cb46 2953 cardSTATE_TO_IDLE();
6a1f2d82 2954 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2955 }
8f51ddb0 2956 break;
50193c1e 2957 }
0014cb46
M
2958 case MFEMUL_INTREG_INC:{
2959 mf_crypto1_decrypt(pcs, receivedCmd, len);
2960 memcpy(&ans, receivedCmd, 4);
2961 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2962 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2963 cardSTATE_TO_IDLE();
2964 break;
7bc95e2e 2965 }
6a1f2d82 2966 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2967 cardINTREG = cardINTREG + ans;
2968 cardSTATE = MFEMUL_WORK;
2969 break;
2970 }
2971 case MFEMUL_INTREG_DEC:{
2972 mf_crypto1_decrypt(pcs, receivedCmd, len);
2973 memcpy(&ans, receivedCmd, 4);
2974 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2975 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2976 cardSTATE_TO_IDLE();
2977 break;
2978 }
6a1f2d82 2979 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2980 cardINTREG = cardINTREG - ans;
2981 cardSTATE = MFEMUL_WORK;
2982 break;
2983 }
2984 case MFEMUL_INTREG_REST:{
2985 mf_crypto1_decrypt(pcs, receivedCmd, len);
2986 memcpy(&ans, receivedCmd, 4);
2987 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2988 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2989 cardSTATE_TO_IDLE();
2990 break;
2991 }
6a1f2d82 2992 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2993 cardSTATE = MFEMUL_WORK;
2994 break;
2995 }
50193c1e 2996 }
50193c1e
M
2997 }
2998
bf5d7992 2999 if (MF_DBGLEVEL >= 1)
3000 Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
5ee53a0e 3001
e99acd00 3002 cmd_send(CMD_ACK,1,0,0,0,0); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
91c7a7cc 3003 LEDsoff();
5ee53a0e 3004 set_tracing(FALSE);
15c4dc5a 3005}
b62a5a84 3006
d2f487af 3007
b62a5a84
M
3008//-----------------------------------------------------------------------------
3009// MIFARE sniffer.
3010//
0194ce8f 3011// if no activity for 2sec, it sends the collected data to the client.
b62a5a84 3012//-----------------------------------------------------------------------------
bc939371 3013// "hf mf sniff"
5cd9ec01 3014void RAMFUNC SniffMifare(uint8_t param) {
bc939371 3015
b62a5a84 3016 LEDsoff();
810f5379 3017
aaa1a9a2 3018 // free eventually allocated BigBuf memory
3019 BigBuf_free(); BigBuf_Clear_ext(false);
3000dc4e
MHS
3020 clear_trace();
3021 set_tracing(TRUE);
b62a5a84 3022
b62a5a84 3023 // The command (reader -> tag) that we're receiving.
810f5379 3024 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
495d7f13 3025 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
810f5379 3026
b62a5a84 3027 // The response (tag -> reader) that we're receiving.
495d7f13 3028 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE] = {0x00};
3029 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE] = {0x00};
b62a5a84 3030
99cf19d9 3031 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
3032
f71f4deb 3033 // allocate the DMA buffer, used to stream samples from the FPGA
0194ce8f 3034 // [iceman] is this sniffed data unsigned?
f71f4deb 3035 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 3036 uint8_t *data = dmaBuf;
3037 uint8_t previous_data = 0;
5cd9ec01
M
3038 int maxDataLen = 0;
3039 int dataLen = 0;
7bc95e2e 3040 bool ReaderIsActive = FALSE;
3041 bool TagIsActive = FALSE;
3042
b62a5a84 3043 // Set up the demodulator for tag -> reader responses.
6a1f2d82 3044 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
3045
3046 // Set up the demodulator for the reader -> tag commands
6a1f2d82 3047 UartInit(receivedCmd, receivedCmdPar);
b62a5a84 3048
57850d9d 3049 // Setup and start DMA.
3050 // set transfer address and number of bytes. Start transfer.
3051 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
3052 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
3053 return;
3054 }
b62a5a84 3055
b62a5a84 3056 LED_D_OFF();
0194ce8f 3057
39864b0b 3058 MfSniffInit();
b62a5a84 3059
b62a5a84 3060 // And now we loop, receiving samples.
0194ce8f 3061 for(uint32_t sniffCounter = 0;; ) {
91c7a7cc 3062
3063 LED_A_ON();
3064 WDT_HIT();
7bc95e2e 3065
5cd9ec01
M
3066 if(BUTTON_PRESS()) {
3067 DbpString("cancelled by button");
7bc95e2e 3068 break;
5cd9ec01 3069 }
91c7a7cc 3070
7bc95e2e 3071 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3072 // check if a transaction is completed (timeout after 2000ms).
3073 // if yes, stop the DMA transfer and send what we have so far to the client
3074 if (MfSniffSend(2000)) {
3075 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3076 sniffCounter = 0;
3077 data = dmaBuf;
3078 maxDataLen = 0;
3079 ReaderIsActive = FALSE;
3080 TagIsActive = FALSE;
57850d9d 3081 // Setup and start DMA. set transfer address and number of bytes. Start transfer.
3082 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
3083 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
3084 return;
3085 }
39864b0b 3086 }
39864b0b 3087 }
7bc95e2e 3088
3089 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3090 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
495d7f13 3091
3092 if (readBufDataP <= dmaBufDataP) // we are processing the same block of data which is currently being transferred
7bc95e2e 3093 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
495d7f13 3094 else
7bc95e2e 3095 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
495d7f13 3096
5cd9ec01 3097 // test for length of buffer
7bc95e2e 3098 if(dataLen > maxDataLen) { // we are more behind than ever...
3099 maxDataLen = dataLen;
f71f4deb 3100 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 3101 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 3102 break;
b62a5a84
M
3103 }
3104 }
5cd9ec01 3105 if(dataLen < 1) continue;
b62a5a84 3106
7bc95e2e 3107 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
3108 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3109 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3110 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
91c7a7cc 3111 Dbprintf("RxEmpty ERROR, data length:%d", dataLen); // temporary
5cd9ec01
M
3112 }
3113 // secondary buffer sets as primary, secondary buffer was stopped
3114 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3115 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
3116 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3117 }
5cd9ec01
M
3118
3119 LED_A_OFF();
b62a5a84 3120
7bc95e2e 3121 if (sniffCounter & 0x01) {
b62a5a84 3122
495d7f13 3123 // no need to try decoding tag data if the reader is sending
3124 if(!TagIsActive) {
7bc95e2e 3125 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3126 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3127 LED_C_INV();
495d7f13 3128
6a1f2d82 3129 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 3130
f8ada309 3131 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3132 DemodReset();
3133 }
3134 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3135 }
3136
495d7f13 3137 // no need to try decoding tag data if the reader is sending
3138 if(!ReaderIsActive) {
7bc95e2e 3139 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3140 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3141 LED_C_INV();
b62a5a84 3142
6a1f2d82 3143 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 3144
7bc95e2e 3145 DemodReset();
0ec548dc 3146 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3147 }
3148 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3149 }
b62a5a84
M
3150 }
3151
7bc95e2e 3152 previous_data = *data;
3153 sniffCounter++;
5cd9ec01 3154 data++;
495d7f13 3155
3156 if(data == dmaBuf + DMA_BUFFER_SIZE)
5cd9ec01 3157 data = dmaBuf;
7bc95e2e 3158
b62a5a84 3159 } // main cycle
bc939371 3160
3161 if (MF_DBGLEVEL >= 1) Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3162
55acbb2a 3163 FpgaDisableSscDma();
39864b0b 3164 MfSniffEnd();
91c7a7cc 3165 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3166 LEDsoff();
5ee53a0e 3167 set_tracing(FALSE);
3803d529 3168}
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