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FIX: antenna was not turn off after "hf 14b write" command. The method is using...
[proxmark3-svn] / armsrc / iso14443a.c
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15c4dc5a 1//-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
f38a1528 13#include "../include/proxmark3.h"
15c4dc5a 14#include "apps.h"
f7e3ed82 15#include "util.h"
9ab7a6c7 16#include "string.h"
f38a1528 17#include "../common/cmd.h"
18#include "../common/iso14443crc.h"
534983d7 19#include "iso14443a.h"
20f9a2a1
M
20#include "crapto1.h"
21#include "mifareutil.h"
15c4dc5a 22
534983d7 23static uint32_t iso14a_timeout;
d19929cb 24uint8_t *trace = (uint8_t *) BigBuf+TRACE_OFFSET;
1e262141 25int rsamples = 0;
7bc95e2e 26int traceLen = 0;
1e262141 27int tracing = TRUE;
28uint8_t trigger = 0;
b0127e65 29// the block number for the ISO14443-4 PCB
30static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 31
7bc95e2e 32//
33// ISO14443 timing:
34//
35// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
36#define REQUEST_GUARD_TIME (7000/16 + 1)
37// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
38#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
39// bool LastCommandWasRequest = FALSE;
40
41//
42// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
43//
d714d3ef 44// When the PM acts as reader and is receiving tag data, it takes
45// 3 ticks delay in the AD converter
46// 16 ticks until the modulation detector completes and sets curbit
47// 8 ticks until bit_to_arm is assigned from curbit
48// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 49// 4*16 ticks until we measure the time
50// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 51#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 52
53// When the PM acts as a reader and is sending, it takes
54// 4*16 ticks until we can write data to the sending hold register
55// 8*16 ticks until the SHR is transferred to the Sending Shift Register
56// 8 ticks until the first transfer starts
57// 8 ticks later the FPGA samples the data
58// 1 tick to assign mod_sig_coil
59#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
60
61// When the PM acts as tag and is receiving it takes
d714d3ef 62// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 63// 3 ticks for the A/D conversion,
64// 8 ticks on average until the start of the SSC transfer,
65// 8 ticks until the SSC samples the first data
66// 7*16 ticks to complete the transfer from FPGA to ARM
67// 8 ticks until the next ssp_clk rising edge
d714d3ef 68// 4*16 ticks until we measure the time
7bc95e2e 69// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 70#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 71
72// The FPGA will report its internal sending delay in
73uint16_t FpgaSendQueueDelay;
74// the 5 first bits are the number of bits buffered in mod_sig_buf
75// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
76#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
77
78// When the PM acts as tag and is sending, it takes
d714d3ef 79// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 80// 8*16 ticks until the SHR is transferred to the Sending Shift Register
81// 8 ticks until the first transfer starts
82// 8 ticks later the FPGA samples the data
83// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
84// + 1 tick to assign mod_sig_coil
d714d3ef 85#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 86
87// When the PM acts as sniffer and is receiving tag data, it takes
88// 3 ticks A/D conversion
d714d3ef 89// 14 ticks to complete the modulation detection
90// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 91// + the delays in transferring data - which is the same for
92// sniffing reader and tag data and therefore not relevant
d714d3ef 93#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 94
d714d3ef 95// When the PM acts as sniffer and is receiving reader data, it takes
96// 2 ticks delay in analogue RF receiver (for the falling edge of the
97// start bit, which marks the start of the communication)
7bc95e2e 98// 3 ticks A/D conversion
d714d3ef 99// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 100// + the delays in transferring data - which is the same for
101// sniffing reader and tag data and therefore not relevant
d714d3ef 102#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 103
104//variables used for timing purposes:
105//these are in ssp_clk cycles:
a501c82b 106static uint32_t NextTransferTime;
107static uint32_t LastTimeProxToAirStart;
108static uint32_t LastProxToAirDuration;
7bc95e2e 109
110
111
8f51ddb0 112// CARD TO READER - manchester
72934aa3 113// Sequence D: 11110000 modulation with subcarrier during first half
114// Sequence E: 00001111 modulation with subcarrier during second half
115// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 116// READER TO CARD - miller
72934aa3 117// Sequence X: 00001100 drop after half a period
118// Sequence Y: 00000000 no drop
119// Sequence Z: 11000000 drop at start
120#define SEC_D 0xf0
121#define SEC_E 0x0f
122#define SEC_F 0x00
123#define SEC_X 0x0c
124#define SEC_Y 0x00
125#define SEC_Z 0xc0
15c4dc5a 126
1e262141 127const uint8_t OddByteParity[256] = {
15c4dc5a 128 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
129 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
130 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
131 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
132 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
133 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
134 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
135 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
136 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
137 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
138 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
139 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
140 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
141 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
142 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
143 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
144};
1e262141 145
902cb3c0 146void iso14a_set_trigger(bool enable) {
534983d7 147 trigger = enable;
148}
149
902cb3c0 150void iso14a_clear_trace() {
7bc95e2e 151 memset(trace, 0x44, TRACE_SIZE);
8556b852
M
152 traceLen = 0;
153}
d19929cb 154
902cb3c0 155void iso14a_set_tracing(bool enable) {
8556b852
M
156 tracing = enable;
157}
d19929cb 158
b0127e65 159void iso14a_set_timeout(uint32_t timeout) {
160 iso14a_timeout = timeout;
161}
8556b852 162
15c4dc5a 163//-----------------------------------------------------------------------------
164// Generate the parity value for a byte sequence
e30c654b 165//
15c4dc5a 166//-----------------------------------------------------------------------------
20f9a2a1
M
167byte_t oddparity (const byte_t bt)
168{
5f6d6c90 169 return OddByteParity[bt];
20f9a2a1
M
170}
171
a501c82b 172void GetParity(const uint8_t * pbtCmd, uint16_t iLen, uint8_t *par)
15c4dc5a 173{
a501c82b 174 uint16_t paritybit_cnt = 0;
175 uint16_t paritybyte_cnt = 0;
176 uint8_t parityBits = 0;
177
178 for (uint16_t i = 0; i < iLen; i++) {
179 // Generate the parity bits
180 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
181 if (paritybit_cnt == 7) {
182 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
183 parityBits = 0; // and advance to next Parity Byte
184 paritybyte_cnt++;
185 paritybit_cnt = 0;
186 } else {
187 paritybit_cnt++;
188 }
5f6d6c90 189 }
a501c82b 190
191 // save remaining parity bits
192 par[paritybyte_cnt] = parityBits;
193
15c4dc5a 194}
195
534983d7 196void AppendCrc14443a(uint8_t* data, int len)
15c4dc5a 197{
5f6d6c90 198 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 199}
200
1e262141 201// The function LogTrace() is also used by the iClass implementation in iClass.c
a501c82b 202bool RAMFUNC LogTrace(const uint8_t *btBytes, uint16_t iLen, uint32_t timestamp_start, uint32_t timestamp_end, uint8_t *parity, bool readerToTag)
15c4dc5a 203{
fdcd43eb 204 if (!tracing) return FALSE;
a501c82b 205
206 uint16_t num_paritybytes = (iLen-1)/8 + 1; // number of valid paritybytes in *parity
207 uint16_t duration = timestamp_end - timestamp_start;
208
7bc95e2e 209 // Return when trace is full
a501c82b 210 if (traceLen + sizeof(iLen) + sizeof(timestamp_start) + sizeof(duration) + num_paritybytes + iLen >= TRACE_SIZE) {
7bc95e2e 211 tracing = FALSE; // don't trace any more
212 return FALSE;
213 }
214
a501c82b 215 // Traceformat:
216 // 32 bits timestamp (little endian)
217 // 16 bits duration (little endian)
218 // 16 bits data length (little endian, Highest Bit used as readerToTag flag)
219 // y Bytes data
220 // x Bytes parity (one byte per 8 bytes data)
221
222 // timestamp (start)
223 trace[traceLen++] = ((timestamp_start >> 0) & 0xff);
224 trace[traceLen++] = ((timestamp_start >> 8) & 0xff);
225 trace[traceLen++] = ((timestamp_start >> 16) & 0xff);
226 trace[traceLen++] = ((timestamp_start >> 24) & 0xff);
227
228 // duration
229 trace[traceLen++] = ((duration >> 0) & 0xff);
230 trace[traceLen++] = ((duration >> 8) & 0xff);
231
232 // data length
233 trace[traceLen++] = ((iLen >> 0) & 0xff);
234 trace[traceLen++] = ((iLen >> 8) & 0xff);
235
236 // readerToTag flag
17cba269 237 if (!readerToTag) {
7bc95e2e 238 trace[traceLen - 1] |= 0x80;
a501c82b 239 }
240
241 // data bytes
7bc95e2e 242 if (btBytes != NULL && iLen != 0) {
243 memcpy(trace + traceLen, btBytes, iLen);
244 }
a501c82b 245 traceLen += iLen;
246
247 // parity bytes
248 if (parity != NULL && iLen != 0) {
249 memcpy(trace + traceLen, parity, num_paritybytes);
250 }
251 traceLen += num_paritybytes;
252
7bc95e2e 253 return TRUE;
15c4dc5a 254}
255
7bc95e2e 256//=============================================================================
257// ISO 14443 Type A - Miller decoder
258//=============================================================================
259// Basics:
260// This decoder is used when the PM3 acts as a tag.
261// The reader will generate "pauses" by temporarily switching of the field.
262// At the PM3 antenna we will therefore measure a modulated antenna voltage.
263// The FPGA does a comparison with a threshold and would deliver e.g.:
264// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
265// The Miller decoder needs to identify the following sequences:
266// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
267// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
268// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
269// Note 1: the bitstream may start at any time. We therefore need to sync.
270// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 271//-----------------------------------------------------------------------------
b62a5a84 272static tUart Uart;
15c4dc5a 273
d7aa3739 274// Lookup-Table to decide if 4 raw bits are a modulation.
275// We accept two or three consecutive "0" in any position with the rest "1"
276const bool Mod_Miller_LUT[] = {
277 TRUE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE,
278 TRUE, TRUE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE
279};
280#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x00F0) >> 4])
281#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x000F)])
282
7bc95e2e 283void UartReset()
15c4dc5a 284{
7bc95e2e 285 Uart.state = STATE_UNSYNCD;
286 Uart.bitCount = 0;
287 Uart.len = 0; // number of decoded data bytes
a501c82b 288 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 289 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
a501c82b 290 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 291 Uart.twoBits = 0x0000; // buffer for 2 Bits
292 Uart.highCnt = 0;
293 Uart.startTime = 0;
294 Uart.endTime = 0;
295}
15c4dc5a 296
a501c82b 297void UartInit(uint8_t *data, uint8_t *parity)
298{
299 Uart.output = data;
300 Uart.parity = parity;
301 UartReset();
302}
d714d3ef 303
7bc95e2e 304// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
305static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
306{
15c4dc5a 307
7bc95e2e 308 Uart.twoBits = (Uart.twoBits << 8) | bit;
309
a501c82b 310 if (Uart.state == STATE_UNSYNCD) { // not yet synced
311
7bc95e2e 312 if (Uart.highCnt < 7) { // wait for a stable unmodulated signal
f5ed4d12 313 if (Uart.twoBits == 0xffff) {
7bc95e2e 314 Uart.highCnt++;
f5ed4d12 315 } else {
7bc95e2e 316 Uart.highCnt = 0;
f5ed4d12 317 }
a501c82b 318 } else {
7bc95e2e 319 Uart.syncBit = 0xFFFF; // not set
320 // look for 00xx1111 (the start bit)
321 if ((Uart.twoBits & 0x6780) == 0x0780) Uart.syncBit = 7;
322 else if ((Uart.twoBits & 0x33C0) == 0x03C0) Uart.syncBit = 6;
323 else if ((Uart.twoBits & 0x19E0) == 0x01E0) Uart.syncBit = 5;
324 else if ((Uart.twoBits & 0x0CF0) == 0x00F0) Uart.syncBit = 4;
325 else if ((Uart.twoBits & 0x0678) == 0x0078) Uart.syncBit = 3;
326 else if ((Uart.twoBits & 0x033C) == 0x003C) Uart.syncBit = 2;
327 else if ((Uart.twoBits & 0x019E) == 0x001E) Uart.syncBit = 1;
328 else if ((Uart.twoBits & 0x00CF) == 0x000F) Uart.syncBit = 0;
329 if (Uart.syncBit != 0xFFFF) {
330 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
331 Uart.startTime -= Uart.syncBit;
d7aa3739 332 Uart.endTime = Uart.startTime;
7bc95e2e 333 Uart.state = STATE_START_OF_COMMUNICATION;
15c4dc5a 334 }
7bc95e2e 335 }
15c4dc5a 336
7bc95e2e 337 } else {
15c4dc5a 338
d7aa3739 339 if (IsMillerModulationNibble1(Uart.twoBits >> Uart.syncBit)) {
340 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation in both halves - error
341 UartReset();
342 Uart.highCnt = 6;
343 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 344 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
345 UartReset();
346 Uart.highCnt = 6;
347 } else {
348 Uart.bitCount++;
349 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
350 Uart.state = STATE_MILLER_Z;
351 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
352 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
353 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
354 Uart.parityBits <<= 1; // make room for the parity bit
355 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
356 Uart.bitCount = 0;
357 Uart.shiftReg = 0;
a501c82b 358 if((Uart.len & 0x0007) == 0) { // every 8 data bytes
359 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
360 Uart.parityBits = 0;
361 }
15c4dc5a 362 }
7bc95e2e 363 }
d7aa3739 364 }
365 } else {
366 if (IsMillerModulationNibble2(Uart.twoBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 367 Uart.bitCount++;
368 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
369 Uart.state = STATE_MILLER_X;
370 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
371 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
372 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
373 Uart.parityBits <<= 1; // make room for the new parity bit
374 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
375 Uart.bitCount = 0;
376 Uart.shiftReg = 0;
a501c82b 377 if ((Uart.len & 0x0007) == 0) { // every 8 data bytes
378 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
379 Uart.parityBits = 0;
380 }
7bc95e2e 381 }
d7aa3739 382 } else { // no modulation in both halves - Sequence Y
7bc95e2e 383 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 384 Uart.state = STATE_UNSYNCD;
a501c82b 385 Uart.bitCount--; // last "0" was part of EOC sequence
386 Uart.shiftReg <<= 1; // drop it
387 if(Uart.bitCount > 0) { // if we decoded some bits
388 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
389 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
390 Uart.parityBits <<= 1; // add a (void) parity bit
391 Uart.parityBits <<= (8 - (Uart.len & 0x0007)); // left align parity bits
392 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
15c4dc5a 393 return TRUE;
a501c82b 394 } else if (Uart.len & 0x0007) { // there are some parity bits to store
395 Uart.parityBits <<= (8 - (Uart.len & 0x0007)); // left align remaining parity bits
396 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
a501c82b 397 }
1b492a97 398 if ( Uart.len) {
399 return TRUE; // we are finished with decoding the raw data sequence
400 } else {
401 UartReset(); // Nothing receiver - start over
402 }
15c4dc5a 403 }
7bc95e2e 404 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
405 UartReset();
406 Uart.highCnt = 6;
407 } else { // a logic "0"
408 Uart.bitCount++;
409 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
410 Uart.state = STATE_MILLER_Y;
411 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
412 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
413 Uart.parityBits <<= 1; // make room for the parity bit
414 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
415 Uart.bitCount = 0;
416 Uart.shiftReg = 0;
a501c82b 417 if ((Uart.len & 0x0007) == 0) { // every 8 data bytes
418 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
419 Uart.parityBits = 0;
420 }
15c4dc5a 421 }
422 }
d7aa3739 423 }
15c4dc5a 424 }
7bc95e2e 425
a501c82b 426 }
15c4dc5a 427
7bc95e2e 428 return FALSE; // not finished yet, need more data
15c4dc5a 429}
430
7bc95e2e 431
432
15c4dc5a 433//=============================================================================
e691fc45 434// ISO 14443 Type A - Manchester decoder
15c4dc5a 435//=============================================================================
e691fc45 436// Basics:
7bc95e2e 437// This decoder is used when the PM3 acts as a reader.
e691fc45 438// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
439// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
440// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
441// The Manchester decoder needs to identify the following sequences:
442// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
443// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
444// 8 ticks unmodulated: Sequence F = end of communication
445// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 446// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 447// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 448static tDemod Demod;
15c4dc5a 449
d7aa3739 450// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 451// We accept three or four "1" in any position
7bc95e2e 452const bool Mod_Manchester_LUT[] = {
d7aa3739 453 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 454 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 455};
456
457#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
458#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 459
2f2d9fc5 460
7bc95e2e 461void DemodReset()
e691fc45 462{
7bc95e2e 463 Demod.state = DEMOD_UNSYNCD;
464 Demod.len = 0; // number of decoded data bytes
a501c82b 465 Demod.parityLen = 0;
7bc95e2e 466 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
467 Demod.parityBits = 0; //
468 Demod.collisionPos = 0; // Position of collision bit
469 Demod.twoBits = 0xffff; // buffer for 2 Bits
470 Demod.highCnt = 0;
471 Demod.startTime = 0;
472 Demod.endTime = 0;
e691fc45 473}
15c4dc5a 474
a501c82b 475void DemodInit(uint8_t *data, uint8_t *parity)
476{
477 Demod.output = data;
478 Demod.parity = parity;
479 DemodReset();
480}
481
7bc95e2e 482// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
483static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
e691fc45 484{
7bc95e2e 485
486 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 487
7bc95e2e 488 if (Demod.state == DEMOD_UNSYNCD) {
489
490 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
491 if (Demod.twoBits == 0x0000) {
492 Demod.highCnt++;
493 } else {
494 Demod.highCnt = 0;
495 }
496 } else {
497 Demod.syncBit = 0xFFFF; // not set
498 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
499 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
500 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
501 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
502 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
503 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
504 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
505 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 506 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 507 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
508 Demod.startTime -= Demod.syncBit;
509 Demod.bitCount = offset; // number of decoded data bits
e691fc45 510 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 511 }
7bc95e2e 512 }
15c4dc5a 513
7bc95e2e 514 } else {
15c4dc5a 515
7bc95e2e 516 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
517 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 518 if (!Demod.collisionPos) {
519 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
520 }
521 } // modulation in first half only - Sequence D = 1
7bc95e2e 522 Demod.bitCount++;
523 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
524 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 525 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 526 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 527 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
528 Demod.bitCount = 0;
529 Demod.shiftReg = 0;
a501c82b 530 if((Demod.len & 0x0007) == 0) { // every 8 data bytes
531 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
532 Demod.parityBits = 0;
533 }
15c4dc5a 534 }
7bc95e2e 535 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
536 } else { // no modulation in first half
537 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 538 Demod.bitCount++;
7bc95e2e 539 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 540 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 541 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 542 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 543 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
544 Demod.bitCount = 0;
545 Demod.shiftReg = 0;
a501c82b 546 if ((Demod.len & 0x0007) == 0) { // every 8 data bytes
547 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
548 Demod.parityBits = 0;
549 }
15c4dc5a 550 }
7bc95e2e 551 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 552 } else { // no modulation in both halves - End of communication
a501c82b 553 if(Demod.bitCount > 0) { // there are some remaining data bits
554 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
555 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
556 Demod.parityBits <<= 1; // add a (void) parity bit
557 Demod.parityBits <<= (8 - (Demod.len & 0x0007)); // left align remaining parity bits
558 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
559 return TRUE;
560 } else if (Demod.len & 0x0007) { // there are some parity bits to store
561 Demod.parityBits <<= (8 - (Demod.len & 0x0007)); // left align remaining parity bits
562 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
1b492a97 563 }
564 if (Demod.len) {
a501c82b 565 return TRUE; // we are finished with decoding the raw data sequence
d7aa3739 566 } else { // nothing received. Start over
567 DemodReset();
e691fc45 568 }
15c4dc5a 569 }
7bc95e2e 570 }
e691fc45 571
572 }
15c4dc5a 573
e691fc45 574 return FALSE; // not finished yet, need more data
15c4dc5a 575}
576
577//=============================================================================
578// Finally, a `sniffer' for ISO 14443 Type A
579// Both sides of communication!
580//=============================================================================
581
582//-----------------------------------------------------------------------------
583// Record the sequence of commands sent by the reader to the tag, with
584// triggering so that we start recording at the point that the tag is moved
585// near the reader.
586//-----------------------------------------------------------------------------
5cd9ec01
M
587void RAMFUNC SnoopIso14443a(uint8_t param) {
588 // param:
589 // bit 0 - trigger from first card answer
590 // bit 1 - trigger from first reader 7-bit request
591
592 LEDsoff();
593 // init trace buffer
5f6d6c90 594 iso14a_clear_trace();
991f13f2 595 iso14a_set_tracing(TRUE);
5cd9ec01
M
596
597 // We won't start recording the frames that we acquire until we trigger;
598 // a good trigger condition to get started is probably when we see a
599 // response from the tag.
600 // triggered == FALSE -- to wait first for card
7bc95e2e 601 bool triggered = !(param & 0x03);
602
5cd9ec01 603 // The command (reader -> tag) that we're receiving.
15c4dc5a 604 // The length of a received command will in most cases be no more than 18 bytes.
605 // So 32 should be enough!
a501c82b 606 uint8_t *receivedCmd = ((uint8_t *)BigBuf) + RECV_CMD_OFFSET;
607 uint8_t *receivedCmdPar = ((uint8_t *)BigBuf) + RECV_CMD_PAR_OFFSET;
608
5cd9ec01 609 // The response (tag -> reader) that we're receiving.
a501c82b 610 uint8_t *receivedResponse = ((uint8_t *)BigBuf) + RECV_RESP_OFFSET;
611 uint8_t *receivedResponsePar = ((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET;
612
5cd9ec01
M
613 // As we receive stuff, we copy it from receivedCmd or receivedResponse
614 // into trace, along with its length and other annotations.
615 //uint8_t *trace = (uint8_t *)BigBuf;
616
617 // The DMA buffer, used to stream samples from the FPGA
7bc95e2e 618 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
619 uint8_t *data = dmaBuf;
620 uint8_t previous_data = 0;
5cd9ec01
M
621 int maxDataLen = 0;
622 int dataLen = 0;
7bc95e2e 623 bool TagIsActive = FALSE;
624 bool ReaderIsActive = FALSE;
625
626 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
15c4dc5a 627
5cd9ec01 628 // Set up the demodulator for tag -> reader responses.
a501c82b 629 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 630
5cd9ec01 631 // Set up the demodulator for the reader -> tag commands
a501c82b 632 UartInit(receivedCmd, receivedCmdPar);
15c4dc5a 633
7bc95e2e 634 // Setup and start DMA.
5cd9ec01 635 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 636
5cd9ec01 637 // And now we loop, receiving samples.
7bc95e2e 638 for(uint32_t rsamples = 0; TRUE; ) {
639
5cd9ec01
M
640 if(BUTTON_PRESS()) {
641 DbpString("cancelled by button");
7bc95e2e 642 break;
5cd9ec01 643 }
15c4dc5a 644
5cd9ec01
M
645 LED_A_ON();
646 WDT_HIT();
15c4dc5a 647
5cd9ec01
M
648 int register readBufDataP = data - dmaBuf;
649 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
650 if (readBufDataP <= dmaBufDataP){
651 dataLen = dmaBufDataP - readBufDataP;
652 } else {
7bc95e2e 653 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
654 }
655 // test for length of buffer
656 if(dataLen > maxDataLen) {
657 maxDataLen = dataLen;
658 if(dataLen > 400) {
7bc95e2e 659 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
660 break;
5cd9ec01
M
661 }
662 }
663 if(dataLen < 1) continue;
664
665 // primary buffer was stopped( <-- we lost data!
666 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
667 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
668 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 669 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
670 }
671 // secondary buffer sets as primary, secondary buffer was stopped
672 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
673 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
674 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
675 }
676
677 LED_A_OFF();
7bc95e2e 678
679 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 680
7bc95e2e 681 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
682 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
683 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
684 LED_C_ON();
5cd9ec01 685
7bc95e2e 686 // check - if there is a short 7bit request from reader
687 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 688
7bc95e2e 689 if(triggered) {
a501c82b 690 if (!LogTrace(receivedCmd,
691 Uart.len,
692 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
693 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
694 Uart.parity,
695 TRUE)) break;
7bc95e2e 696 }
697 /* And ready to receive another command. */
698 UartReset();
699 /* And also reset the demod code, which might have been */
700 /* false-triggered by the commands from the reader. */
701 DemodReset();
702 LED_B_OFF();
703 }
704 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 705 }
3be2a5ae 706
7bc95e2e 707 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
708 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
709 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
710 LED_B_ON();
5cd9ec01 711
a501c82b 712 if (!LogTrace(receivedResponse,
713 Demod.len,
714 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
715 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
716 Demod.parity,
717 FALSE)) break;
5cd9ec01 718
7bc95e2e 719 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 720
7bc95e2e 721 // And ready to receive another response.
722 DemodReset();
723 LED_C_OFF();
724 }
725 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
726 }
5cd9ec01
M
727 }
728
7bc95e2e 729 previous_data = *data;
730 rsamples++;
5cd9ec01 731 data++;
d714d3ef 732 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
733 data = dmaBuf;
734 }
735 } // main cycle
736
737 DbpString("COMMAND FINISHED");
15c4dc5a 738
7bc95e2e 739 FpgaDisableSscDma();
740 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
741 Dbprintf("traceLen=%d, Uart.output[0]=%08x", traceLen, (uint32_t)Uart.output[0]);
5cd9ec01 742 LEDsoff();
15c4dc5a 743}
744
15c4dc5a 745//-----------------------------------------------------------------------------
746// Prepare tag messages
747//-----------------------------------------------------------------------------
a501c82b 748static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
15c4dc5a 749{
8f51ddb0 750 ToSendReset();
15c4dc5a 751
752 // Correction bit, might be removed when not needed
753 ToSendStuffBit(0);
754 ToSendStuffBit(0);
755 ToSendStuffBit(0);
756 ToSendStuffBit(0);
757 ToSendStuffBit(1); // 1
758 ToSendStuffBit(0);
759 ToSendStuffBit(0);
760 ToSendStuffBit(0);
8f51ddb0 761
15c4dc5a 762 // Send startbit
72934aa3 763 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 764 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 765
a501c82b 766 for( uint16_t i = 0; i < len; i++) {
8f51ddb0 767 uint8_t b = cmd[i];
15c4dc5a 768
769 // Data bits
a501c82b 770 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 771 if(b & 1) {
72934aa3 772 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 773 } else {
72934aa3 774 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
775 }
776 b >>= 1;
777 }
15c4dc5a 778
0014cb46 779 // Get the parity bit
a501c82b 780 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 781 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 782 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 783 } else {
72934aa3 784 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 785 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 786 }
8f51ddb0 787 }
15c4dc5a 788
8f51ddb0
M
789 // Send stopbit
790 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 791
8f51ddb0
M
792 // Convert from last byte pos to length
793 ToSendMax++;
8f51ddb0
M
794}
795
a501c82b 796static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
797{
798 uint8_t par[MAX_PARITY_SIZE];
799
800 GetParity(cmd, len, par);
801 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 802}
803
15c4dc5a 804
8f51ddb0
M
805static void Code4bitAnswerAsTag(uint8_t cmd)
806{
807 int i;
808
5f6d6c90 809 ToSendReset();
8f51ddb0
M
810
811 // Correction bit, might be removed when not needed
812 ToSendStuffBit(0);
813 ToSendStuffBit(0);
814 ToSendStuffBit(0);
815 ToSendStuffBit(0);
816 ToSendStuffBit(1); // 1
817 ToSendStuffBit(0);
818 ToSendStuffBit(0);
819 ToSendStuffBit(0);
820
821 // Send startbit
822 ToSend[++ToSendMax] = SEC_D;
823
824 uint8_t b = cmd;
825 for(i = 0; i < 4; i++) {
826 if(b & 1) {
827 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 828 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
829 } else {
830 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 831 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
832 }
833 b >>= 1;
834 }
835
836 // Send stopbit
837 ToSend[++ToSendMax] = SEC_F;
838
5f6d6c90 839 // Convert from last byte pos to length
840 ToSendMax++;
15c4dc5a 841}
842
843//-----------------------------------------------------------------------------
844// Wait for commands from reader
845// Stop when button is pressed
846// Or return TRUE when command is captured
847//-----------------------------------------------------------------------------
a501c82b 848static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
15c4dc5a 849{
850 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
851 // only, since we are receiving, not transmitting).
852 // Signal field is off with the appropriate LED
853 LED_D_OFF();
854 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
855
856 // Now run a `software UART' on the stream of incoming samples.
a501c82b 857 UartInit(received, parity);
7bc95e2e 858
859 // clear RXRDY:
860 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 861
862 for(;;) {
863 WDT_HIT();
864
865 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 866
15c4dc5a 867 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 868 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
869 if(MillerDecoding(b, 0)) {
870 *len = Uart.len;
15c4dc5a 871 return TRUE;
872 }
7bc95e2e 873 }
15c4dc5a 874 }
875}
28afbd2b 876
a501c82b 877static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
7bc95e2e 878int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
28afbd2b 879int EmSend4bit(uint8_t resp);
a501c82b 880int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
881int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
882int EmSendCmd(uint8_t *resp, uint16_t respLen);
883int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
884bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
885 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
15c4dc5a 886
ce02f6f9 887static uint8_t* free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
888
889typedef struct {
890 uint8_t* response;
891 size_t response_n;
892 uint8_t* modulation;
893 size_t modulation_n;
7bc95e2e 894 uint32_t ProxToAirDuration;
ce02f6f9 895} tag_response_info_t;
896
897void reset_free_buffer() {
898 free_buffer_pointer = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET);
899}
900
901bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 902 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 903 // This will need the following byte array for a modulation sequence
904 // 144 data bits (18 * 8)
905 // 18 parity bits
906 // 2 Start and stop
907 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
908 // 1 just for the case
909 // ----------- +
910 // 166 bytes, since every bit that needs to be send costs us a byte
911 //
912
913 // Prepare the tag modulation bits from the message
914 CodeIso14443aAsTag(response_info->response,response_info->response_n);
915
916 // Make sure we do not exceed the free buffer space
917 if (ToSendMax > max_buffer_size) {
918 Dbprintf("Out of memory, when modulating bits for tag answer:");
919 Dbhexdump(response_info->response_n,response_info->response,false);
920 return false;
921 }
922
923 // Copy the byte array, used for this modulation to the buffer position
924 memcpy(response_info->modulation,ToSend,ToSendMax);
925
7bc95e2e 926 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
ce02f6f9 927 response_info->modulation_n = ToSendMax;
7bc95e2e 928 response_info->ProxToAirDuration = LastProxToAirDuration;
ce02f6f9 929
930 return true;
931}
932
933bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
934 // Retrieve and store the current buffer index
935 response_info->modulation = free_buffer_pointer;
936
937 // Determine the maximum size we can use from our buffer
a501c82b 938 size_t max_buffer_size = (((uint8_t *)BigBuf) + FREE_BUFFER_OFFSET + FREE_BUFFER_SIZE) - free_buffer_pointer;
ce02f6f9 939
940 // Forward the prepare tag modulation function to the inner function
941 if (prepare_tag_modulation(response_info,max_buffer_size)) {
942 // Update the free buffer offset
943 free_buffer_pointer += ToSendMax;
944 return true;
945 } else {
946 return false;
947 }
948}
949
15c4dc5a 950//-----------------------------------------------------------------------------
951// Main loop of simulated tag: receive commands from reader, decide what
952// response to send, and send it.
953//-----------------------------------------------------------------------------
28afbd2b 954void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
15c4dc5a 955{
5f6d6c90 956 // Enable and clear the trace
5f6d6c90 957 iso14a_clear_trace();
7bc95e2e 958 iso14a_set_tracing(TRUE);
81cd0474 959
81cd0474 960 uint8_t sak;
961
962 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
963 uint8_t response1[2];
964
965 switch (tagType) {
966 case 1: { // MIFARE Classic
967 // Says: I am Mifare 1k - original line
968 response1[0] = 0x04;
969 response1[1] = 0x00;
970 sak = 0x08;
971 } break;
972 case 2: { // MIFARE Ultralight
973 // Says: I am a stupid memory tag, no crypto
974 response1[0] = 0x04;
975 response1[1] = 0x00;
976 sak = 0x00;
977 } break;
978 case 3: { // MIFARE DESFire
979 // Says: I am a DESFire tag, ph33r me
980 response1[0] = 0x04;
981 response1[1] = 0x03;
982 sak = 0x20;
983 } break;
984 case 4: { // ISO/IEC 14443-4
985 // Says: I am a javacard (JCOP)
986 response1[0] = 0x04;
987 response1[1] = 0x00;
988 sak = 0x28;
989 } break;
95e63594 990 case 5: { // MIFARE TNP3XXX
991 // Says: I am a toy
992 response1[0] = 0x01;
993 response1[1] = 0x0f;
994 sak = 0x01;
995 } break;
81cd0474 996 default: {
997 Dbprintf("Error: unkown tagtype (%d)",tagType);
998 return;
999 } break;
1000 }
1001
1002 // The second response contains the (mandatory) first 24 bits of the UID
1003 uint8_t response2[5];
1004
1005 // Check if the uid uses the (optional) part
1006 uint8_t response2a[5];
1007 if (uid_2nd) {
1008 response2[0] = 0x88;
1009 num_to_bytes(uid_1st,3,response2+1);
1010 num_to_bytes(uid_2nd,4,response2a);
1011 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1012
1013 // Configure the ATQA and SAK accordingly
1014 response1[0] |= 0x40;
1015 sak |= 0x04;
1016 } else {
1017 num_to_bytes(uid_1st,4,response2);
1018 // Configure the ATQA and SAK accordingly
1019 response1[0] &= 0xBF;
1020 sak &= 0xFB;
1021 }
1022
1023 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1024 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1025
1026 // Prepare the mandatory SAK (for 4 and 7 byte UID)
1027 uint8_t response3[3];
1028 response3[0] = sak;
1029 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1030
1031 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
1032 uint8_t response3a[3];
1033 response3a[0] = sak & 0xFB;
1034 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1035
254b70a4 1036 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
a501c82b 1037 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1038 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1039 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1040 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1041 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 1042 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1043
7bc95e2e 1044 #define TAG_RESPONSE_COUNT 7
1045 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1046 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1047 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1048 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1049 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1050 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1051 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1052 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1053 };
1054
1055 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1056 // Such a response is less time critical, so we can prepare them on the fly
1057 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1058 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1059 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1060 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1061 tag_response_info_t dynamic_response_info = {
1062 .response = dynamic_response_buffer,
1063 .response_n = 0,
1064 .modulation = dynamic_modulation_buffer,
1065 .modulation_n = 0
1066 };
ce02f6f9 1067
7bc95e2e 1068 // Reset the offset pointer of the free buffer
1069 reset_free_buffer();
ce02f6f9 1070
7bc95e2e 1071 // Prepare the responses of the anticollision phase
ce02f6f9 1072 // there will be not enough time to do this at the moment the reader sends it REQA
7bc95e2e 1073 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1074 prepare_allocated_tag_modulation(&responses[i]);
1075 }
15c4dc5a 1076
7bc95e2e 1077 int len = 0;
15c4dc5a 1078
1079 // To control where we are in the protocol
1080 int order = 0;
1081 int lastorder;
1082
1083 // Just to allow some checks
1084 int happened = 0;
1085 int happened2 = 0;
81cd0474 1086 int cmdsRecvd = 0;
15c4dc5a 1087
254b70a4 1088 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 1089 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
15c4dc5a 1090
a501c82b 1091 // buffers used on software Uart:
1092 uint8_t *receivedCmd = ((uint8_t *)BigBuf) + RECV_CMD_OFFSET;
1093 uint8_t *receivedCmdPar = ((uint8_t *)BigBuf) + RECV_CMD_PAR_OFFSET;
1094
254b70a4 1095 cmdsRecvd = 0;
7bc95e2e 1096 tag_response_info_t* p_response;
15c4dc5a 1097
254b70a4 1098 LED_A_ON();
1099 for(;;) {
7bc95e2e 1100 // Clean receive command buffer
1101
a501c82b 1102 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1103 DbpString("Button press");
a501c82b 1104 break;
254b70a4 1105 }
7bc95e2e 1106
1107 p_response = NULL;
1108
254b70a4 1109 // Okay, look at the command now.
1110 lastorder = order;
1111 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1112 p_response = &responses[0]; order = 1;
254b70a4 1113 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1114 p_response = &responses[0]; order = 6;
254b70a4 1115 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1116 p_response = &responses[1]; order = 2;
a501c82b 1117 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1118 p_response = &responses[2]; order = 20;
254b70a4 1119 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1120 p_response = &responses[3]; order = 3;
254b70a4 1121 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1122 p_response = &responses[4]; order = 30;
254b70a4 1123 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
a501c82b 1124 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
7bc95e2e 1125 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
5f6d6c90 1126 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
7bc95e2e 1127 p_response = NULL;
254b70a4 1128 } else if(receivedCmd[0] == 0x50) { // Received a HALT
a501c82b 1129
7bc95e2e 1130 if (tracing) {
a501c82b 1131 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1132 }
1133 p_response = NULL;
254b70a4 1134 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
ce02f6f9 1135 p_response = &responses[5]; order = 7;
254b70a4 1136 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
7bc95e2e 1137 if (tagType == 1 || tagType == 2) { // RATS not supported
1138 EmSend4bit(CARD_NACK_NA);
1139 p_response = NULL;
1140 } else {
1141 p_response = &responses[6]; order = 70;
1142 }
a501c82b 1143 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
7bc95e2e 1144 if (tracing) {
a501c82b 1145 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1146 }
1147 uint32_t nr = bytes_to_num(receivedCmd,4);
1148 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1149 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1150 } else {
1151 // Check for ISO 14443A-4 compliant commands, look at left nibble
1152 switch (receivedCmd[0]) {
1153
1154 case 0x0B:
1155 case 0x0A: { // IBlock (command)
1156 dynamic_response_info.response[0] = receivedCmd[0];
1157 dynamic_response_info.response[1] = 0x00;
1158 dynamic_response_info.response[2] = 0x90;
1159 dynamic_response_info.response[3] = 0x00;
1160 dynamic_response_info.response_n = 4;
1161 } break;
1162
1163 case 0x1A:
1164 case 0x1B: { // Chaining command
1165 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1166 dynamic_response_info.response_n = 2;
1167 } break;
1168
1169 case 0xaa:
1170 case 0xbb: {
1171 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1172 dynamic_response_info.response_n = 2;
1173 } break;
1174
1175 case 0xBA: { //
1176 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1177 dynamic_response_info.response_n = 2;
1178 } break;
1179
1180 case 0xCA:
1181 case 0xC2: { // Readers sends deselect command
1182 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1183 dynamic_response_info.response_n = 2;
1184 } break;
1185
1186 default: {
1187 // Never seen this command before
1188 if (tracing) {
a501c82b 1189 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1190 }
1191 Dbprintf("Received unknown command (len=%d):",len);
1192 Dbhexdump(len,receivedCmd,false);
1193 // Do not respond
1194 dynamic_response_info.response_n = 0;
1195 } break;
1196 }
ce02f6f9 1197
7bc95e2e 1198 if (dynamic_response_info.response_n > 0) {
1199 // Copy the CID from the reader query
1200 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1201
7bc95e2e 1202 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1203 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1204 dynamic_response_info.response_n += 2;
ce02f6f9 1205
7bc95e2e 1206 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1207 Dbprintf("Error preparing tag response");
1208 if (tracing) {
a501c82b 1209 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1210 }
1211 break;
1212 }
1213 p_response = &dynamic_response_info;
1214 }
81cd0474 1215 }
15c4dc5a 1216
1217 // Count number of wakeups received after a halt
1218 if(order == 6 && lastorder == 5) { happened++; }
1219
1220 // Count number of other messages after a halt
1221 if(order != 6 && lastorder == 5) { happened2++; }
1222
15c4dc5a 1223 if(cmdsRecvd > 999) {
1224 DbpString("1000 commands later...");
254b70a4 1225 break;
15c4dc5a 1226 }
ce02f6f9 1227 cmdsRecvd++;
1228
1229 if (p_response != NULL) {
7bc95e2e 1230 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1231 // do the tracing for the previous reader request and this tag answer:
a501c82b 1232 uint8_t par[MAX_PARITY_SIZE];
1233 GetParity(p_response->response, p_response->response_n, par);
1234
7bc95e2e 1235 EmLogTrace(Uart.output,
1236 Uart.len,
1237 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1238 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
a501c82b 1239 Uart.parity,
7bc95e2e 1240 p_response->response,
1241 p_response->response_n,
1242 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1243 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
a501c82b 1244 par);
7bc95e2e 1245 }
1246
1247 if (!tracing) {
1248 Dbprintf("Trace Full. Simulation stopped.");
1249 break;
1250 }
1251 }
15c4dc5a 1252
1253 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1254 LED_A_OFF();
1255}
1256
9492e0b0 1257
1258// prepare a delayed transfer. This simply shifts ToSend[] by a number
1259// of bits specified in the delay parameter.
1260void PrepareDelayedTransfer(uint16_t delay)
1261{
1262 uint8_t bitmask = 0;
1263 uint8_t bits_to_shift = 0;
1264 uint8_t bits_shifted = 0;
1265
1266 delay &= 0x07;
1267 if (delay) {
1268 for (uint16_t i = 0; i < delay; i++) {
1269 bitmask |= (0x01 << i);
1270 }
7bc95e2e 1271 ToSend[ToSendMax++] = 0x00;
9492e0b0 1272 for (uint16_t i = 0; i < ToSendMax; i++) {
1273 bits_to_shift = ToSend[i] & bitmask;
1274 ToSend[i] = ToSend[i] >> delay;
1275 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1276 bits_shifted = bits_to_shift;
1277 }
1278 }
1279}
1280
7bc95e2e 1281
1282//-------------------------------------------------------------------------------------
15c4dc5a 1283// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1284// Parameter timing:
7bc95e2e 1285// if NULL: transfer at next possible time, taking into account
1286// request guard time and frame delay time
1287// if == 0: transfer immediately and return time of transfer
9492e0b0 1288// if != 0: delay transfer until time specified
7bc95e2e 1289//-------------------------------------------------------------------------------------
a501c82b 1290static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1291{
7bc95e2e 1292
9492e0b0 1293 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1294
7bc95e2e 1295 uint32_t ThisTransferTime = 0;
e30c654b 1296
9492e0b0 1297 if (timing) {
1298 if(*timing == 0) { // Measure time
7bc95e2e 1299 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
9492e0b0 1300 } else {
1301 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1302 }
7bc95e2e 1303 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1304 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1305 LastTimeProxToAirStart = *timing;
1306 } else {
1307 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1308 while(GetCountSspClk() < ThisTransferTime);
1309 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1310 }
1311
7bc95e2e 1312 // clear TXRDY
1313 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1314
7bc95e2e 1315 uint16_t c = 0;
9492e0b0 1316 for(;;) {
1317 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1318 AT91C_BASE_SSC->SSC_THR = cmd[c];
1319 c++;
1320 if(c >= len) {
1321 break;
1322 }
1323 }
1324 }
7bc95e2e 1325
f6c18637 1326 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1327}
1328
7bc95e2e 1329
15c4dc5a 1330//-----------------------------------------------------------------------------
195af472 1331// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1332//-----------------------------------------------------------------------------
a501c82b 1333void CodeIso14443aBitsAsReaderPar(const uint8_t * cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1334{
7bc95e2e 1335 int i, j;
1336 int last;
1337 uint8_t b;
e30c654b 1338
7bc95e2e 1339 ToSendReset();
e30c654b 1340
7bc95e2e 1341 // Start of Communication (Seq. Z)
1342 ToSend[++ToSendMax] = SEC_Z;
1343 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1344 last = 0;
1345
1346 size_t bytecount = nbytes(bits);
1347 // Generate send structure for the data bits
1348 for (i = 0; i < bytecount; i++) {
1349 // Get the current byte to send
1350 b = cmd[i];
1351 size_t bitsleft = MIN((bits-(i*8)),8);
1352
1353 for (j = 0; j < bitsleft; j++) {
1354 if (b & 1) {
1355 // Sequence X
1356 ToSend[++ToSendMax] = SEC_X;
1357 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1358 last = 1;
1359 } else {
1360 if (last == 0) {
1361 // Sequence Z
1362 ToSend[++ToSendMax] = SEC_Z;
1363 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1364 } else {
1365 // Sequence Y
1366 ToSend[++ToSendMax] = SEC_Y;
1367 last = 0;
1368 }
1369 }
1370 b >>= 1;
1371 }
1372
a501c82b 1373 // Only transmit parity bit if we transmitted a complete byte
7bc95e2e 1374 if (j == 8) {
1375 // Get the parity bit
a501c82b 1376 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1377 // Sequence X
1378 ToSend[++ToSendMax] = SEC_X;
1379 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1380 last = 1;
1381 } else {
1382 if (last == 0) {
1383 // Sequence Z
1384 ToSend[++ToSendMax] = SEC_Z;
1385 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1386 } else {
1387 // Sequence Y
1388 ToSend[++ToSendMax] = SEC_Y;
1389 last = 0;
1390 }
1391 }
1392 }
1393 }
e30c654b 1394
7bc95e2e 1395 // End of Communication: Logic 0 followed by Sequence Y
1396 if (last == 0) {
1397 // Sequence Z
1398 ToSend[++ToSendMax] = SEC_Z;
1399 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1400 } else {
1401 // Sequence Y
1402 ToSend[++ToSendMax] = SEC_Y;
1403 last = 0;
1404 }
1405 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1406
7bc95e2e 1407 // Convert to length of command:
1408 ToSendMax++;
15c4dc5a 1409}
1410
195af472 1411//-----------------------------------------------------------------------------
1412// Prepare reader command to send to FPGA
1413//-----------------------------------------------------------------------------
a501c82b 1414void CodeIso14443aAsReaderPar(const uint8_t * cmd, uint16_t len, const uint8_t *parity)
195af472 1415{
a501c82b 1416 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1417}
1418
9ca155ba
M
1419//-----------------------------------------------------------------------------
1420// Wait for commands from reader
1421// Stop when button is pressed (return 1) or field was gone (return 2)
1422// Or return 0 when command is captured
1423//-----------------------------------------------------------------------------
a501c82b 1424static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
9ca155ba
M
1425{
1426 *len = 0;
1427
1428 uint32_t timer = 0, vtime = 0;
1429 int analogCnt = 0;
1430 int analogAVG = 0;
1431
1432 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1433 // only, since we are receiving, not transmitting).
1434 // Signal field is off with the appropriate LED
1435 LED_D_OFF();
1436 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1437
1438 // Set ADC to read field strength
1439 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1440 AT91C_BASE_ADC->ADC_MR =
1441 ADC_MODE_PRESCALE(32) |
1442 ADC_MODE_STARTUP_TIME(16) |
1443 ADC_MODE_SAMPLE_HOLD_TIME(8);
1444 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1445 // start ADC
1446 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1447
1448 // Now run a 'software UART' on the stream of incoming samples.
a501c82b 1449 UartInit(received, parity);
7bc95e2e 1450
1451 // Clear RXRDY:
1452 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba
M
1453
1454 for(;;) {
1455 WDT_HIT();
1456
1457 if (BUTTON_PRESS()) return 1;
1458
1459 // test if the field exists
1460 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1461 analogCnt++;
1462 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1463 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1464 if (analogCnt >= 32) {
1465 if ((33000 * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1466 vtime = GetTickCount();
1467 if (!timer) timer = vtime;
1468 // 50ms no field --> card to idle state
1469 if (vtime - timer > 50) return 2;
1470 } else
1471 if (timer) timer = 0;
1472 analogCnt = 0;
1473 analogAVG = 0;
1474 }
1475 }
7bc95e2e 1476
9ca155ba 1477 // receive and test the miller decoding
7bc95e2e 1478 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1479 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1480 if(MillerDecoding(b, 0)) {
1481 *len = Uart.len;
9ca155ba
M
1482 return 0;
1483 }
7bc95e2e 1484 }
1485
9ca155ba
M
1486 }
1487}
1488
9ca155ba 1489
a501c82b 1490static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
7bc95e2e 1491{
1492 uint8_t b;
1493 uint16_t i = 0;
1494 uint32_t ThisTransferTime;
1495
9ca155ba
M
1496 // Modulate Manchester
1497 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1498
1499 // include correction bit if necessary
1500 if (Uart.parityBits & 0x01) {
1501 correctionNeeded = TRUE;
1502 }
1503 if(correctionNeeded) {
9ca155ba
M
1504 // 1236, so correction bit needed
1505 i = 0;
7bc95e2e 1506 } else {
1507 i = 1;
9ca155ba 1508 }
7bc95e2e 1509
d714d3ef 1510 // clear receiving shift register and holding register
7bc95e2e 1511 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1512 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1513 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1514 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1515
7bc95e2e 1516 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1517 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1518 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1519 if (AT91C_BASE_SSC->SSC_RHR) break;
1520 }
1521
1522 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1523
1524 // Clear TXRDY:
1525 AT91C_BASE_SSC->SSC_THR = SEC_F;
1526
9ca155ba 1527 // send cycle
7bc95e2e 1528 for(; i <= respLen; ) {
9ca155ba 1529 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1530 AT91C_BASE_SSC->SSC_THR = resp[i++];
1531 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1532 }
7bc95e2e 1533
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M
1534 if(BUTTON_PRESS()) {
1535 break;
1536 }
1537 }
1538
7bc95e2e 1539 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1540 for (i = 0; i < 2 ; ) {
1541 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1542 AT91C_BASE_SSC->SSC_THR = SEC_F;
1543 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1544 i++;
1545 }
1546 }
1547
1548 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1549
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M
1550 return 0;
1551}
1552
7bc95e2e 1553int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1554 Code4bitAnswerAsTag(resp);
0a39986e 1555 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1556 // do the tracing for the previous reader request and this tag answer:
a501c82b 1557 uint8_t par[1];
1558 GetParity(&resp, 1, par);
7bc95e2e 1559 EmLogTrace(Uart.output,
1560 Uart.len,
1561 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1562 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
a501c82b 1563 Uart.parity,
7bc95e2e 1564 &resp,
1565 1,
1566 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1567 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
a501c82b 1568 par);
0a39986e 1569 return res;
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M
1570}
1571
8f51ddb0 1572int EmSend4bit(uint8_t resp){
7bc95e2e 1573 return EmSend4bitEx(resp, false);
8f51ddb0
M
1574}
1575
a501c82b 1576int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1577 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1578 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1579 // do the tracing for the previous reader request and this tag answer:
1580 EmLogTrace(Uart.output,
1581 Uart.len,
1582 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1583 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
a501c82b 1584 Uart.parity,
7bc95e2e 1585 resp,
1586 respLen,
1587 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1588 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
a501c82b 1589 par);
8f51ddb0
M
1590 return res;
1591}
1592
a501c82b 1593int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1594 uint8_t par[MAX_PARITY_SIZE];
1595 GetParity(resp, respLen, par);
1596 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
8f51ddb0 1597}
a501c82b 1598
1599int EmSendCmd(uint8_t *resp, uint16_t respLen){
1600 uint8_t par[MAX_PARITY_SIZE];
1601 GetParity(resp, respLen, par);
1602 return EmSendCmdExPar(resp, respLen, false, par);
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M
1603}
1604
a501c82b 1605int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1606 return EmSendCmdExPar(resp, respLen, false, par);
1607}
1608
a501c82b 1609bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1610 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1611{
f5ed4d12 1612 if (tracing) {
a501c82b 1613 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1614 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1615 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1616 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1617 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1618 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1619 reader_EndTime = tag_StartTime - exact_fdt;
1620 reader_StartTime = reader_EndTime - reader_modlen;
1621 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
1622 return FALSE;
f5ed4d12 1623 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1624 } else {
1625 return TRUE;
1626 }
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M
1627}
1628
15c4dc5a 1629//-----------------------------------------------------------------------------
1630// Wait a certain time for tag response
1631// If a response is captured return TRUE
e691fc45 1632// If it takes too long return FALSE
15c4dc5a 1633//-----------------------------------------------------------------------------
a501c82b 1634static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1635{
1b492a97 1636 uint32_t c;
e691fc45 1637
15c4dc5a 1638 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1639 // only, since we are receiving, not transmitting).
1640 // Signal field is on with the appropriate LED
1641 LED_D_ON();
1642 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1643
534983d7 1644 // Now get the answer from the card
a501c82b 1645 DemodInit(receivedResponse, receivedResponsePar);
1646
7bc95e2e 1647 // clear RXRDY:
1648 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1649
15c4dc5a 1650 c = 0;
1651 for(;;) {
534983d7 1652 WDT_HIT();
15c4dc5a 1653
534983d7 1654 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1655 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1656 if(ManchesterDecoding(b, offset, 0)) {
1657 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1658 return TRUE;
a501c82b 1659 } else if (c++ > iso14a_timeout) {
7bc95e2e 1660 return FALSE;
15c4dc5a 1661 }
534983d7 1662 }
1663 }
15c4dc5a 1664}
1665
a501c82b 1666void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1667{
a501c82b 1668 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1669
7bc95e2e 1670 // Send command to tag
1671 TransmitFor14443a(ToSend, ToSendMax, timing);
1672 if(trigger)
1673 LED_A_ON();
dfc3c505 1674
7bc95e2e 1675 // Log reader command in trace buffer
1676 if (tracing) {
a501c82b 1677 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
7bc95e2e 1678 }
15c4dc5a 1679}
1680
a501c82b 1681void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1682{
a501c82b 1683 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1684}
15c4dc5a 1685
a501c82b 1686void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1687{
a501c82b 1688 // Generate parity and redirect
1689 uint8_t par[MAX_PARITY_SIZE];
1690 GetParity(frame, len/8, par);
1691 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1692}
1693
a501c82b 1694void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1695{
a501c82b 1696 // Generate parity and redirect
1697 uint8_t par[MAX_PARITY_SIZE];
1698 GetParity(frame, len, par);
1699 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1700}
1701
a501c82b 1702int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1703{
a501c82b 1704 if (!GetIso14443aAnswerFromTag(receivedAnswer,parity,offset)) return FALSE;
7bc95e2e 1705 if (tracing) {
a501c82b 1706 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1707 }
e691fc45 1708 return Demod.len;
1709}
1710
a501c82b 1711int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
15c4dc5a 1712{
a501c82b 1713 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
7bc95e2e 1714 if (tracing) {
a501c82b 1715 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1716 }
e691fc45 1717 return Demod.len;
f89c7050
M
1718}
1719
e691fc45 1720/* performs iso14443a anticollision procedure
534983d7 1721 * fills the uid pointer unless NULL
1722 * fills resp_data unless NULL */
79a73ab2 1723int iso14443a_select_card(byte_t* uid_ptr, iso14a_card_select_t* p_hi14a_card, uint32_t* cuid_ptr) {
3bc3598e 1724
1725 //uint8_t deselect[] = {0xc2}; //DESELECT
f5ed4d12 1726 //uint8_t halt[] = { 0x50, 0x00, 0x57, 0xCD }; // HALT
a501c82b 1727 uint8_t wupa[] = { 0x52 }; // WAKE-UP
1728 //uint8_t reqa[] = { 0x26 }; // REQUEST A
1729 uint8_t sel_all[] = { 0x93,0x20 };
1730 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1731 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1732 uint8_t *resp = ((uint8_t *)BigBuf) + RECV_RESP_OFFSET;
1733 uint8_t *resp_par = ((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET;
1734
1735 byte_t uid_resp[4];
1736 size_t uid_resp_len;
d3499d36 1737 uint8_t sak = 0x04; // cascade uid
1738 int cascade_level = 0;
1b492a97 1739 int len =0;
a501c82b 1740
d3499d36 1741 // test for the SKYLANDERS TOY.
3bc3598e 1742 // ReaderTransmit(deselect,sizeof(deselect), NULL);
1743 // len = ReaderReceive(resp, resp_par);
a501c82b 1744
d3499d36 1745 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1746 ReaderTransmitBitsPar(wupa,7,0, NULL);
7bc95e2e 1747
d3499d36 1748 // Receive the ATQA
1749 if(!ReaderReceive(resp, resp_par)) return 0;
1750
1751 if(p_hi14a_card) {
1752 memcpy(p_hi14a_card->atqa, resp, 2);
1753 p_hi14a_card->uidlen = 0;
1754 memset(p_hi14a_card->uid,0,10);
1755 }
5f6d6c90 1756
d3499d36 1757 // clear uid
1758 if (uid_ptr) {
1759 memset(uid_ptr,0,10);
1760 }
79a73ab2 1761
ed258538 1762 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1763 // which case we need to make a cascade 2 request and select - this is a long UID
1764 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1765 for(; sak & 0x04; cascade_level++) {
1766 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1767 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1768
1769 // SELECT_ALL
9492e0b0 1770 ReaderTransmit(sel_all,sizeof(sel_all), NULL);
a501c82b 1771 if (!ReaderReceive(resp, resp_par)) return 0;
5f6d6c90 1772
e691fc45 1773 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1774 memset(uid_resp, 0, 4);
1775 uint16_t uid_resp_bits = 0;
1776 uint16_t collision_answer_offset = 0;
1777 // anti-collision-loop:
1778 while (Demod.collisionPos) {
1779 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1780 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1781 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1782 uid_resp[uid_resp_bits & 0xf8] |= UIDbit << (uid_resp_bits % 8);
1783 }
1784 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1785 uid_resp_bits++;
1786 // construct anticollosion command:
1787 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1788 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1789 sel_uid[2+i] = uid_resp[i];
1790 }
1791 collision_answer_offset = uid_resp_bits%8;
1792 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
a501c82b 1793 if (!ReaderReceiveOffset(resp, collision_answer_offset,resp_par)) return 0;
e691fc45 1794 }
1795 // finally, add the last bits and BCC of the UID
1796 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1797 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1798 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1799 }
1800
1801 } else { // no collision, use the response to SELECT_ALL as current uid
1802 memcpy(uid_resp,resp,4);
1803 }
1804 uid_resp_len = 4;
95e63594 1805
e691fc45 1806 // calculate crypto UID. Always use last 4 Bytes.
5f6d6c90 1807 if(cuid_ptr) {
1808 *cuid_ptr = bytes_to_num(uid_resp, 4);
79a73ab2 1809 }
e30c654b 1810
ed258538 1811 // Construct SELECT UID command
e691fc45 1812 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1813 memcpy(sel_uid+2,uid_resp,4); // the UID
1814 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1815 AppendCrc14443a(sel_uid,7); // calculate and add CRC
9492e0b0 1816 ReaderTransmit(sel_uid,sizeof(sel_uid), NULL);
534983d7 1817
ed258538 1818 // Receive the SAK
10403a6a 1819 if (!ReaderReceive(resp, resp_par)) return 0;
ed258538 1820 sak = resp[0];
95e63594 1821
d3499d36 1822 // Test if more parts of the uid are coming
e691fc45 1823 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
a501c82b 1824 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1825 // http://www.nxp.com/documents/application_note/AN10927.pdf
a501c82b 1826 uid_resp[0] = uid_resp[1];
1827 uid_resp[1] = uid_resp[2];
1828 uid_resp[2] = uid_resp[3];
1829
1830 uid_resp_len = 3;
79a73ab2 1831 }
5f6d6c90 1832
79a73ab2 1833 if(uid_ptr) {
1834 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1835 }
5f6d6c90 1836
79a73ab2 1837 if(p_hi14a_card) {
1838 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1839 p_hi14a_card->uidlen += uid_resp_len;
1840 }
ed258538 1841 }
79a73ab2 1842
ed258538 1843 if(p_hi14a_card) {
1844 p_hi14a_card->sak = sak;
1845 p_hi14a_card->ats_len = 0;
1846 }
534983d7 1847
1b492a97 1848 // non iso14443a compliant tag
1849 if( (sak & 0x20) == 0) return 2;
1850
d3499d36 1851 // Request for answer to select
1852 AppendCrc14443a(rats, 2);
1853 ReaderTransmit(rats, sizeof(rats), NULL);
3bc3598e 1854
1b492a97 1855 if (!(len = ReaderReceive(resp, resp_par))) return 0;
5191b3d1 1856
1b492a97 1857
d3499d36 1858 if(p_hi14a_card) {
1859 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1860 p_hi14a_card->ats_len = len;
1861 }
5f6d6c90 1862
d3499d36 1863 // reset the PCB block number
1864 iso14_pcb_blocknum = 0;
1865 return 1;
7e758047 1866}
15c4dc5a 1867
7bc95e2e 1868void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1869 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1870 // Set up the synchronous serial port
1871 FpgaSetupSsc();
7bc95e2e 1872 // connect Demodulated Signal to ADC:
7e758047 1873 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
e30c654b 1874
7e758047 1875 // Signal field is on with the appropriate LED
95e63594 1876 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
7bc95e2e 1877 LED_D_ON();
1878 } else {
1879 LED_D_OFF();
1880 }
1881 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
534983d7 1882
7bc95e2e 1883 // Start the timer
1884 StartCountSspClk();
1885
1886 DemodReset();
1887 UartReset();
1888 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
f38a1528 1889 iso14a_set_timeout(1050); // 10ms default 10*105 =
7e758047 1890}
15c4dc5a 1891
a501c82b 1892int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1893 uint8_t parity[MAX_PARITY_SIZE];
534983d7 1894 uint8_t real_cmd[cmd_len+4];
1895 real_cmd[0] = 0x0a; //I-Block
b0127e65 1896 // put block number into the PCB
1897 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 1898 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1899 memcpy(real_cmd+2, cmd, cmd_len);
1900 AppendCrc14443a(real_cmd,cmd_len+2);
1901
9492e0b0 1902 ReaderTransmit(real_cmd, cmd_len+4, NULL);
a501c82b 1903 size_t len = ReaderReceive(data, parity);
b0127e65 1904 uint8_t * data_bytes = (uint8_t *) data;
1905 if (!len)
1906 return 0; //DATA LINK ERROR
1907 // if we received an I- or R(ACK)-Block with a block number equal to the
1908 // current block number, toggle the current block number
1909 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1910 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1911 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1912 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1913 {
1914 iso14_pcb_blocknum ^= 1;
1915 }
1916
534983d7 1917 return len;
1918}
1919
7e758047 1920//-----------------------------------------------------------------------------
1921// Read an ISO 14443a tag. Send out commands and store answers.
1922//
1923//-----------------------------------------------------------------------------
7bc95e2e 1924void ReaderIso14443a(UsbCommand *c)
7e758047 1925{
534983d7 1926 iso14a_command_t param = c->arg[0];
7bc95e2e 1927 uint8_t *cmd = c->d.asBytes;
a501c82b 1928 size_t len = c->arg[1];
1929 size_t lenbits = c->arg[2];
9492e0b0 1930 uint32_t arg0 = 0;
1931 byte_t buf[USB_CMD_DATA_SIZE];
a501c82b 1932 uint8_t par[MAX_PARITY_SIZE];
902cb3c0 1933
5f6d6c90 1934 if(param & ISO14A_CONNECT) {
1935 iso14a_clear_trace();
1936 }
e691fc45 1937
7bc95e2e 1938 iso14a_set_tracing(TRUE);
e30c654b 1939
79a73ab2 1940 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1941 iso14a_set_trigger(TRUE);
9492e0b0 1942 }
15c4dc5a 1943
534983d7 1944 if(param & ISO14A_CONNECT) {
7bc95e2e 1945 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 1946 if(!(param & ISO14A_NO_SELECT)) {
1947 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1948 arg0 = iso14443a_select_card(NULL,card,NULL);
1949 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1950 }
534983d7 1951 }
e30c654b 1952
534983d7 1953 if(param & ISO14A_SET_TIMEOUT) {
313ee67e 1954 iso14a_set_timeout(c->arg[2]);
534983d7 1955 }
e30c654b 1956
534983d7 1957 if(param & ISO14A_APDU) {
902cb3c0 1958 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 1959 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1960 }
e30c654b 1961
534983d7 1962 if(param & ISO14A_RAW) {
1963 if(param & ISO14A_APPEND_CRC) {
1964 AppendCrc14443a(cmd,len);
1965 len += 2;
a501c82b 1966 if (lenbits) lenbits += 16;
15c4dc5a 1967 }
a501c82b 1968 if(lenbits>0) {
1969 GetParity(cmd, lenbits/8, par);
1970 ReaderTransmitBitsPar(cmd, lenbits, par, NULL);
5f6d6c90 1971 } else {
1972 ReaderTransmit(cmd,len, NULL);
1973 }
a501c82b 1974 arg0 = ReaderReceive(buf, par);
9492e0b0 1975 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1976 }
15c4dc5a 1977
79a73ab2 1978 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1979 iso14a_set_trigger(FALSE);
9492e0b0 1980 }
15c4dc5a 1981
79a73ab2 1982 if(param & ISO14A_NO_DISCONNECT) {
534983d7 1983 return;
9492e0b0 1984 }
15c4dc5a 1985
15c4dc5a 1986 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1987 LEDsoff();
15c4dc5a 1988}
b0127e65 1989
1c611bbd 1990
1c611bbd 1991// Determine the distance between two nonces.
1992// Assume that the difference is small, but we don't know which is first.
1993// Therefore try in alternating directions.
1994int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1995
1996 uint16_t i;
1997 uint32_t nttmp1, nttmp2;
e772353f 1998
1c611bbd 1999 if (nt1 == nt2) return 0;
2000
2001 nttmp1 = nt1;
2002 nttmp2 = nt2;
2003
2004 for (i = 1; i < 32768; i++) {
2005 nttmp1 = prng_successor(nttmp1, 1);
2006 if (nttmp1 == nt2) return i;
2007 nttmp2 = prng_successor(nttmp2, 1);
2008 if (nttmp2 == nt1) return -i;
2009 }
2010
2011 return(-99999); // either nt1 or nt2 are invalid nonces
e772353f 2012}
2013
e772353f 2014
1c611bbd 2015//-----------------------------------------------------------------------------
2016// Recover several bits of the cypher stream. This implements (first stages of)
2017// the algorithm described in "The Dark Side of Security by Obscurity and
2018// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2019// (article by Nicolas T. Courtois, 2009)
2020//-----------------------------------------------------------------------------
2021void ReaderMifare(bool first_try)
2022{
2023 // Mifare AUTH
2024 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2025 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2026 static uint8_t mf_nr_ar3;
e772353f 2027
a501c82b 2028 uint8_t* receivedAnswer = (((uint8_t *)BigBuf) + RECV_RESP_OFFSET);
2029 uint8_t* receivedAnswerPar = (((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET);
7bc95e2e 2030
d2f487af 2031 iso14a_clear_trace();
7bc95e2e 2032 iso14a_set_tracing(TRUE);
e772353f 2033
1c611bbd 2034 byte_t nt_diff = 0;
a501c82b 2035 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2036 static byte_t par_low = 0;
2037 bool led_on = TRUE;
a501c82b 2038 uint8_t uid[10] ={0};
1c611bbd 2039 uint32_t cuid;
e772353f 2040
a61b4976 2041 uint32_t nt = 0;
2042 uint32_t previous_nt = 0;
1c611bbd 2043 static uint32_t nt_attacked = 0;
95e63594 2044 byte_t par_list[8] = {0x00};
2045 byte_t ks_list[8] = {0x00};
e772353f 2046
1c611bbd 2047 static uint32_t sync_time;
2048 static uint32_t sync_cycles;
2049 int catch_up_cycles = 0;
2050 int last_catch_up = 0;
2051 uint16_t consecutive_resyncs = 0;
2052 int isOK = 0;
e772353f 2053
1c611bbd 2054 if (first_try) {
1c611bbd 2055 mf_nr_ar3 = 0;
7bc95e2e 2056 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2057 sync_time = GetCountSspClk() & 0xfffffff8;
1c611bbd 2058 sync_cycles = 65536; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2059 nt_attacked = 0;
2060 nt = 0;
a501c82b 2061 par[0] = 0;
1c611bbd 2062 }
2063 else {
2064 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1c611bbd 2065 mf_nr_ar3++;
2066 mf_nr_ar[3] = mf_nr_ar3;
a501c82b 2067 par[0] = par_low;
1c611bbd 2068 }
e30c654b 2069
15c4dc5a 2070 LED_A_ON();
2071 LED_B_OFF();
2072 LED_C_OFF();
1c611bbd 2073
7bc95e2e 2074
1c611bbd 2075 for(uint16_t i = 0; TRUE; i++) {
2076
2077 WDT_HIT();
e30c654b 2078
1c611bbd 2079 // Test if the action was cancelled
2080 if(BUTTON_PRESS()) {
2081 break;
2082 }
2083
2084 LED_C_ON();
e30c654b 2085
1c611bbd 2086 if(!iso14443a_select_card(uid, NULL, &cuid)) {
9492e0b0 2087 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1c611bbd 2088 continue;
2089 }
2090
9492e0b0 2091 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
1c611bbd 2092 catch_up_cycles = 0;
2093
2094 // if we missed the sync time already, advance to the next nonce repeat
7bc95e2e 2095 while(GetCountSspClk() > sync_time) {
9492e0b0 2096 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
1c611bbd 2097 }
e30c654b 2098
9492e0b0 2099 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2100 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
f89c7050 2101
1c611bbd 2102 // Receive the (4 Byte) "random" nonce
a501c82b 2103 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2104 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
1c611bbd 2105 continue;
2106 }
2107
1c611bbd 2108 previous_nt = nt;
2109 nt = bytes_to_num(receivedAnswer, 4);
2110
2111 // Transmit reader nonce with fake par
9492e0b0 2112 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
1c611bbd 2113
2114 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2115 int nt_distance = dist_nt(previous_nt, nt);
2116 if (nt_distance == 0) {
2117 nt_attacked = nt;
2118 }
2119 else {
2120 if (nt_distance == -99999) { // invalid nonce received, try again
2121 continue;
2122 }
2123 sync_cycles = (sync_cycles - nt_distance);
9492e0b0 2124 if (MF_DBGLEVEL >= 3) Dbprintf("calibrating in cycle %d. nt_distance=%d, Sync_cycles: %d\n", i, nt_distance, sync_cycles);
1c611bbd 2125 continue;
2126 }
2127 }
2128
2129 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2130 catch_up_cycles = -dist_nt(nt_attacked, nt);
2131 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2132 catch_up_cycles = 0;
2133 continue;
2134 }
2135 if (catch_up_cycles == last_catch_up) {
2136 consecutive_resyncs++;
2137 }
2138 else {
2139 last_catch_up = catch_up_cycles;
2140 consecutive_resyncs = 0;
2141 }
2142 if (consecutive_resyncs < 3) {
9492e0b0 2143 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
1c611bbd 2144 }
2145 else {
2146 sync_cycles = sync_cycles + catch_up_cycles;
9492e0b0 2147 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
1c611bbd 2148 }
2149 continue;
2150 }
2151
2152 consecutive_resyncs = 0;
2153
2154 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
a501c82b 2155 if (ReaderReceive(receivedAnswer, receivedAnswerPar))
1c611bbd 2156 {
9492e0b0 2157 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2158
2159 if (nt_diff == 0)
2160 {
a501c82b 2161 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2162 }
2163
2164 led_on = !led_on;
2165 if(led_on) LED_B_ON(); else LED_B_OFF();
2166
a501c82b 2167 par_list[nt_diff] = SwapBits(par[0], 8);
1c611bbd 2168 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2169
2170 // Test if the information is complete
2171 if (nt_diff == 0x07) {
2172 isOK = 1;
2173 break;
2174 }
2175
2176 nt_diff = (nt_diff + 1) & 0x07;
2177 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
a501c82b 2178 par[0] = par_low;
1c611bbd 2179 } else {
2180 if (nt_diff == 0 && first_try)
2181 {
a501c82b 2182 par[0]++;
1c611bbd 2183 } else {
a501c82b 2184 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2185 }
2186 }
2187 }
2188
1c611bbd 2189
2190 mf_nr_ar[3] &= 0x1F;
2191
2192 byte_t buf[28];
2193 memcpy(buf + 0, uid, 4);
2194 num_to_bytes(nt, 4, buf + 4);
2195 memcpy(buf + 8, par_list, 8);
2196 memcpy(buf + 16, ks_list, 8);
2197 memcpy(buf + 24, mf_nr_ar, 4);
2198
2199 cmd_send(CMD_ACK,isOK,0,0,buf,28);
2200
2201 // Thats it...
2202 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2203 LEDsoff();
7bc95e2e 2204
2205 iso14a_set_tracing(FALSE);
20f9a2a1 2206}
1c611bbd 2207
d2f487af 2208/**
2209 *MIFARE 1K simulate.
2210 *
2211 *@param flags :
2212 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2213 * 4B_FLAG_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2214 * 7B_FLAG_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2215 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
2216 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2217 */
2218void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
20f9a2a1 2219{
50193c1e 2220 int cardSTATE = MFEMUL_NOFIELD;
8556b852 2221 int _7BUID = 0;
9ca155ba 2222 int vHf = 0; // in mV
8f51ddb0 2223 int res;
0a39986e
M
2224 uint32_t selTimer = 0;
2225 uint32_t authTimer = 0;
a501c82b 2226 uint16_t len = 0;
8f51ddb0 2227 uint8_t cardWRBL = 0;
9ca155ba
M
2228 uint8_t cardAUTHSC = 0;
2229 uint8_t cardAUTHKEY = 0xff; // no authentication
51969283 2230 uint32_t cardRr = 0;
9ca155ba 2231 uint32_t cuid = 0;
d2f487af 2232 //uint32_t rn_enc = 0;
51969283 2233 uint32_t ans = 0;
0014cb46
M
2234 uint32_t cardINTREG = 0;
2235 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2236 struct Crypto1State mpcs = {0, 0};
2237 struct Crypto1State *pcs;
2238 pcs = &mpcs;
d2f487af 2239 uint32_t numReads = 0;//Counts numer of times reader read a block
a501c82b 2240 uint8_t* receivedCmd = get_bigbufptr_recvcmdbuf();
2241 uint8_t* receivedCmd_par = receivedCmd + MAX_FRAME_SIZE;
2242 uint8_t* response = get_bigbufptr_recvrespbuf();
2243 uint8_t* response_par = response + MAX_FRAME_SIZE;
9ca155ba 2244
d2f487af 2245 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
2246 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2247 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
2248 uint8_t rSAK[] = {0x08, 0xb6, 0xdd};
2249 uint8_t rSAK1[] = {0x04, 0xda, 0x17};
9ca155ba 2250
d2f487af 2251 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2252 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
7bc95e2e 2253
d2f487af 2254 //Here, we collect UID,NT,AR,NR,UID2,NT2,AR2,NR2
2255 // This can be used in a reader-only attack.
2256 // (it can also be retrieved via 'hf 14a list', but hey...
2257 uint32_t ar_nr_responses[] = {0,0,0,0,0,0,0,0};
2258 uint8_t ar_nr_collected = 0;
0014cb46 2259
0a39986e 2260 // clear trace
7bc95e2e 2261 iso14a_clear_trace();
2262 iso14a_set_tracing(TRUE);
51969283 2263
7bc95e2e 2264 // Authenticate response - nonce
51969283 2265 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
7bc95e2e 2266
d2f487af 2267 //-- Determine the UID
2268 // Can be set from emulator memory, incoming data
2269 // and can be 7 or 4 bytes long
7bc95e2e 2270 if (flags & FLAG_4B_UID_IN_DATA)
d2f487af 2271 {
2272 // 4B uid comes from data-portion of packet
2273 memcpy(rUIDBCC1,datain,4);
8556b852 2274 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
8556b852 2275
7bc95e2e 2276 } else if (flags & FLAG_7B_UID_IN_DATA) {
d2f487af 2277 // 7B uid comes from data-portion of packet
2278 memcpy(&rUIDBCC1[1],datain,3);
2279 memcpy(rUIDBCC2, datain+3, 4);
2280 _7BUID = true;
7bc95e2e 2281 } else {
d2f487af 2282 // get UID from emul memory
2283 emlGetMemBt(receivedCmd, 7, 1);
2284 _7BUID = !(receivedCmd[0] == 0x00);
2285 if (!_7BUID) { // ---------- 4BUID
2286 emlGetMemBt(rUIDBCC1, 0, 4);
2287 } else { // ---------- 7BUID
2288 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2289 emlGetMemBt(rUIDBCC2, 3, 4);
2290 }
2291 }
7bc95e2e 2292
d2f487af 2293 /*
2294 * Regardless of what method was used to set the UID, set fifth byte and modify
2295 * the ATQA for 4 or 7-byte UID
2296 */
d2f487af 2297 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
7bc95e2e 2298 if (_7BUID) {
d2f487af 2299 rATQA[0] = 0x44;
8556b852 2300 rUIDBCC1[0] = 0x88;
8556b852
M
2301 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2302 }
2303
9ca155ba 2304 // We need to listen to the high-frequency, peak-detected path.
7bc95e2e 2305 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
9ca155ba 2306
9ca155ba 2307
d2f487af 2308 if (MF_DBGLEVEL >= 1) {
2309 if (!_7BUID) {
a501c82b 2310 Dbprintf("4B UID: %02x%02x%02x%02x",
2311 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3]);
7bc95e2e 2312 } else {
a501c82b 2313 Dbprintf("7B UID: (%02x)%02x%02x%02x%02x%02x%02x%02x",
2314 rUIDBCC1[0], rUIDBCC1[1], rUIDBCC1[2], rUIDBCC1[3],
2315 rUIDBCC2[0], rUIDBCC2[1] ,rUIDBCC2[2], rUIDBCC2[3]);
d2f487af 2316 }
2317 }
7bc95e2e 2318
2319 bool finished = FALSE;
d2f487af 2320 while (!BUTTON_PRESS() && !finished) {
9ca155ba 2321 WDT_HIT();
9ca155ba
M
2322
2323 // find reader field
2324 // Vref = 3300mV, and an 10:1 voltage divider on the input
2325 // can measure voltages up to 33000 mV
2326 if (cardSTATE == MFEMUL_NOFIELD) {
2327 vHf = (33000 * AvgAdc(ADC_CHAN_HF)) >> 10;
2328 if (vHf > MF_MINFIELDV) {
0014cb46 2329 cardSTATE_TO_IDLE();
9ca155ba
M
2330 LED_A_ON();
2331 }
2332 }
d2f487af 2333 if(cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2334
d2f487af 2335 //Now, get data
2336
a501c82b 2337 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2338 if (res == 2) { //Field is off!
2339 cardSTATE = MFEMUL_NOFIELD;
2340 LEDsoff();
2341 continue;
7bc95e2e 2342 } else if (res == 1) {
2343 break; //return value 1 means button press
2344 }
2345
d2f487af 2346 // REQ or WUP request in ANY state and WUP in HALTED state
2347 if (len == 1 && ((receivedCmd[0] == 0x26 && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == 0x52)) {
2348 selTimer = GetTickCount();
2349 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == 0x52));
2350 cardSTATE = MFEMUL_SELECT1;
2351
2352 // init crypto block
2353 LED_B_OFF();
2354 LED_C_OFF();
2355 crypto1_destroy(pcs);
2356 cardAUTHKEY = 0xff;
2357 continue;
0a39986e 2358 }
7bc95e2e 2359
50193c1e 2360 switch (cardSTATE) {
d2f487af 2361 case MFEMUL_NOFIELD:
2362 case MFEMUL_HALTED:
50193c1e 2363 case MFEMUL_IDLE:{
a501c82b 2364 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2365 break;
2366 }
2367 case MFEMUL_SELECT1:{
9ca155ba
M
2368 // select all
2369 if (len == 2 && (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x20)) {
d2f487af 2370 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2371 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2372 break;
9ca155ba
M
2373 }
2374
d2f487af 2375 if (MF_DBGLEVEL >= 4 && len == 9 && receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 )
2376 {
2377 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2378 }
9ca155ba 2379 // select card
0a39986e
M
2380 if (len == 9 &&
2381 (receivedCmd[0] == 0x93 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
bfb6a143 2382 EmSendCmd(_7BUID?rSAK1:rSAK, _7BUID?sizeof(rSAK1):sizeof(rSAK));
9ca155ba 2383 cuid = bytes_to_num(rUIDBCC1, 4);
8556b852
M
2384 if (!_7BUID) {
2385 cardSTATE = MFEMUL_WORK;
0014cb46
M
2386 LED_B_ON();
2387 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2388 break;
8556b852
M
2389 } else {
2390 cardSTATE = MFEMUL_SELECT2;
8556b852 2391 }
9ca155ba 2392 }
50193c1e
M
2393 break;
2394 }
d2f487af 2395 case MFEMUL_AUTH1:{
2396 if( len != 8)
2397 {
2398 cardSTATE_TO_IDLE();
a501c82b 2399 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2400 break;
2401 }
2402 uint32_t ar = bytes_to_num(receivedCmd, 4);
a501c82b 2403 uint32_t nr = bytes_to_num(&receivedCmd[4], 4);
d2f487af 2404
2405 //Collect AR/NR
2406 if(ar_nr_collected < 2){
273b57a7 2407 if(ar_nr_responses[2] != ar)
2408 {// Avoid duplicates... probably not necessary, ar should vary.
d2f487af 2409 ar_nr_responses[ar_nr_collected*4] = cuid;
2410 ar_nr_responses[ar_nr_collected*4+1] = nonce;
2411 ar_nr_responses[ar_nr_collected*4+2] = ar;
2412 ar_nr_responses[ar_nr_collected*4+3] = nr;
273b57a7 2413 ar_nr_collected++;
d2f487af 2414 }
2415 }
2416
2417 // --- crypto
2418 crypto1_word(pcs, ar , 1);
2419 cardRr = nr ^ crypto1_word(pcs, 0, 0);
2420
2421 // test if auth OK
2422 if (cardRr != prng_successor(nonce, 64)){
a501c82b 2423 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2424 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2425 cardRr, prng_successor(nonce, 64));
7bc95e2e 2426 // Shouldn't we respond anything here?
d2f487af 2427 // Right now, we don't nack or anything, which causes the
2428 // reader to do a WUPA after a while. /Martin
b03c0f2d 2429 // -- which is the correct response. /piwi
d2f487af 2430 cardSTATE_TO_IDLE();
a501c82b 2431 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2432 break;
2433 }
2434
2435 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2436
2437 num_to_bytes(ans, 4, rAUTH_AT);
2438 // --- crypto
2439 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2440 LED_C_ON();
2441 cardSTATE = MFEMUL_WORK;
b03c0f2d 2442 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2443 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2444 GetTickCount() - authTimer);
d2f487af 2445 break;
2446 }
50193c1e 2447 case MFEMUL_SELECT2:{
7bc95e2e 2448 if (!len) {
a501c82b 2449 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2450 break;
2451 }
8556b852 2452 if (len == 2 && (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x20)) {
9ca155ba 2453 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
8556b852
M
2454 break;
2455 }
9ca155ba 2456
8556b852
M
2457 // select 2 card
2458 if (len == 9 &&
2459 (receivedCmd[0] == 0x95 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
2460 EmSendCmd(rSAK, sizeof(rSAK));
8556b852
M
2461 cuid = bytes_to_num(rUIDBCC2, 4);
2462 cardSTATE = MFEMUL_WORK;
2463 LED_B_ON();
0014cb46 2464 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
8556b852
M
2465 break;
2466 }
0014cb46
M
2467
2468 // i guess there is a command). go into the work state.
7bc95e2e 2469 if (len != 4) {
a501c82b 2470 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2471 break;
2472 }
0014cb46 2473 cardSTATE = MFEMUL_WORK;
d2f487af 2474 //goto lbWORK;
2475 //intentional fall-through to the next case-stmt
50193c1e 2476 }
51969283 2477
7bc95e2e 2478 case MFEMUL_WORK:{
2479 if (len == 0) {
a501c82b 2480 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2481 break;
2482 }
2483
d2f487af 2484 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2485
7bc95e2e 2486 if(encrypted_data) {
51969283
M
2487 // decrypt seqence
2488 mf_crypto1_decrypt(pcs, receivedCmd, len);
d2f487af 2489 }
7bc95e2e 2490
d2f487af 2491 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
2492 authTimer = GetTickCount();
2493 cardAUTHSC = receivedCmd[1] / 4; // received block num
2494 cardAUTHKEY = receivedCmd[0] - 0x60;
2495 crypto1_destroy(pcs);//Added by martin
2496 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
51969283 2497
d2f487af 2498 if (!encrypted_data) { // first authentication
b03c0f2d 2499 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
51969283 2500
d2f487af 2501 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2502 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
7bc95e2e 2503 } else { // nested authentication
b03c0f2d 2504 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
7bc95e2e 2505 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2506 num_to_bytes(ans, 4, rAUTH_AT);
2507 }
2508 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2509 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2510 cardSTATE = MFEMUL_AUTH1;
2511 break;
51969283 2512 }
7bc95e2e 2513
8f51ddb0
M
2514 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2515 // BUT... ACK --> NACK
2516 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2517 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2518 break;
2519 }
2520
2521 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2522 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2523 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2524 break;
0a39986e
M
2525 }
2526
7bc95e2e 2527 if(len != 4) {
a501c82b 2528 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2529 break;
2530 }
d2f487af 2531
2532 if(receivedCmd[0] == 0x30 // read block
2533 || receivedCmd[0] == 0xA0 // write block
b03c0f2d 2534 || receivedCmd[0] == 0xC0 // inc
2535 || receivedCmd[0] == 0xC1 // dec
2536 || receivedCmd[0] == 0xC2 // restore
7bc95e2e 2537 || receivedCmd[0] == 0xB0) { // transfer
2538 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2539 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2540 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2541 break;
2542 }
2543
7bc95e2e 2544 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2545 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
d2f487af 2546 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2547 break;
2548 }
d2f487af 2549 }
2550 // read block
2551 if (receivedCmd[0] == 0x30) {
b03c0f2d 2552 if (MF_DBGLEVEL >= 4) {
d2f487af 2553 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2554 }
8f51ddb0
M
2555 emlGetMem(response, receivedCmd[1], 1);
2556 AppendCrc14443a(response, 16);
a501c82b 2557 mf_crypto1_encrypt(pcs, response, 18, response_par);
2558 EmSendCmdPar(response, 18, response_par);
d2f487af 2559 numReads++;
7bc95e2e 2560 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
d2f487af 2561 Dbprintf("%d reads done, exiting", numReads);
2562 finished = true;
2563 }
0a39986e
M
2564 break;
2565 }
0a39986e 2566 // write block
d2f487af 2567 if (receivedCmd[0] == 0xA0) {
b03c0f2d 2568 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
8f51ddb0 2569 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2570 cardSTATE = MFEMUL_WRITEBL2;
2571 cardWRBL = receivedCmd[1];
0a39986e 2572 break;
7bc95e2e 2573 }
0014cb46 2574 // increment, decrement, restore
d2f487af 2575 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
b03c0f2d 2576 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2577 if (emlCheckValBl(receivedCmd[1])) {
2578 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2579 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2580 break;
2581 }
2582 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2583 if (receivedCmd[0] == 0xC1)
2584 cardSTATE = MFEMUL_INTREG_INC;
2585 if (receivedCmd[0] == 0xC0)
2586 cardSTATE = MFEMUL_INTREG_DEC;
2587 if (receivedCmd[0] == 0xC2)
2588 cardSTATE = MFEMUL_INTREG_REST;
2589 cardWRBL = receivedCmd[1];
0014cb46
M
2590 break;
2591 }
0014cb46 2592 // transfer
d2f487af 2593 if (receivedCmd[0] == 0xB0) {
b03c0f2d 2594 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
0014cb46
M
2595 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2596 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2597 else
2598 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2599 break;
2600 }
9ca155ba 2601 // halt
d2f487af 2602 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
9ca155ba 2603 LED_B_OFF();
0a39986e 2604 LED_C_OFF();
0014cb46
M
2605 cardSTATE = MFEMUL_HALTED;
2606 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
a501c82b 2607 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2608 break;
9ca155ba 2609 }
d2f487af 2610 // RATS
2611 if (receivedCmd[0] == 0xe0) {//RATS
8f51ddb0
M
2612 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2613 break;
2614 }
d2f487af 2615 // command not allowed
2616 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2617 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2618 break;
8f51ddb0
M
2619 }
2620 case MFEMUL_WRITEBL2:{
2621 if (len == 18){
2622 mf_crypto1_decrypt(pcs, receivedCmd, len);
2623 emlSetMem(receivedCmd, cardWRBL, 1);
2624 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2625 cardSTATE = MFEMUL_WORK;
51969283 2626 } else {
0014cb46 2627 cardSTATE_TO_IDLE();
a501c82b 2628 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2629 }
8f51ddb0 2630 break;
50193c1e 2631 }
0014cb46
M
2632
2633 case MFEMUL_INTREG_INC:{
2634 mf_crypto1_decrypt(pcs, receivedCmd, len);
2635 memcpy(&ans, receivedCmd, 4);
2636 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2637 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2638 cardSTATE_TO_IDLE();
2639 break;
7bc95e2e 2640 }
a501c82b 2641 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2642 cardINTREG = cardINTREG + ans;
2643 cardSTATE = MFEMUL_WORK;
2644 break;
2645 }
2646 case MFEMUL_INTREG_DEC:{
2647 mf_crypto1_decrypt(pcs, receivedCmd, len);
2648 memcpy(&ans, receivedCmd, 4);
2649 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2650 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2651 cardSTATE_TO_IDLE();
2652 break;
2653 }
a501c82b 2654 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2655 cardINTREG = cardINTREG - ans;
2656 cardSTATE = MFEMUL_WORK;
2657 break;
2658 }
2659 case MFEMUL_INTREG_REST:{
2660 mf_crypto1_decrypt(pcs, receivedCmd, len);
2661 memcpy(&ans, receivedCmd, 4);
2662 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2663 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2664 cardSTATE_TO_IDLE();
2665 break;
2666 }
a501c82b 2667 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2668 cardSTATE = MFEMUL_WORK;
2669 break;
2670 }
50193c1e 2671 }
50193c1e
M
2672 }
2673
9ca155ba
M
2674 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2675 LEDsoff();
2676
d2f487af 2677 if(flags & FLAG_INTERACTIVE)// Interactive mode flag, means we need to send ACK
2678 {
2679 //May just aswell send the collected ar_nr in the response aswell
2680 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,0,0,&ar_nr_responses,ar_nr_collected*4*4);
2681 }
d714d3ef 2682
d2f487af 2683 if(flags & FLAG_NR_AR_ATTACK)
2684 {
7bc95e2e 2685 if(ar_nr_collected > 1) {
d2f487af 2686 Dbprintf("Collected two pairs of AR/NR which can be used to extract keys from reader:");
d714d3ef 2687 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
d2f487af 2688 ar_nr_responses[0], // UID
2689 ar_nr_responses[1], //NT
2690 ar_nr_responses[2], //AR1
2691 ar_nr_responses[3], //NR1
2692 ar_nr_responses[6], //AR2
2693 ar_nr_responses[7] //NR2
2694 );
7bc95e2e 2695 } else {
d2f487af 2696 Dbprintf("Failed to obtain two AR/NR pairs!");
7bc95e2e 2697 if(ar_nr_collected >0) {
d714d3ef 2698 Dbprintf("Only got these: UID=%08x, nonce=%08x, AR1=%08x, NR1=%08x",
d2f487af 2699 ar_nr_responses[0], // UID
2700 ar_nr_responses[1], //NT
2701 ar_nr_responses[2], //AR1
2702 ar_nr_responses[3] //NR1
2703 );
2704 }
2705 }
2706 }
0014cb46 2707 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, traceLen);
15c4dc5a 2708}
b62a5a84 2709
d2f487af 2710
2711
b62a5a84
M
2712//-----------------------------------------------------------------------------
2713// MIFARE sniffer.
2714//
2715//-----------------------------------------------------------------------------
5cd9ec01
M
2716void RAMFUNC SniffMifare(uint8_t param) {
2717 // param:
2718 // bit 0 - trigger from first card answer
2719 // bit 1 - trigger from first reader 7-bit request
39864b0b
M
2720
2721 // C(red) A(yellow) B(green)
b62a5a84
M
2722 LEDsoff();
2723 // init trace buffer
991f13f2 2724 iso14a_clear_trace();
2725 iso14a_set_tracing(TRUE);
b62a5a84 2726
b62a5a84
M
2727 // The command (reader -> tag) that we're receiving.
2728 // The length of a received command will in most cases be no more than 18 bytes.
2729 // So 32 should be enough!
2730 uint8_t *receivedCmd = (((uint8_t *)BigBuf) + RECV_CMD_OFFSET);
a501c82b 2731 uint8_t *receivedCmdPar = ((uint8_t *)BigBuf) + RECV_CMD_PAR_OFFSET;
b62a5a84 2732 // The response (tag -> reader) that we're receiving.
a501c82b 2733 uint8_t *receivedResponse = (((uint8_t *)BigBuf) + RECV_RESP_OFFSET);
2734 uint8_t *receivedResponsePar = ((uint8_t *)BigBuf) + RECV_RESP_PAR_OFFSET;
2735
b62a5a84
M
2736 // As we receive stuff, we copy it from receivedCmd or receivedResponse
2737 // into trace, along with its length and other annotations.
2738 //uint8_t *trace = (uint8_t *)BigBuf;
2739
2740 // The DMA buffer, used to stream samples from the FPGA
7bc95e2e 2741 uint8_t *dmaBuf = ((uint8_t *)BigBuf) + DMA_BUFFER_OFFSET;
2742 uint8_t *data = dmaBuf;
2743 uint8_t previous_data = 0;
5cd9ec01
M
2744 int maxDataLen = 0;
2745 int dataLen = 0;
7bc95e2e 2746 bool ReaderIsActive = FALSE;
2747 bool TagIsActive = FALSE;
2748
2749 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
b62a5a84
M
2750
2751 // Set up the demodulator for tag -> reader responses.
a501c82b 2752 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
2753
2754 // Set up the demodulator for the reader -> tag commands
a501c82b 2755 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
2756
2757 // Setup for the DMA.
7bc95e2e 2758 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 2759
b62a5a84 2760 LED_D_OFF();
39864b0b
M
2761
2762 // init sniffer
2763 MfSniffInit();
b62a5a84 2764
b62a5a84 2765 // And now we loop, receiving samples.
7bc95e2e 2766 for(uint32_t sniffCounter = 0; TRUE; ) {
2767
5cd9ec01
M
2768 if(BUTTON_PRESS()) {
2769 DbpString("cancelled by button");
7bc95e2e 2770 break;
5cd9ec01
M
2771 }
2772
b62a5a84
M
2773 LED_A_ON();
2774 WDT_HIT();
39864b0b 2775
7bc95e2e 2776 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
2777 // check if a transaction is completed (timeout after 2000ms).
2778 // if yes, stop the DMA transfer and send what we have so far to the client
2779 if (MfSniffSend(2000)) {
2780 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2781 sniffCounter = 0;
2782 data = dmaBuf;
2783 maxDataLen = 0;
2784 ReaderIsActive = FALSE;
2785 TagIsActive = FALSE;
2786 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 2787 }
39864b0b 2788 }
7bc95e2e 2789
2790 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
2791 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
2792 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2793 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2794 } else {
2795 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
5cd9ec01
M
2796 }
2797 // test for length of buffer
7bc95e2e 2798 if(dataLen > maxDataLen) { // we are more behind than ever...
2799 maxDataLen = dataLen;
5cd9ec01
M
2800 if(dataLen > 400) {
2801 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 2802 break;
b62a5a84
M
2803 }
2804 }
5cd9ec01 2805 if(dataLen < 1) continue;
b62a5a84 2806
7bc95e2e 2807 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
2808 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2809 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2810 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
55acbb2a 2811 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
2812 }
2813 // secondary buffer sets as primary, secondary buffer was stopped
2814 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2815 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
2816 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2817 }
5cd9ec01
M
2818
2819 LED_A_OFF();
b62a5a84 2820
7bc95e2e 2821 if (sniffCounter & 0x01) {
b62a5a84 2822
7bc95e2e 2823 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
2824 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2825 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
2826 LED_C_INV();
a501c82b 2827 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 2828
7bc95e2e 2829 /* And ready to receive another command. */
2830 UartReset();
2831
2832 /* And also reset the demod code */
2833 DemodReset();
2834 }
2835 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2836 }
2837
2838 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
2839 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2840 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
2841 LED_C_INV();
b62a5a84 2842
a501c82b 2843 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 2844
7bc95e2e 2845 // And ready to receive another response.
2846 DemodReset();
2847 }
2848 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2849 }
b62a5a84
M
2850 }
2851
7bc95e2e 2852 previous_data = *data;
2853 sniffCounter++;
5cd9ec01 2854 data++;
d714d3ef 2855 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01 2856 data = dmaBuf;
b62a5a84 2857 }
7bc95e2e 2858
b62a5a84
M
2859 } // main cycle
2860
2861 DbpString("COMMAND FINISHED");
2862
55acbb2a 2863 FpgaDisableSscDma();
39864b0b
M
2864 MfSniffEnd();
2865
7bc95e2e 2866 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
b62a5a84 2867 LEDsoff();
3803d529 2868}
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