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15c4dc5a 1//-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
e30c654b 13#include "proxmark3.h"
15c4dc5a 14#include "apps.h"
f7e3ed82 15#include "util.h"
9ab7a6c7 16#include "string.h"
902cb3c0 17#include "cmd.h"
15c4dc5a 18#include "iso14443crc.h"
534983d7 19#include "iso14443a.h"
20f9a2a1
M
20#include "crapto1.h"
21#include "mifareutil.h"
3000dc4e 22#include "BigBuf.h"
c872d8c1 23#include "protocols.h"
24
534983d7 25static uint32_t iso14a_timeout;
1e262141 26int rsamples = 0;
1e262141 27uint8_t trigger = 0;
b0127e65 28// the block number for the ISO14443-4 PCB
29static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 30
7bc95e2e 31//
32// ISO14443 timing:
33//
34// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
35#define REQUEST_GUARD_TIME (7000/16 + 1)
36// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
37#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
38// bool LastCommandWasRequest = FALSE;
39
40//
41// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
42//
d714d3ef 43// When the PM acts as reader and is receiving tag data, it takes
44// 3 ticks delay in the AD converter
45// 16 ticks until the modulation detector completes and sets curbit
46// 8 ticks until bit_to_arm is assigned from curbit
47// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 48// 4*16 ticks until we measure the time
49// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 50#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 51
52// When the PM acts as a reader and is sending, it takes
53// 4*16 ticks until we can write data to the sending hold register
54// 8*16 ticks until the SHR is transferred to the Sending Shift Register
55// 8 ticks until the first transfer starts
56// 8 ticks later the FPGA samples the data
57// 1 tick to assign mod_sig_coil
58#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
59
60// When the PM acts as tag and is receiving it takes
d714d3ef 61// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 62// 3 ticks for the A/D conversion,
63// 8 ticks on average until the start of the SSC transfer,
64// 8 ticks until the SSC samples the first data
65// 7*16 ticks to complete the transfer from FPGA to ARM
66// 8 ticks until the next ssp_clk rising edge
d714d3ef 67// 4*16 ticks until we measure the time
7bc95e2e 68// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 69#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
7bc95e2e 70
71// The FPGA will report its internal sending delay in
72uint16_t FpgaSendQueueDelay;
73// the 5 first bits are the number of bits buffered in mod_sig_buf
74// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
75#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
76
77// When the PM acts as tag and is sending, it takes
d714d3ef 78// 4*16 ticks until we can write data to the sending hold register
7bc95e2e 79// 8*16 ticks until the SHR is transferred to the Sending Shift Register
80// 8 ticks until the first transfer starts
81// 8 ticks later the FPGA samples the data
82// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
83// + 1 tick to assign mod_sig_coil
d714d3ef 84#define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
7bc95e2e 85
86// When the PM acts as sniffer and is receiving tag data, it takes
87// 3 ticks A/D conversion
d714d3ef 88// 14 ticks to complete the modulation detection
89// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 90// + the delays in transferring data - which is the same for
91// sniffing reader and tag data and therefore not relevant
d714d3ef 92#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
7bc95e2e 93
d714d3ef 94// When the PM acts as sniffer and is receiving reader data, it takes
95// 2 ticks delay in analogue RF receiver (for the falling edge of the
96// start bit, which marks the start of the communication)
7bc95e2e 97// 3 ticks A/D conversion
d714d3ef 98// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 99// + the delays in transferring data - which is the same for
100// sniffing reader and tag data and therefore not relevant
d714d3ef 101#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 102
103//variables used for timing purposes:
104//these are in ssp_clk cycles:
6a1f2d82 105static uint32_t NextTransferTime;
106static uint32_t LastTimeProxToAirStart;
107static uint32_t LastProxToAirDuration;
7bc95e2e 108
109
110
8f51ddb0 111// CARD TO READER - manchester
72934aa3 112// Sequence D: 11110000 modulation with subcarrier during first half
113// Sequence E: 00001111 modulation with subcarrier during second half
114// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 115// READER TO CARD - miller
72934aa3 116// Sequence X: 00001100 drop after half a period
117// Sequence Y: 00000000 no drop
118// Sequence Z: 11000000 drop at start
119#define SEC_D 0xf0
120#define SEC_E 0x0f
121#define SEC_F 0x00
122#define SEC_X 0x0c
123#define SEC_Y 0x00
124#define SEC_Z 0xc0
15c4dc5a 125
1e262141 126const uint8_t OddByteParity[256] = {
15c4dc5a 127 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
128 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
129 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
130 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
131 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
132 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
133 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
134 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
135 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
136 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
137 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
138 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
139 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
140 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
141 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
142 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
143};
144
19a700a8 145
902cb3c0 146void iso14a_set_trigger(bool enable) {
534983d7 147 trigger = enable;
148}
149
d19929cb 150
b0127e65 151void iso14a_set_timeout(uint32_t timeout) {
152 iso14a_timeout = timeout;
19a700a8 153 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
b0127e65 154}
8556b852 155
19a700a8 156
157void iso14a_set_ATS_timeout(uint8_t *ats) {
158
159 uint8_t tb1;
160 uint8_t fwi;
161 uint32_t fwt;
162
163 if (ats[0] > 1) { // there is a format byte T0
164 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
165 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
166 tb1 = ats[3];
167 } else {
168 tb1 = ats[2];
169 }
170 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
171 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
172
173 iso14a_set_timeout(fwt/(8*16));
174 }
175 }
176}
177
178
15c4dc5a 179//-----------------------------------------------------------------------------
180// Generate the parity value for a byte sequence
e30c654b 181//
15c4dc5a 182//-----------------------------------------------------------------------------
20f9a2a1
M
183byte_t oddparity (const byte_t bt)
184{
5f6d6c90 185 return OddByteParity[bt];
20f9a2a1
M
186}
187
6a1f2d82 188void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
15c4dc5a 189{
6a1f2d82 190 uint16_t paritybit_cnt = 0;
191 uint16_t paritybyte_cnt = 0;
192 uint8_t parityBits = 0;
193
194 for (uint16_t i = 0; i < iLen; i++) {
195 // Generate the parity bits
196 parityBits |= ((OddByteParity[pbtCmd[i]]) << (7-paritybit_cnt));
197 if (paritybit_cnt == 7) {
198 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
199 parityBits = 0; // and advance to next Parity Byte
200 paritybyte_cnt++;
201 paritybit_cnt = 0;
202 } else {
203 paritybit_cnt++;
204 }
5f6d6c90 205 }
6a1f2d82 206
207 // save remaining parity bits
208 par[paritybyte_cnt] = parityBits;
209
15c4dc5a 210}
211
534983d7 212void AppendCrc14443a(uint8_t* data, int len)
15c4dc5a 213{
5f6d6c90 214 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 215}
216
48ece4a7 217void AppendCrc14443b(uint8_t* data, int len)
218{
219 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
220}
221
222
7bc95e2e 223//=============================================================================
224// ISO 14443 Type A - Miller decoder
225//=============================================================================
226// Basics:
227// This decoder is used when the PM3 acts as a tag.
228// The reader will generate "pauses" by temporarily switching of the field.
229// At the PM3 antenna we will therefore measure a modulated antenna voltage.
230// The FPGA does a comparison with a threshold and would deliver e.g.:
231// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
232// The Miller decoder needs to identify the following sequences:
233// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
234// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
235// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
236// Note 1: the bitstream may start at any time. We therefore need to sync.
237// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 238//-----------------------------------------------------------------------------
b62a5a84 239static tUart Uart;
15c4dc5a 240
d7aa3739 241// Lookup-Table to decide if 4 raw bits are a modulation.
05ddb52c 242// We accept the following:
243// 0001 - a 3 tick wide pause
244// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
245// 0111 - a 2 tick wide pause shifted left
246// 1001 - a 2 tick wide pause shifted right
d7aa3739 247const bool Mod_Miller_LUT[] = {
05ddb52c 248 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
249 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
d7aa3739 250};
05ddb52c 251#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
252#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 253
7bc95e2e 254void UartReset()
15c4dc5a 255{
7bc95e2e 256 Uart.state = STATE_UNSYNCD;
257 Uart.bitCount = 0;
258 Uart.len = 0; // number of decoded data bytes
6a1f2d82 259 Uart.parityLen = 0; // number of decoded parity bytes
7bc95e2e 260 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
6a1f2d82 261 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 262 Uart.startTime = 0;
263 Uart.endTime = 0;
264}
15c4dc5a 265
6a1f2d82 266void UartInit(uint8_t *data, uint8_t *parity)
267{
268 Uart.output = data;
269 Uart.parity = parity;
05ddb52c 270 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
6a1f2d82 271 UartReset();
272}
d714d3ef 273
7bc95e2e 274// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
275static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
276{
15c4dc5a 277
ef00343c 278 Uart.fourBits = (Uart.fourBits << 8) | bit;
7bc95e2e 279
0c8d25eb 280 if (Uart.state == STATE_UNSYNCD) { // not yet synced
3fe4ff4f 281
ef00343c 282 Uart.syncBit = 9999; // not set
05ddb52c 283 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
284 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
285 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
286 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
48ece4a7 287 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
288 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
05ddb52c 289 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
290 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
291 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
292 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
293 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
294 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
295 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
296 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
297
ef00343c 298 if (Uart.syncBit != 9999) { // found a sync bit
299 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
300 Uart.startTime -= Uart.syncBit;
301 Uart.endTime = Uart.startTime;
302 Uart.state = STATE_START_OF_COMMUNICATION;
7bc95e2e 303 }
15c4dc5a 304
7bc95e2e 305 } else {
15c4dc5a 306
ef00343c 307 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
308 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
d7aa3739 309 UartReset();
d7aa3739 310 } else { // Modulation in first half = Sequence Z = logic "0"
7bc95e2e 311 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
312 UartReset();
7bc95e2e 313 } else {
314 Uart.bitCount++;
315 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
316 Uart.state = STATE_MILLER_Z;
317 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
318 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
319 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
320 Uart.parityBits <<= 1; // make room for the parity bit
321 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
322 Uart.bitCount = 0;
323 Uart.shiftReg = 0;
6a1f2d82 324 if((Uart.len&0x0007) == 0) { // every 8 data bytes
325 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
326 Uart.parityBits = 0;
327 }
15c4dc5a 328 }
7bc95e2e 329 }
d7aa3739 330 }
331 } else {
ef00343c 332 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 333 Uart.bitCount++;
334 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
335 Uart.state = STATE_MILLER_X;
336 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
337 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
338 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
339 Uart.parityBits <<= 1; // make room for the new parity bit
340 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
341 Uart.bitCount = 0;
342 Uart.shiftReg = 0;
6a1f2d82 343 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
344 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
345 Uart.parityBits = 0;
346 }
7bc95e2e 347 }
d7aa3739 348 } else { // no modulation in both halves - Sequence Y
7bc95e2e 349 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
15c4dc5a 350 Uart.state = STATE_UNSYNCD;
6a1f2d82 351 Uart.bitCount--; // last "0" was part of EOC sequence
352 Uart.shiftReg <<= 1; // drop it
353 if(Uart.bitCount > 0) { // if we decoded some bits
354 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
355 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
356 Uart.parityBits <<= 1; // add a (void) parity bit
357 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
358 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
359 return TRUE;
360 } else if (Uart.len & 0x0007) { // there are some parity bits to store
361 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
362 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 363 }
364 if (Uart.len) {
6a1f2d82 365 return TRUE; // we are finished with decoding the raw data sequence
52bfb955 366 } else {
0c8d25eb 367 UartReset(); // Nothing received - start over
7bc95e2e 368 }
15c4dc5a 369 }
7bc95e2e 370 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
371 UartReset();
7bc95e2e 372 } else { // a logic "0"
373 Uart.bitCount++;
374 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
375 Uart.state = STATE_MILLER_Y;
376 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
377 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
378 Uart.parityBits <<= 1; // make room for the parity bit
379 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
380 Uart.bitCount = 0;
381 Uart.shiftReg = 0;
6a1f2d82 382 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
383 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
384 Uart.parityBits = 0;
385 }
15c4dc5a 386 }
387 }
d7aa3739 388 }
15c4dc5a 389 }
7bc95e2e 390
391 }
15c4dc5a 392
7bc95e2e 393 return FALSE; // not finished yet, need more data
15c4dc5a 394}
395
7bc95e2e 396
397
15c4dc5a 398//=============================================================================
e691fc45 399// ISO 14443 Type A - Manchester decoder
15c4dc5a 400//=============================================================================
e691fc45 401// Basics:
7bc95e2e 402// This decoder is used when the PM3 acts as a reader.
e691fc45 403// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
404// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
405// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
406// The Manchester decoder needs to identify the following sequences:
407// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
408// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
409// 8 ticks unmodulated: Sequence F = end of communication
410// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 411// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 412// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 413static tDemod Demod;
15c4dc5a 414
d7aa3739 415// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 416// We accept three or four "1" in any position
7bc95e2e 417const bool Mod_Manchester_LUT[] = {
d7aa3739 418 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
d714d3ef 419 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
7bc95e2e 420};
421
422#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
423#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 424
2f2d9fc5 425
7bc95e2e 426void DemodReset()
e691fc45 427{
7bc95e2e 428 Demod.state = DEMOD_UNSYNCD;
429 Demod.len = 0; // number of decoded data bytes
6a1f2d82 430 Demod.parityLen = 0;
7bc95e2e 431 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
432 Demod.parityBits = 0; //
433 Demod.collisionPos = 0; // Position of collision bit
434 Demod.twoBits = 0xffff; // buffer for 2 Bits
435 Demod.highCnt = 0;
436 Demod.startTime = 0;
437 Demod.endTime = 0;
e691fc45 438}
15c4dc5a 439
6a1f2d82 440void DemodInit(uint8_t *data, uint8_t *parity)
441{
442 Demod.output = data;
443 Demod.parity = parity;
444 DemodReset();
445}
446
7bc95e2e 447// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
448static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
e691fc45 449{
7bc95e2e 450
451 Demod.twoBits = (Demod.twoBits << 8) | bit;
e691fc45 452
7bc95e2e 453 if (Demod.state == DEMOD_UNSYNCD) {
454
455 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
456 if (Demod.twoBits == 0x0000) {
457 Demod.highCnt++;
458 } else {
459 Demod.highCnt = 0;
460 }
461 } else {
462 Demod.syncBit = 0xFFFF; // not set
463 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
464 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
465 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
466 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
467 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
468 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
469 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
470 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 471 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 472 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
473 Demod.startTime -= Demod.syncBit;
474 Demod.bitCount = offset; // number of decoded data bits
e691fc45 475 Demod.state = DEMOD_MANCHESTER_DATA;
2f2d9fc5 476 }
7bc95e2e 477 }
15c4dc5a 478
7bc95e2e 479 } else {
15c4dc5a 480
7bc95e2e 481 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
482 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 483 if (!Demod.collisionPos) {
484 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
485 }
486 } // modulation in first half only - Sequence D = 1
7bc95e2e 487 Demod.bitCount++;
488 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
489 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 490 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 491 Demod.parityBits <<= 1; // make room for the parity bit
e691fc45 492 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
493 Demod.bitCount = 0;
494 Demod.shiftReg = 0;
6a1f2d82 495 if((Demod.len&0x0007) == 0) { // every 8 data bytes
496 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
497 Demod.parityBits = 0;
498 }
15c4dc5a 499 }
7bc95e2e 500 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
501 } else { // no modulation in first half
502 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 503 Demod.bitCount++;
7bc95e2e 504 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
e691fc45 505 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 506 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
7bc95e2e 507 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 508 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
509 Demod.bitCount = 0;
510 Demod.shiftReg = 0;
6a1f2d82 511 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
512 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
513 Demod.parityBits = 0;
514 }
15c4dc5a 515 }
7bc95e2e 516 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
e691fc45 517 } else { // no modulation in both halves - End of communication
6a1f2d82 518 if(Demod.bitCount > 0) { // there are some remaining data bits
519 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
520 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
521 Demod.parityBits <<= 1; // add a (void) parity bit
522 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
523 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
524 return TRUE;
525 } else if (Demod.len & 0x0007) { // there are some parity bits to store
526 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
527 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 528 }
529 if (Demod.len) {
d7aa3739 530 return TRUE; // we are finished with decoding the raw data sequence
531 } else { // nothing received. Start over
532 DemodReset();
e691fc45 533 }
15c4dc5a 534 }
7bc95e2e 535 }
e691fc45 536
537 }
15c4dc5a 538
e691fc45 539 return FALSE; // not finished yet, need more data
15c4dc5a 540}
541
542//=============================================================================
543// Finally, a `sniffer' for ISO 14443 Type A
544// Both sides of communication!
545//=============================================================================
546
547//-----------------------------------------------------------------------------
548// Record the sequence of commands sent by the reader to the tag, with
549// triggering so that we start recording at the point that the tag is moved
550// near the reader.
551//-----------------------------------------------------------------------------
5cd9ec01
M
552void RAMFUNC SnoopIso14443a(uint8_t param) {
553 // param:
554 // bit 0 - trigger from first card answer
555 // bit 1 - trigger from first reader 7-bit request
556
557 LEDsoff();
5cd9ec01 558
09ffd16e 559 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
560
f71f4deb 561 // Allocate memory from BigBuf for some buffers
562 // free all previous allocations first
563 BigBuf_free();
564
5cd9ec01 565 // The command (reader -> tag) that we're receiving.
f71f4deb 566 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
567 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6a1f2d82 568
5cd9ec01 569 // The response (tag -> reader) that we're receiving.
f71f4deb 570 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
571 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
5cd9ec01
M
572
573 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 574 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
575
576 // init trace buffer
3000dc4e
MHS
577 clear_trace();
578 set_tracing(TRUE);
f71f4deb 579
7bc95e2e 580 uint8_t *data = dmaBuf;
581 uint8_t previous_data = 0;
5cd9ec01
M
582 int maxDataLen = 0;
583 int dataLen = 0;
7bc95e2e 584 bool TagIsActive = FALSE;
585 bool ReaderIsActive = FALSE;
586
5cd9ec01 587 // Set up the demodulator for tag -> reader responses.
6a1f2d82 588 DemodInit(receivedResponse, receivedResponsePar);
589
5cd9ec01 590 // Set up the demodulator for the reader -> tag commands
6a1f2d82 591 UartInit(receivedCmd, receivedCmdPar);
592
7bc95e2e 593 // Setup and start DMA.
5cd9ec01 594 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
7bc95e2e 595
09ffd16e 596 // We won't start recording the frames that we acquire until we trigger;
597 // a good trigger condition to get started is probably when we see a
598 // response from the tag.
599 // triggered == FALSE -- to wait first for card
600 bool triggered = !(param & 0x03);
601
5cd9ec01 602 // And now we loop, receiving samples.
7bc95e2e 603 for(uint32_t rsamples = 0; TRUE; ) {
604
5cd9ec01
M
605 if(BUTTON_PRESS()) {
606 DbpString("cancelled by button");
7bc95e2e 607 break;
5cd9ec01 608 }
15c4dc5a 609
5cd9ec01
M
610 LED_A_ON();
611 WDT_HIT();
15c4dc5a 612
5cd9ec01
M
613 int register readBufDataP = data - dmaBuf;
614 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
615 if (readBufDataP <= dmaBufDataP){
616 dataLen = dmaBufDataP - readBufDataP;
617 } else {
7bc95e2e 618 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
619 }
620 // test for length of buffer
621 if(dataLen > maxDataLen) {
622 maxDataLen = dataLen;
f71f4deb 623 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 624 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
625 break;
5cd9ec01
M
626 }
627 }
628 if(dataLen < 1) continue;
629
630 // primary buffer was stopped( <-- we lost data!
631 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
632 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
633 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 634 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
635 }
636 // secondary buffer sets as primary, secondary buffer was stopped
637 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
638 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
639 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
640 }
641
642 LED_A_OFF();
7bc95e2e 643
644 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 645
7bc95e2e 646 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
647 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
648 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
649 LED_C_ON();
5cd9ec01 650
7bc95e2e 651 // check - if there is a short 7bit request from reader
652 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
5cd9ec01 653
7bc95e2e 654 if(triggered) {
6a1f2d82 655 if (!LogTrace(receivedCmd,
656 Uart.len,
657 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
658 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
659 Uart.parity,
660 TRUE)) break;
7bc95e2e 661 }
662 /* And ready to receive another command. */
48ece4a7 663 UartReset();
7bc95e2e 664 /* And also reset the demod code, which might have been */
665 /* false-triggered by the commands from the reader. */
666 DemodReset();
667 LED_B_OFF();
668 }
669 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 670 }
3be2a5ae 671
7bc95e2e 672 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
673 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
674 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
675 LED_B_ON();
5cd9ec01 676
6a1f2d82 677 if (!LogTrace(receivedResponse,
678 Demod.len,
679 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
680 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
681 Demod.parity,
682 FALSE)) break;
5cd9ec01 683
7bc95e2e 684 if ((!triggered) && (param & 0x01)) triggered = TRUE;
5cd9ec01 685
7bc95e2e 686 // And ready to receive another response.
687 DemodReset();
48ece4a7 688 // And reset the Miller decoder including itS (now outdated) input buffer
689 UartInit(receivedCmd, receivedCmdPar);
690
7bc95e2e 691 LED_C_OFF();
692 }
693 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
694 }
5cd9ec01
M
695 }
696
7bc95e2e 697 previous_data = *data;
698 rsamples++;
5cd9ec01 699 data++;
d714d3ef 700 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
701 data = dmaBuf;
702 }
703 } // main cycle
704
705 DbpString("COMMAND FINISHED");
15c4dc5a 706
7bc95e2e 707 FpgaDisableSscDma();
708 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
3000dc4e 709 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
5cd9ec01 710 LEDsoff();
15c4dc5a 711}
712
15c4dc5a 713//-----------------------------------------------------------------------------
714// Prepare tag messages
715//-----------------------------------------------------------------------------
6a1f2d82 716static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
15c4dc5a 717{
8f51ddb0 718 ToSendReset();
15c4dc5a 719
720 // Correction bit, might be removed when not needed
721 ToSendStuffBit(0);
722 ToSendStuffBit(0);
723 ToSendStuffBit(0);
724 ToSendStuffBit(0);
725 ToSendStuffBit(1); // 1
726 ToSendStuffBit(0);
727 ToSendStuffBit(0);
728 ToSendStuffBit(0);
8f51ddb0 729
15c4dc5a 730 // Send startbit
72934aa3 731 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 732 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 733
6a1f2d82 734 for(uint16_t i = 0; i < len; i++) {
8f51ddb0 735 uint8_t b = cmd[i];
15c4dc5a 736
737 // Data bits
6a1f2d82 738 for(uint16_t j = 0; j < 8; j++) {
15c4dc5a 739 if(b & 1) {
72934aa3 740 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 741 } else {
72934aa3 742 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
743 }
744 b >>= 1;
745 }
15c4dc5a 746
0014cb46 747 // Get the parity bit
6a1f2d82 748 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 749 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 750 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 751 } else {
72934aa3 752 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 753 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 754 }
8f51ddb0 755 }
15c4dc5a 756
8f51ddb0
M
757 // Send stopbit
758 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 759
8f51ddb0
M
760 // Convert from last byte pos to length
761 ToSendMax++;
8f51ddb0
M
762}
763
6a1f2d82 764static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len)
765{
766 uint8_t par[MAX_PARITY_SIZE];
767
768 GetParity(cmd, len, par);
769 CodeIso14443aAsTagPar(cmd, len, par);
15c4dc5a 770}
771
15c4dc5a 772
8f51ddb0
M
773static void Code4bitAnswerAsTag(uint8_t cmd)
774{
775 int i;
776
5f6d6c90 777 ToSendReset();
8f51ddb0
M
778
779 // Correction bit, might be removed when not needed
780 ToSendStuffBit(0);
781 ToSendStuffBit(0);
782 ToSendStuffBit(0);
783 ToSendStuffBit(0);
784 ToSendStuffBit(1); // 1
785 ToSendStuffBit(0);
786 ToSendStuffBit(0);
787 ToSendStuffBit(0);
788
789 // Send startbit
790 ToSend[++ToSendMax] = SEC_D;
791
792 uint8_t b = cmd;
793 for(i = 0; i < 4; i++) {
794 if(b & 1) {
795 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 796 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
797 } else {
798 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 799 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
800 }
801 b >>= 1;
802 }
803
804 // Send stopbit
805 ToSend[++ToSendMax] = SEC_F;
806
5f6d6c90 807 // Convert from last byte pos to length
808 ToSendMax++;
15c4dc5a 809}
810
811//-----------------------------------------------------------------------------
812// Wait for commands from reader
813// Stop when button is pressed
814// Or return TRUE when command is captured
815//-----------------------------------------------------------------------------
6a1f2d82 816static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
15c4dc5a 817{
818 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
819 // only, since we are receiving, not transmitting).
820 // Signal field is off with the appropriate LED
821 LED_D_OFF();
822 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
823
824 // Now run a `software UART' on the stream of incoming samples.
6a1f2d82 825 UartInit(received, parity);
7bc95e2e 826
827 // clear RXRDY:
828 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
15c4dc5a 829
830 for(;;) {
831 WDT_HIT();
832
833 if(BUTTON_PRESS()) return FALSE;
7bc95e2e 834
15c4dc5a 835 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
7bc95e2e 836 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
837 if(MillerDecoding(b, 0)) {
838 *len = Uart.len;
15c4dc5a 839 return TRUE;
840 }
7bc95e2e 841 }
15c4dc5a 842 }
843}
28afbd2b 844
6a1f2d82 845static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
7bc95e2e 846int EmSend4bitEx(uint8_t resp, bool correctionNeeded);
28afbd2b 847int EmSend4bit(uint8_t resp);
6a1f2d82 848int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par);
849int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded);
850int EmSendCmd(uint8_t *resp, uint16_t respLen);
851int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
852bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
853 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity);
15c4dc5a 854
117d9ec2 855static uint8_t* free_buffer_pointer;
ce02f6f9 856
857typedef struct {
858 uint8_t* response;
859 size_t response_n;
860 uint8_t* modulation;
861 size_t modulation_n;
7bc95e2e 862 uint32_t ProxToAirDuration;
ce02f6f9 863} tag_response_info_t;
864
ce02f6f9 865bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 866 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 867 // This will need the following byte array for a modulation sequence
868 // 144 data bits (18 * 8)
869 // 18 parity bits
870 // 2 Start and stop
871 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
872 // 1 just for the case
873 // ----------- +
874 // 166 bytes, since every bit that needs to be send costs us a byte
875 //
f71f4deb 876
877
ce02f6f9 878 // Prepare the tag modulation bits from the message
879 CodeIso14443aAsTag(response_info->response,response_info->response_n);
880
881 // Make sure we do not exceed the free buffer space
882 if (ToSendMax > max_buffer_size) {
883 Dbprintf("Out of memory, when modulating bits for tag answer:");
884 Dbhexdump(response_info->response_n,response_info->response,false);
885 return false;
886 }
887
888 // Copy the byte array, used for this modulation to the buffer position
889 memcpy(response_info->modulation,ToSend,ToSendMax);
890
7bc95e2e 891 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
ce02f6f9 892 response_info->modulation_n = ToSendMax;
7bc95e2e 893 response_info->ProxToAirDuration = LastProxToAirDuration;
ce02f6f9 894
895 return true;
896}
897
f71f4deb 898
899// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
900// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
901// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
902// -> need 273 bytes buffer
903#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
904
ce02f6f9 905bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
906 // Retrieve and store the current buffer index
907 response_info->modulation = free_buffer_pointer;
908
909 // Determine the maximum size we can use from our buffer
f71f4deb 910 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
ce02f6f9 911
912 // Forward the prepare tag modulation function to the inner function
f71f4deb 913 if (prepare_tag_modulation(response_info, max_buffer_size)) {
ce02f6f9 914 // Update the free buffer offset
915 free_buffer_pointer += ToSendMax;
916 return true;
917 } else {
918 return false;
919 }
920}
921
15c4dc5a 922//-----------------------------------------------------------------------------
923// Main loop of simulated tag: receive commands from reader, decide what
924// response to send, and send it.
925//-----------------------------------------------------------------------------
28afbd2b 926void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
15c4dc5a 927{
81cd0474 928 uint8_t sak;
929
930 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
931 uint8_t response1[2];
932
933 switch (tagType) {
934 case 1: { // MIFARE Classic
935 // Says: I am Mifare 1k - original line
936 response1[0] = 0x04;
937 response1[1] = 0x00;
938 sak = 0x08;
939 } break;
940 case 2: { // MIFARE Ultralight
941 // Says: I am a stupid memory tag, no crypto
942 response1[0] = 0x04;
943 response1[1] = 0x00;
944 sak = 0x00;
945 } break;
946 case 3: { // MIFARE DESFire
947 // Says: I am a DESFire tag, ph33r me
948 response1[0] = 0x04;
949 response1[1] = 0x03;
950 sak = 0x20;
951 } break;
952 case 4: { // ISO/IEC 14443-4
953 // Says: I am a javacard (JCOP)
954 response1[0] = 0x04;
955 response1[1] = 0x00;
956 sak = 0x28;
957 } break;
3fe4ff4f 958 case 5: { // MIFARE TNP3XXX
959 // Says: I am a toy
960 response1[0] = 0x01;
961 response1[1] = 0x0f;
962 sak = 0x01;
963 } break;
81cd0474 964 default: {
965 Dbprintf("Error: unkown tagtype (%d)",tagType);
966 return;
967 } break;
968 }
969
970 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 971 uint8_t response2[5] = {0x00};
81cd0474 972
973 // Check if the uid uses the (optional) part
c8b6da22 974 uint8_t response2a[5] = {0x00};
975
81cd0474 976 if (uid_2nd) {
977 response2[0] = 0x88;
978 num_to_bytes(uid_1st,3,response2+1);
979 num_to_bytes(uid_2nd,4,response2a);
980 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
981
982 // Configure the ATQA and SAK accordingly
983 response1[0] |= 0x40;
984 sak |= 0x04;
985 } else {
986 num_to_bytes(uid_1st,4,response2);
987 // Configure the ATQA and SAK accordingly
988 response1[0] &= 0xBF;
989 sak &= 0xFB;
990 }
991
992 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
993 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
994
995 // Prepare the mandatory SAK (for 4 and 7 byte UID)
c8b6da22 996 uint8_t response3[3] = {0x00};
81cd0474 997 response3[0] = sak;
998 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
999
1000 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 1001 uint8_t response3a[3] = {0x00};
81cd0474 1002 response3a[0] = sak & 0xFB;
1003 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1004
254b70a4 1005 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
6a1f2d82 1006 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1007 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
1008 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1009 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1010 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 1011 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1012
7bc95e2e 1013 #define TAG_RESPONSE_COUNT 7
1014 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1015 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1016 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1017 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1018 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1019 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1020 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1021 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1022 };
1023
1024 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1025 // Such a response is less time critical, so we can prepare them on the fly
1026 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1027 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1028 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1029 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1030 tag_response_info_t dynamic_response_info = {
1031 .response = dynamic_response_buffer,
1032 .response_n = 0,
1033 .modulation = dynamic_modulation_buffer,
1034 .modulation_n = 0
1035 };
ce02f6f9 1036
09ffd16e 1037 // We need to listen to the high-frequency, peak-detected path.
1038 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1039
f71f4deb 1040 BigBuf_free_keep_EM();
1041
1042 // allocate buffers:
1043 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1044 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1045 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1046
1047 // clear trace
3000dc4e
MHS
1048 clear_trace();
1049 set_tracing(TRUE);
f71f4deb 1050
7bc95e2e 1051 // Prepare the responses of the anticollision phase
ce02f6f9 1052 // there will be not enough time to do this at the moment the reader sends it REQA
7bc95e2e 1053 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
1054 prepare_allocated_tag_modulation(&responses[i]);
1055 }
15c4dc5a 1056
7bc95e2e 1057 int len = 0;
15c4dc5a 1058
1059 // To control where we are in the protocol
1060 int order = 0;
1061 int lastorder;
1062
1063 // Just to allow some checks
1064 int happened = 0;
1065 int happened2 = 0;
81cd0474 1066 int cmdsRecvd = 0;
15c4dc5a 1067
254b70a4 1068 cmdsRecvd = 0;
7bc95e2e 1069 tag_response_info_t* p_response;
15c4dc5a 1070
254b70a4 1071 LED_A_ON();
1072 for(;;) {
7bc95e2e 1073 // Clean receive command buffer
6a1f2d82 1074 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1075 DbpString("Button press");
254b70a4 1076 break;
1077 }
7bc95e2e 1078
1079 p_response = NULL;
1080
254b70a4 1081 // Okay, look at the command now.
1082 lastorder = order;
1083 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1084 p_response = &responses[0]; order = 1;
254b70a4 1085 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1086 p_response = &responses[0]; order = 6;
254b70a4 1087 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1088 p_response = &responses[1]; order = 2;
6a1f2d82 1089 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1090 p_response = &responses[2]; order = 20;
254b70a4 1091 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1092 p_response = &responses[3]; order = 3;
254b70a4 1093 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1094 p_response = &responses[4]; order = 30;
254b70a4 1095 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
6a1f2d82 1096 EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
7bc95e2e 1097 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
5f6d6c90 1098 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
7bc95e2e 1099 p_response = NULL;
254b70a4 1100 } else if(receivedCmd[0] == 0x50) { // Received a HALT
3fe4ff4f 1101
7bc95e2e 1102 if (tracing) {
6a1f2d82 1103 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1104 }
1105 p_response = NULL;
254b70a4 1106 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
ce02f6f9 1107 p_response = &responses[5]; order = 7;
254b70a4 1108 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
7bc95e2e 1109 if (tagType == 1 || tagType == 2) { // RATS not supported
1110 EmSend4bit(CARD_NACK_NA);
1111 p_response = NULL;
1112 } else {
1113 p_response = &responses[6]; order = 70;
1114 }
6a1f2d82 1115 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
7bc95e2e 1116 if (tracing) {
6a1f2d82 1117 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1118 }
1119 uint32_t nr = bytes_to_num(receivedCmd,4);
1120 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1121 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1122 } else {
1123 // Check for ISO 14443A-4 compliant commands, look at left nibble
1124 switch (receivedCmd[0]) {
1125
1126 case 0x0B:
1127 case 0x0A: { // IBlock (command)
1128 dynamic_response_info.response[0] = receivedCmd[0];
1129 dynamic_response_info.response[1] = 0x00;
1130 dynamic_response_info.response[2] = 0x90;
1131 dynamic_response_info.response[3] = 0x00;
1132 dynamic_response_info.response_n = 4;
1133 } break;
1134
1135 case 0x1A:
1136 case 0x1B: { // Chaining command
1137 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1138 dynamic_response_info.response_n = 2;
1139 } break;
1140
1141 case 0xaa:
1142 case 0xbb: {
1143 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1144 dynamic_response_info.response_n = 2;
1145 } break;
1146
1147 case 0xBA: { //
1148 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1149 dynamic_response_info.response_n = 2;
1150 } break;
1151
1152 case 0xCA:
1153 case 0xC2: { // Readers sends deselect command
1154 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1155 dynamic_response_info.response_n = 2;
1156 } break;
1157
1158 default: {
1159 // Never seen this command before
1160 if (tracing) {
6a1f2d82 1161 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1162 }
1163 Dbprintf("Received unknown command (len=%d):",len);
1164 Dbhexdump(len,receivedCmd,false);
1165 // Do not respond
1166 dynamic_response_info.response_n = 0;
1167 } break;
1168 }
ce02f6f9 1169
7bc95e2e 1170 if (dynamic_response_info.response_n > 0) {
1171 // Copy the CID from the reader query
1172 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1173
7bc95e2e 1174 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1175 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1176 dynamic_response_info.response_n += 2;
ce02f6f9 1177
7bc95e2e 1178 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1179 Dbprintf("Error preparing tag response");
1180 if (tracing) {
6a1f2d82 1181 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 1182 }
1183 break;
1184 }
1185 p_response = &dynamic_response_info;
1186 }
81cd0474 1187 }
15c4dc5a 1188
1189 // Count number of wakeups received after a halt
1190 if(order == 6 && lastorder == 5) { happened++; }
1191
1192 // Count number of other messages after a halt
1193 if(order != 6 && lastorder == 5) { happened2++; }
1194
15c4dc5a 1195 if(cmdsRecvd > 999) {
1196 DbpString("1000 commands later...");
254b70a4 1197 break;
15c4dc5a 1198 }
ce02f6f9 1199 cmdsRecvd++;
1200
1201 if (p_response != NULL) {
7bc95e2e 1202 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1203 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1204 uint8_t par[MAX_PARITY_SIZE];
1205 GetParity(p_response->response, p_response->response_n, par);
3fe4ff4f 1206
7bc95e2e 1207 EmLogTrace(Uart.output,
1208 Uart.len,
1209 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1210 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1211 Uart.parity,
7bc95e2e 1212 p_response->response,
1213 p_response->response_n,
1214 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1215 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1216 par);
7bc95e2e 1217 }
1218
1219 if (!tracing) {
1220 Dbprintf("Trace Full. Simulation stopped.");
1221 break;
1222 }
1223 }
15c4dc5a 1224
1225 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1226 LED_A_OFF();
f71f4deb 1227 BigBuf_free_keep_EM();
15c4dc5a 1228}
1229
9492e0b0 1230
1231// prepare a delayed transfer. This simply shifts ToSend[] by a number
1232// of bits specified in the delay parameter.
1233void PrepareDelayedTransfer(uint16_t delay)
1234{
1235 uint8_t bitmask = 0;
1236 uint8_t bits_to_shift = 0;
1237 uint8_t bits_shifted = 0;
1238
1239 delay &= 0x07;
1240 if (delay) {
1241 for (uint16_t i = 0; i < delay; i++) {
1242 bitmask |= (0x01 << i);
1243 }
7bc95e2e 1244 ToSend[ToSendMax++] = 0x00;
9492e0b0 1245 for (uint16_t i = 0; i < ToSendMax; i++) {
1246 bits_to_shift = ToSend[i] & bitmask;
1247 ToSend[i] = ToSend[i] >> delay;
1248 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1249 bits_shifted = bits_to_shift;
1250 }
1251 }
1252}
1253
7bc95e2e 1254
1255//-------------------------------------------------------------------------------------
15c4dc5a 1256// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1257// Parameter timing:
7bc95e2e 1258// if NULL: transfer at next possible time, taking into account
1259// request guard time and frame delay time
1260// if == 0: transfer immediately and return time of transfer
9492e0b0 1261// if != 0: delay transfer until time specified
7bc95e2e 1262//-------------------------------------------------------------------------------------
6a1f2d82 1263static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1264{
7bc95e2e 1265
9492e0b0 1266 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1267
7bc95e2e 1268 uint32_t ThisTransferTime = 0;
e30c654b 1269
9492e0b0 1270 if (timing) {
1271 if(*timing == 0) { // Measure time
7bc95e2e 1272 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
9492e0b0 1273 } else {
1274 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1275 }
7bc95e2e 1276 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1277 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1278 LastTimeProxToAirStart = *timing;
1279 } else {
1280 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1281 while(GetCountSspClk() < ThisTransferTime);
1282 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1283 }
1284
7bc95e2e 1285 // clear TXRDY
1286 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1287
7bc95e2e 1288 uint16_t c = 0;
9492e0b0 1289 for(;;) {
1290 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1291 AT91C_BASE_SSC->SSC_THR = cmd[c];
1292 c++;
1293 if(c >= len) {
1294 break;
1295 }
1296 }
1297 }
7bc95e2e 1298
1299 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
15c4dc5a 1300}
1301
7bc95e2e 1302
15c4dc5a 1303//-----------------------------------------------------------------------------
195af472 1304// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1305//-----------------------------------------------------------------------------
6a1f2d82 1306void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1307{
7bc95e2e 1308 int i, j;
1309 int last;
1310 uint8_t b;
e30c654b 1311
7bc95e2e 1312 ToSendReset();
e30c654b 1313
7bc95e2e 1314 // Start of Communication (Seq. Z)
1315 ToSend[++ToSendMax] = SEC_Z;
1316 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1317 last = 0;
1318
1319 size_t bytecount = nbytes(bits);
1320 // Generate send structure for the data bits
1321 for (i = 0; i < bytecount; i++) {
1322 // Get the current byte to send
1323 b = cmd[i];
1324 size_t bitsleft = MIN((bits-(i*8)),8);
1325
1326 for (j = 0; j < bitsleft; j++) {
1327 if (b & 1) {
1328 // Sequence X
1329 ToSend[++ToSendMax] = SEC_X;
1330 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1331 last = 1;
1332 } else {
1333 if (last == 0) {
1334 // Sequence Z
1335 ToSend[++ToSendMax] = SEC_Z;
1336 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1337 } else {
1338 // Sequence Y
1339 ToSend[++ToSendMax] = SEC_Y;
1340 last = 0;
1341 }
1342 }
1343 b >>= 1;
1344 }
1345
6a1f2d82 1346 // Only transmit parity bit if we transmitted a complete byte
48ece4a7 1347 if (j == 8 && parity != NULL) {
7bc95e2e 1348 // Get the parity bit
6a1f2d82 1349 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1350 // Sequence X
1351 ToSend[++ToSendMax] = SEC_X;
1352 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1353 last = 1;
1354 } else {
1355 if (last == 0) {
1356 // Sequence Z
1357 ToSend[++ToSendMax] = SEC_Z;
1358 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1359 } else {
1360 // Sequence Y
1361 ToSend[++ToSendMax] = SEC_Y;
1362 last = 0;
1363 }
1364 }
1365 }
1366 }
e30c654b 1367
7bc95e2e 1368 // End of Communication: Logic 0 followed by Sequence Y
1369 if (last == 0) {
1370 // Sequence Z
1371 ToSend[++ToSendMax] = SEC_Z;
1372 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1373 } else {
1374 // Sequence Y
1375 ToSend[++ToSendMax] = SEC_Y;
1376 last = 0;
1377 }
1378 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1379
7bc95e2e 1380 // Convert to length of command:
1381 ToSendMax++;
15c4dc5a 1382}
1383
195af472 1384//-----------------------------------------------------------------------------
1385// Prepare reader command to send to FPGA
1386//-----------------------------------------------------------------------------
6a1f2d82 1387void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity)
195af472 1388{
6a1f2d82 1389 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
195af472 1390}
1391
0c8d25eb 1392
9ca155ba
M
1393//-----------------------------------------------------------------------------
1394// Wait for commands from reader
1395// Stop when button is pressed (return 1) or field was gone (return 2)
1396// Or return 0 when command is captured
1397//-----------------------------------------------------------------------------
6a1f2d82 1398static int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
9ca155ba
M
1399{
1400 *len = 0;
1401
1402 uint32_t timer = 0, vtime = 0;
1403 int analogCnt = 0;
1404 int analogAVG = 0;
1405
1406 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1407 // only, since we are receiving, not transmitting).
1408 // Signal field is off with the appropriate LED
1409 LED_D_OFF();
1410 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1411
1412 // Set ADC to read field strength
1413 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1414 AT91C_BASE_ADC->ADC_MR =
0c8d25eb 1415 ADC_MODE_PRESCALE(63) |
1416 ADC_MODE_STARTUP_TIME(1) |
1417 ADC_MODE_SAMPLE_HOLD_TIME(15);
9ca155ba
M
1418 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1419 // start ADC
1420 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1421
1422 // Now run a 'software UART' on the stream of incoming samples.
6a1f2d82 1423 UartInit(received, parity);
7bc95e2e 1424
1425 // Clear RXRDY:
1426 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1427
9ca155ba
M
1428 for(;;) {
1429 WDT_HIT();
1430
1431 if (BUTTON_PRESS()) return 1;
1432
1433 // test if the field exists
1434 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1435 analogCnt++;
1436 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1437 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1438 if (analogCnt >= 32) {
0c8d25eb 1439 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
9ca155ba
M
1440 vtime = GetTickCount();
1441 if (!timer) timer = vtime;
1442 // 50ms no field --> card to idle state
1443 if (vtime - timer > 50) return 2;
1444 } else
1445 if (timer) timer = 0;
1446 analogCnt = 0;
1447 analogAVG = 0;
1448 }
1449 }
7bc95e2e 1450
9ca155ba 1451 // receive and test the miller decoding
7bc95e2e 1452 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1453 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1454 if(MillerDecoding(b, 0)) {
1455 *len = Uart.len;
9ca155ba
M
1456 return 0;
1457 }
7bc95e2e 1458 }
1459
9ca155ba
M
1460 }
1461}
1462
9ca155ba 1463
6a1f2d82 1464static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded)
7bc95e2e 1465{
1466 uint8_t b;
1467 uint16_t i = 0;
1468 uint32_t ThisTransferTime;
1469
9ca155ba
M
1470 // Modulate Manchester
1471 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1472
1473 // include correction bit if necessary
1474 if (Uart.parityBits & 0x01) {
1475 correctionNeeded = TRUE;
1476 }
1477 if(correctionNeeded) {
9ca155ba
M
1478 // 1236, so correction bit needed
1479 i = 0;
7bc95e2e 1480 } else {
1481 i = 1;
9ca155ba 1482 }
7bc95e2e 1483
d714d3ef 1484 // clear receiving shift register and holding register
7bc95e2e 1485 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1486 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1487 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1488 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
9ca155ba 1489
7bc95e2e 1490 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1491 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1492 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1493 if (AT91C_BASE_SSC->SSC_RHR) break;
1494 }
1495
1496 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1497
1498 // Clear TXRDY:
1499 AT91C_BASE_SSC->SSC_THR = SEC_F;
1500
9ca155ba 1501 // send cycle
bb42a03e 1502 for(; i < respLen; ) {
9ca155ba 1503 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1504 AT91C_BASE_SSC->SSC_THR = resp[i++];
1505 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1506 }
7bc95e2e 1507
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M
1508 if(BUTTON_PRESS()) {
1509 break;
1510 }
1511 }
1512
7bc95e2e 1513 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
0c8d25eb 1514 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
1515 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
7bc95e2e 1516 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1517 AT91C_BASE_SSC->SSC_THR = SEC_F;
1518 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1519 i++;
1520 }
1521 }
0c8d25eb 1522
7bc95e2e 1523 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1524
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M
1525 return 0;
1526}
1527
7bc95e2e 1528int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1529 Code4bitAnswerAsTag(resp);
0a39986e 1530 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1531 // do the tracing for the previous reader request and this tag answer:
6a1f2d82 1532 uint8_t par[1];
1533 GetParity(&resp, 1, par);
7bc95e2e 1534 EmLogTrace(Uart.output,
1535 Uart.len,
1536 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1537 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1538 Uart.parity,
7bc95e2e 1539 &resp,
1540 1,
1541 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1542 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1543 par);
0a39986e 1544 return res;
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M
1545}
1546
8f51ddb0 1547int EmSend4bit(uint8_t resp){
7bc95e2e 1548 return EmSend4bitEx(resp, false);
8f51ddb0
M
1549}
1550
6a1f2d82 1551int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
7bc95e2e 1552 CodeIso14443aAsTagPar(resp, respLen, par);
8f51ddb0 1553 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
7bc95e2e 1554 // do the tracing for the previous reader request and this tag answer:
1555 EmLogTrace(Uart.output,
1556 Uart.len,
1557 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1558 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
6a1f2d82 1559 Uart.parity,
7bc95e2e 1560 resp,
1561 respLen,
1562 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1563 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
6a1f2d82 1564 par);
8f51ddb0
M
1565 return res;
1566}
1567
6a1f2d82 1568int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1569 uint8_t par[MAX_PARITY_SIZE];
1570 GetParity(resp, respLen, par);
1571 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
8f51ddb0
M
1572}
1573
6a1f2d82 1574int EmSendCmd(uint8_t *resp, uint16_t respLen){
1575 uint8_t par[MAX_PARITY_SIZE];
1576 GetParity(resp, respLen, par);
1577 return EmSendCmdExPar(resp, respLen, false, par);
8f51ddb0
M
1578}
1579
6a1f2d82 1580int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1581 return EmSendCmdExPar(resp, respLen, false, par);
1582}
1583
6a1f2d82 1584bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1585 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
7bc95e2e 1586{
1587 if (tracing) {
1588 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1589 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1590 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1591 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1592 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1593 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1594 reader_EndTime = tag_StartTime - exact_fdt;
1595 reader_StartTime = reader_EndTime - reader_modlen;
6a1f2d82 1596 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE)) {
7bc95e2e 1597 return FALSE;
6a1f2d82 1598 } else return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
7bc95e2e 1599 } else {
1600 return TRUE;
1601 }
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M
1602}
1603
15c4dc5a 1604//-----------------------------------------------------------------------------
1605// Wait a certain time for tag response
1606// If a response is captured return TRUE
e691fc45 1607// If it takes too long return FALSE
15c4dc5a 1608//-----------------------------------------------------------------------------
6a1f2d82 1609static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1610{
52bfb955 1611 uint32_t c;
e691fc45 1612
15c4dc5a 1613 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1614 // only, since we are receiving, not transmitting).
1615 // Signal field is on with the appropriate LED
1616 LED_D_ON();
1617 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1c611bbd 1618
534983d7 1619 // Now get the answer from the card
6a1f2d82 1620 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1621
7bc95e2e 1622 // clear RXRDY:
1623 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1624
15c4dc5a 1625 c = 0;
1626 for(;;) {
534983d7 1627 WDT_HIT();
15c4dc5a 1628
534983d7 1629 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1630 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1631 if(ManchesterDecoding(b, offset, 0)) {
1632 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
15c4dc5a 1633 return TRUE;
19a700a8 1634 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
7bc95e2e 1635 return FALSE;
15c4dc5a 1636 }
534983d7 1637 }
1638 }
15c4dc5a 1639}
1640
48ece4a7 1641
6a1f2d82 1642void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1643{
6a1f2d82 1644 CodeIso14443aBitsAsReaderPar(frame, bits, par);
dfc3c505 1645
7bc95e2e 1646 // Send command to tag
1647 TransmitFor14443a(ToSend, ToSendMax, timing);
1648 if(trigger)
1649 LED_A_ON();
dfc3c505 1650
7bc95e2e 1651 // Log reader command in trace buffer
1652 if (tracing) {
6a1f2d82 1653 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, TRUE);
7bc95e2e 1654 }
15c4dc5a 1655}
1656
48ece4a7 1657
6a1f2d82 1658void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1659{
6a1f2d82 1660 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1661}
15c4dc5a 1662
48ece4a7 1663
6a1f2d82 1664void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1665{
1666 // Generate parity and redirect
6a1f2d82 1667 uint8_t par[MAX_PARITY_SIZE];
1668 GetParity(frame, len/8, par);
1669 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1670}
1671
48ece4a7 1672
6a1f2d82 1673void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1674{
1675 // Generate parity and redirect
6a1f2d82 1676 uint8_t par[MAX_PARITY_SIZE];
1677 GetParity(frame, len, par);
1678 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1679}
1680
6a1f2d82 1681int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1682{
6a1f2d82 1683 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return FALSE;
7bc95e2e 1684 if (tracing) {
6a1f2d82 1685 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1686 }
e691fc45 1687 return Demod.len;
1688}
1689
6a1f2d82 1690int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
15c4dc5a 1691{
6a1f2d82 1692 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return FALSE;
7bc95e2e 1693 if (tracing) {
6a1f2d82 1694 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
7bc95e2e 1695 }
e691fc45 1696 return Demod.len;
f89c7050
M
1697}
1698
e691fc45 1699/* performs iso14443a anticollision procedure
534983d7 1700 * fills the uid pointer unless NULL
1701 * fills resp_data unless NULL */
6a1f2d82 1702int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr) {
1703 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1704 uint8_t sel_all[] = { 0x93,0x20 };
1705 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1706 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
f71f4deb 1707 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1708 uint8_t resp_par[MAX_PARITY_SIZE];
6a1f2d82 1709 byte_t uid_resp[4];
1710 size_t uid_resp_len;
1711
1712 uint8_t sak = 0x04; // cascade uid
1713 int cascade_level = 0;
1714 int len;
1715
1716 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
9492e0b0 1717 ReaderTransmitBitsPar(wupa,7,0, NULL);
7bc95e2e 1718
6a1f2d82 1719 // Receive the ATQA
1720 if(!ReaderReceive(resp, resp_par)) return 0;
6a1f2d82 1721
1722 if(p_hi14a_card) {
1723 memcpy(p_hi14a_card->atqa, resp, 2);
1724 p_hi14a_card->uidlen = 0;
1725 memset(p_hi14a_card->uid,0,10);
1726 }
5f6d6c90 1727
6a1f2d82 1728 // clear uid
1729 if (uid_ptr) {
1730 memset(uid_ptr,0,10);
1731 }
79a73ab2 1732
ee1eadee 1733 // check for proprietary anticollision:
1734 if ((resp[0] & 0x1F) == 0) {
1735 return 3;
1736 }
1737
6a1f2d82 1738 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1739 // which case we need to make a cascade 2 request and select - this is a long UID
1740 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1741 for(; sak & 0x04; cascade_level++) {
1742 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1743 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1744
1745 // SELECT_ALL
1746 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1747 if (!ReaderReceive(resp, resp_par)) return 0;
1748
1749 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1750 memset(uid_resp, 0, 4);
1751 uint16_t uid_resp_bits = 0;
1752 uint16_t collision_answer_offset = 0;
1753 // anti-collision-loop:
1754 while (Demod.collisionPos) {
1755 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1756 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1757 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
758f1fd1 1758 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1759 }
1760 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1761 uid_resp_bits++;
1762 // construct anticollosion command:
1763 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1764 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1765 sel_uid[2+i] = uid_resp[i];
1766 }
1767 collision_answer_offset = uid_resp_bits%8;
1768 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1769 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
e691fc45 1770 }
6a1f2d82 1771 // finally, add the last bits and BCC of the UID
1772 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1773 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1774 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
e691fc45 1775 }
e691fc45 1776
6a1f2d82 1777 } else { // no collision, use the response to SELECT_ALL as current uid
1778 memcpy(uid_resp, resp, 4);
1779 }
1780 uid_resp_len = 4;
5f6d6c90 1781
6a1f2d82 1782 // calculate crypto UID. Always use last 4 Bytes.
1783 if(cuid_ptr) {
1784 *cuid_ptr = bytes_to_num(uid_resp, 4);
1785 }
e30c654b 1786
6a1f2d82 1787 // Construct SELECT UID command
1788 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1789 memcpy(sel_uid+2, uid_resp, 4); // the UID
1790 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1791 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1792 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1793
1794 // Receive the SAK
1795 if (!ReaderReceive(resp, resp_par)) return 0;
1796 sak = resp[0];
1797
52ab55ab 1798 // Test if more parts of the uid are coming
6a1f2d82 1799 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1800 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1801 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1802 uid_resp[0] = uid_resp[1];
1803 uid_resp[1] = uid_resp[2];
1804 uid_resp[2] = uid_resp[3];
1805
1806 uid_resp_len = 3;
1807 }
5f6d6c90 1808
6a1f2d82 1809 if(uid_ptr) {
1810 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1811 }
5f6d6c90 1812
6a1f2d82 1813 if(p_hi14a_card) {
1814 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1815 p_hi14a_card->uidlen += uid_resp_len;
1816 }
1817 }
79a73ab2 1818
6a1f2d82 1819 if(p_hi14a_card) {
1820 p_hi14a_card->sak = sak;
1821 p_hi14a_card->ats_len = 0;
1822 }
534983d7 1823
3fe4ff4f 1824 // non iso14443a compliant tag
1825 if( (sak & 0x20) == 0) return 2;
534983d7 1826
6a1f2d82 1827 // Request for answer to select
1828 AppendCrc14443a(rats, 2);
1829 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1830
6a1f2d82 1831 if (!(len = ReaderReceive(resp, resp_par))) return 0;
5191b3d1 1832
3fe4ff4f 1833
6a1f2d82 1834 if(p_hi14a_card) {
1835 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1836 p_hi14a_card->ats_len = len;
1837 }
5f6d6c90 1838
6a1f2d82 1839 // reset the PCB block number
1840 iso14_pcb_blocknum = 0;
19a700a8 1841
1842 // set default timeout based on ATS
1843 iso14a_set_ATS_timeout(resp);
1844
6a1f2d82 1845 return 1;
7e758047 1846}
15c4dc5a 1847
7bc95e2e 1848void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1849 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1850 // Set up the synchronous serial port
1851 FpgaSetupSsc();
7bc95e2e 1852 // connect Demodulated Signal to ADC:
7e758047 1853 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
e30c654b 1854
7e758047 1855 // Signal field is on with the appropriate LED
7bc95e2e 1856 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1857 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1858 LED_D_ON();
1859 } else {
1860 LED_D_OFF();
1861 }
1862 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
534983d7 1863
7bc95e2e 1864 // Start the timer
1865 StartCountSspClk();
1866
1867 DemodReset();
1868 UartReset();
1869 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
1870 iso14a_set_timeout(1050); // 10ms default
7e758047 1871}
15c4dc5a 1872
6a1f2d82 1873int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1874 uint8_t parity[MAX_PARITY_SIZE];
534983d7 1875 uint8_t real_cmd[cmd_len+4];
1876 real_cmd[0] = 0x0a; //I-Block
b0127e65 1877 // put block number into the PCB
1878 real_cmd[0] |= iso14_pcb_blocknum;
534983d7 1879 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
1880 memcpy(real_cmd+2, cmd, cmd_len);
1881 AppendCrc14443a(real_cmd,cmd_len+2);
1882
9492e0b0 1883 ReaderTransmit(real_cmd, cmd_len+4, NULL);
6a1f2d82 1884 size_t len = ReaderReceive(data, parity);
1885 uint8_t *data_bytes = (uint8_t *) data;
b0127e65 1886 if (!len)
1887 return 0; //DATA LINK ERROR
1888 // if we received an I- or R(ACK)-Block with a block number equal to the
1889 // current block number, toggle the current block number
1890 else if (len >= 4 // PCB+CID+CRC = 4 bytes
1891 && ((data_bytes[0] & 0xC0) == 0 // I-Block
1892 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
1893 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
1894 {
1895 iso14_pcb_blocknum ^= 1;
1896 }
1897
534983d7 1898 return len;
1899}
1900
7e758047 1901//-----------------------------------------------------------------------------
1902// Read an ISO 14443a tag. Send out commands and store answers.
1903//
1904//-----------------------------------------------------------------------------
7bc95e2e 1905void ReaderIso14443a(UsbCommand *c)
7e758047 1906{
534983d7 1907 iso14a_command_t param = c->arg[0];
7bc95e2e 1908 uint8_t *cmd = c->d.asBytes;
04bc1c66 1909 size_t len = c->arg[1] & 0xffff;
1910 size_t lenbits = c->arg[1] >> 16;
1911 uint32_t timeout = c->arg[2];
9492e0b0 1912 uint32_t arg0 = 0;
1913 byte_t buf[USB_CMD_DATA_SIZE];
6a1f2d82 1914 uint8_t par[MAX_PARITY_SIZE];
902cb3c0 1915
5f6d6c90 1916 if(param & ISO14A_CONNECT) {
3000dc4e 1917 clear_trace();
5f6d6c90 1918 }
e691fc45 1919
3000dc4e 1920 set_tracing(TRUE);
e30c654b 1921
79a73ab2 1922 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1923 iso14a_set_trigger(TRUE);
9492e0b0 1924 }
15c4dc5a 1925
534983d7 1926 if(param & ISO14A_CONNECT) {
7bc95e2e 1927 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 1928 if(!(param & ISO14A_NO_SELECT)) {
1929 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
1930 arg0 = iso14443a_select_card(NULL,card,NULL);
1931 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
1932 }
534983d7 1933 }
e30c654b 1934
534983d7 1935 if(param & ISO14A_SET_TIMEOUT) {
04bc1c66 1936 iso14a_set_timeout(timeout);
534983d7 1937 }
e30c654b 1938
534983d7 1939 if(param & ISO14A_APDU) {
902cb3c0 1940 arg0 = iso14_apdu(cmd, len, buf);
79a73ab2 1941 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1942 }
e30c654b 1943
534983d7 1944 if(param & ISO14A_RAW) {
1945 if(param & ISO14A_APPEND_CRC) {
48ece4a7 1946 if(param & ISO14A_TOPAZMODE) {
1947 AppendCrc14443b(cmd,len);
1948 } else {
1949 AppendCrc14443a(cmd,len);
1950 }
534983d7 1951 len += 2;
c7324bef 1952 if (lenbits) lenbits += 16;
15c4dc5a 1953 }
48ece4a7 1954 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
1955 if(param & ISO14A_TOPAZMODE) {
1956 int bits_to_send = lenbits;
1957 uint16_t i = 0;
1958 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
1959 bits_to_send -= 7;
1960 while (bits_to_send > 0) {
1961 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
1962 bits_to_send -= 8;
1963 }
1964 } else {
1965 GetParity(cmd, lenbits/8, par);
1966 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
1967 }
1968 } else { // want to send complete bytes only
1969 if(param & ISO14A_TOPAZMODE) {
1970 uint16_t i = 0;
1971 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
1972 while (i < len) {
1973 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
1974 }
1975 } else {
1976 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
1977 }
5f6d6c90 1978 }
6a1f2d82 1979 arg0 = ReaderReceive(buf, par);
9492e0b0 1980 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
534983d7 1981 }
15c4dc5a 1982
79a73ab2 1983 if(param & ISO14A_REQUEST_TRIGGER) {
7bc95e2e 1984 iso14a_set_trigger(FALSE);
9492e0b0 1985 }
15c4dc5a 1986
79a73ab2 1987 if(param & ISO14A_NO_DISCONNECT) {
534983d7 1988 return;
9492e0b0 1989 }
15c4dc5a 1990
15c4dc5a 1991 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1992 LEDsoff();
15c4dc5a 1993}
b0127e65 1994
1c611bbd 1995
1c611bbd 1996// Determine the distance between two nonces.
1997// Assume that the difference is small, but we don't know which is first.
1998// Therefore try in alternating directions.
1999int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2000
2001 uint16_t i;
2002 uint32_t nttmp1, nttmp2;
e772353f 2003
1c611bbd 2004 if (nt1 == nt2) return 0;
2005
2006 nttmp1 = nt1;
2007 nttmp2 = nt2;
2008
2009 for (i = 1; i < 32768; i++) {
2010 nttmp1 = prng_successor(nttmp1, 1);
2011 if (nttmp1 == nt2) return i;
2012 nttmp2 = prng_successor(nttmp2, 1);
dc8ba239 2013 if (nttmp2 == nt1) return -i;
1c611bbd 2014 }
2015
2016 return(-99999); // either nt1 or nt2 are invalid nonces
e772353f 2017}
2018
e772353f 2019
1c611bbd 2020//-----------------------------------------------------------------------------
2021// Recover several bits of the cypher stream. This implements (first stages of)
2022// the algorithm described in "The Dark Side of Security by Obscurity and
2023// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2024// (article by Nicolas T. Courtois, 2009)
2025//-----------------------------------------------------------------------------
2026void ReaderMifare(bool first_try)
2027{
2028 // Mifare AUTH
2029 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2030 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2031 static uint8_t mf_nr_ar3;
e772353f 2032
f71f4deb 2033 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2034 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
7bc95e2e 2035
09ffd16e 2036 if (first_try) {
2037 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2038 }
2039
f71f4deb 2040 // free eventually allocated BigBuf memory. We want all for tracing.
2041 BigBuf_free();
2042
3000dc4e
MHS
2043 clear_trace();
2044 set_tracing(TRUE);
e772353f 2045
1c611bbd 2046 byte_t nt_diff = 0;
6a1f2d82 2047 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
1c611bbd 2048 static byte_t par_low = 0;
2049 bool led_on = TRUE;
ca4714cd 2050 uint8_t uid[10] ={0};
1c611bbd 2051 uint32_t cuid;
e772353f 2052
6a1f2d82 2053 uint32_t nt = 0;
2ed270a8 2054 uint32_t previous_nt = 0;
1c611bbd 2055 static uint32_t nt_attacked = 0;
3fe4ff4f 2056 byte_t par_list[8] = {0x00};
2057 byte_t ks_list[8] = {0x00};
e772353f 2058
dfb387bf 2059 #define PRNG_SEQUENCE_LENGTH (1 << 16);
1c611bbd 2060 static uint32_t sync_time;
8c6b2298 2061 static int32_t sync_cycles;
1c611bbd 2062 int catch_up_cycles = 0;
2063 int last_catch_up = 0;
8c6b2298 2064 uint16_t elapsed_prng_sequences;
1c611bbd 2065 uint16_t consecutive_resyncs = 0;
2066 int isOK = 0;
e772353f 2067
1c611bbd 2068 if (first_try) {
1c611bbd 2069 mf_nr_ar3 = 0;
7bc95e2e 2070 sync_time = GetCountSspClk() & 0xfffffff8;
dfb387bf 2071 sync_cycles = PRNG_SEQUENCE_LENGTH; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
1c611bbd 2072 nt_attacked = 0;
6a1f2d82 2073 par[0] = 0;
1c611bbd 2074 }
2075 else {
2076 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1c611bbd 2077 mf_nr_ar3++;
2078 mf_nr_ar[3] = mf_nr_ar3;
6a1f2d82 2079 par[0] = par_low;
1c611bbd 2080 }
e30c654b 2081
15c4dc5a 2082 LED_A_ON();
2083 LED_B_OFF();
2084 LED_C_OFF();
1c611bbd 2085
dc8ba239 2086
dfb387bf 2087 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
8c6b2298 2088 #define MAX_SYNC_TRIES 32
2089 #define NUM_DEBUG_INFOS 8 // per strategy
2090 #define MAX_STRATEGY 3
dfb387bf 2091 uint16_t unexpected_random = 0;
2092 uint16_t sync_tries = 0;
2093 int16_t debug_info_nr = -1;
8c6b2298 2094 uint16_t strategy = 0;
2095 int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS];
2096 uint32_t select_time;
2097 uint32_t halt_time;
dc8ba239 2098
1c611bbd 2099 for(uint16_t i = 0; TRUE; i++) {
2100
dc8ba239 2101 LED_C_ON();
1c611bbd 2102 WDT_HIT();
e30c654b 2103
1c611bbd 2104 // Test if the action was cancelled
2105 if(BUTTON_PRESS()) {
dc8ba239 2106 isOK = -1;
1c611bbd 2107 break;
2108 }
2109
8c6b2298 2110 if (strategy == 2) {
2111 // test with additional hlt command
2112 halt_time = 0;
2113 int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time);
2114 if (len && MF_DBGLEVEL >= 3) {
2115 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len);
2116 }
2117 }
2118
2119 if (strategy == 3) {
2120 // test with FPGA power off/on
2121 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2122 SpinDelay(200);
2123 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2124 SpinDelay(100);
2125 }
2126
1c611bbd 2127 if(!iso14443a_select_card(uid, NULL, &cuid)) {
9492e0b0 2128 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1c611bbd 2129 continue;
2130 }
8c6b2298 2131 select_time = GetCountSspClk();
1c611bbd 2132
8c6b2298 2133 elapsed_prng_sequences = 1;
dfb387bf 2134 if (debug_info_nr == -1) {
2135 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2136 catch_up_cycles = 0;
1c611bbd 2137
dfb387bf 2138 // if we missed the sync time already, advance to the next nonce repeat
2139 while(GetCountSspClk() > sync_time) {
8c6b2298 2140 elapsed_prng_sequences++;
dfb387bf 2141 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2142 }
e30c654b 2143
dfb387bf 2144 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2145 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2146 } else {
8c6b2298 2147 // collect some information on tag nonces for debugging:
2148 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
2149 if (strategy == 0) {
2150 // nonce distances at fixed time after card select:
2151 sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES;
2152 } else if (strategy == 1) {
2153 // nonce distances at fixed time between authentications:
2154 sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES;
2155 } else if (strategy == 2) {
2156 // nonce distances at fixed time after halt:
2157 sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES;
2158 } else {
2159 // nonce_distances at fixed time after power on
2160 sync_time = DEBUG_FIXED_SYNC_CYCLES;
2161 }
2162 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
dfb387bf 2163 }
f89c7050 2164
1c611bbd 2165 // Receive the (4 Byte) "random" nonce
6a1f2d82 2166 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2167 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
1c611bbd 2168 continue;
2169 }
2170
1c611bbd 2171 previous_nt = nt;
2172 nt = bytes_to_num(receivedAnswer, 4);
2173
2174 // Transmit reader nonce with fake par
9492e0b0 2175 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
1c611bbd 2176
2177 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2178 int nt_distance = dist_nt(previous_nt, nt);
2179 if (nt_distance == 0) {
2180 nt_attacked = nt;
dfb387bf 2181 } else {
dc8ba239 2182 if (nt_distance == -99999) { // invalid nonce received
dfb387bf 2183 unexpected_random++;
8c6b2298 2184 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
dc8ba239 2185 isOK = -3; // Card has an unpredictable PRNG. Give up
2186 break;
2187 } else {
2188 continue; // continue trying...
2189 }
1c611bbd 2190 }
dfb387bf 2191 if (++sync_tries > MAX_SYNC_TRIES) {
8c6b2298 2192 if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) {
dfb387bf 2193 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2194 break;
2195 } else { // continue for a while, just to collect some debug info
8c6b2298 2196 debug_info[strategy][debug_info_nr] = nt_distance;
2197 debug_info_nr++;
2198 if (debug_info_nr == NUM_DEBUG_INFOS) {
2199 strategy++;
2200 debug_info_nr = 0;
2201 }
dfb387bf 2202 continue;
2203 }
2204 }
8c6b2298 2205 sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences);
dfb387bf 2206 if (sync_cycles <= 0) {
2207 sync_cycles += PRNG_SEQUENCE_LENGTH;
2208 }
2209 if (MF_DBGLEVEL >= 3) {
8c6b2298 2210 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
dfb387bf 2211 }
1c611bbd 2212 continue;
2213 }
2214 }
2215
2216 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2217 catch_up_cycles = -dist_nt(nt_attacked, nt);
2218 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2219 catch_up_cycles = 0;
2220 continue;
2221 }
8c6b2298 2222 catch_up_cycles /= elapsed_prng_sequences;
1c611bbd 2223 if (catch_up_cycles == last_catch_up) {
2224 consecutive_resyncs++;
2225 }
2226 else {
2227 last_catch_up = catch_up_cycles;
2228 consecutive_resyncs = 0;
2229 }
2230 if (consecutive_resyncs < 3) {
9492e0b0 2231 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
1c611bbd 2232 }
2233 else {
2234 sync_cycles = sync_cycles + catch_up_cycles;
9492e0b0 2235 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
8c6b2298 2236 last_catch_up = 0;
2237 catch_up_cycles = 0;
2238 consecutive_resyncs = 0;
1c611bbd 2239 }
2240 continue;
2241 }
2242
2243 consecutive_resyncs = 0;
2244
2245 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
8c6b2298 2246 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
9492e0b0 2247 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
1c611bbd 2248
8c6b2298 2249 if (nt_diff == 0) {
6a1f2d82 2250 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2251 }
2252
2253 led_on = !led_on;
2254 if(led_on) LED_B_ON(); else LED_B_OFF();
2255
6a1f2d82 2256 par_list[nt_diff] = SwapBits(par[0], 8);
1c611bbd 2257 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2258
2259 // Test if the information is complete
2260 if (nt_diff == 0x07) {
2261 isOK = 1;
2262 break;
2263 }
2264
2265 nt_diff = (nt_diff + 1) & 0x07;
2266 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2267 par[0] = par_low;
1c611bbd 2268 } else {
2269 if (nt_diff == 0 && first_try)
2270 {
6a1f2d82 2271 par[0]++;
dc8ba239 2272 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2273 isOK = -2;
2274 break;
2275 }
1c611bbd 2276 } else {
6a1f2d82 2277 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2278 }
2279 }
2280 }
2281
1c611bbd 2282
2283 mf_nr_ar[3] &= 0x1F;
dfb387bf 2284
2285 if (isOK == -4) {
2286 if (MF_DBGLEVEL >= 3) {
8c6b2298 2287 for (uint16_t i = 0; i <= MAX_STRATEGY; i++) {
2288 for(uint16_t j = 0; j < NUM_DEBUG_INFOS; j++) {
2289 Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]);
2290 }
dfb387bf 2291 }
2292 }
2293 }
1c611bbd 2294
2295 byte_t buf[28];
2296 memcpy(buf + 0, uid, 4);
2297 num_to_bytes(nt, 4, buf + 4);
2298 memcpy(buf + 8, par_list, 8);
2299 memcpy(buf + 16, ks_list, 8);
2300 memcpy(buf + 24, mf_nr_ar, 4);
2301
dc8ba239 2302 cmd_send(CMD_ACK, isOK, 0, 0, buf, 28);
1c611bbd 2303
2304 // Thats it...
2305 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2306 LEDsoff();
7bc95e2e 2307
3000dc4e 2308 set_tracing(FALSE);
20f9a2a1 2309}
1c611bbd 2310
79dcb9e0 2311typedef struct {
2312 uint32_t cuid;
2313 uint8_t sector;
2314 uint8_t keytype;
2315 uint32_t nonce;
2316 uint32_t ar;
2317 uint32_t nr;
2318 uint32_t nonce2;
2319 uint32_t ar2;
2320 uint32_t nr2;
2321} nonces_t;
2322
d2f487af 2323/**
2324 *MIFARE 1K simulate.
2325 *
2326 *@param flags :
2327 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
c872d8c1 2328 * FLAG_4B_UID_IN_DATA - means that there is a 4-byte UID in the data-section, we're expected to use that
2329 * FLAG_7B_UID_IN_DATA - means that there is a 7-byte UID in the data-section, we're expected to use that
2330 * FLAG_10B_UID_IN_DATA - use 10-byte UID in the data-section not finished
d2f487af 2331 * FLAG_NR_AR_ATTACK - means we should collect NR_AR responses for bruteforcing later
c872d8c1 2332 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is infinite ...
2333 * (unless reader attack mode enabled then it runs util it gets enough nonces to recover all keys attmpted)
d2f487af 2334 */
2335void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain)
20f9a2a1 2336{
50193c1e 2337 int cardSTATE = MFEMUL_NOFIELD;
c872d8c1 2338 int _UID_LEN = 0; // 4, 7, 10
9ca155ba 2339 int vHf = 0; // in mV
8f51ddb0 2340 int res;
0a39986e
M
2341 uint32_t selTimer = 0;
2342 uint32_t authTimer = 0;
6a1f2d82 2343 uint16_t len = 0;
8f51ddb0 2344 uint8_t cardWRBL = 0;
9ca155ba
M
2345 uint8_t cardAUTHSC = 0;
2346 uint8_t cardAUTHKEY = 0xff; // no authentication
51969283 2347 uint32_t cardRr = 0;
9ca155ba 2348 uint32_t cuid = 0;
d2f487af 2349 //uint32_t rn_enc = 0;
51969283 2350 uint32_t ans = 0;
0014cb46
M
2351 uint32_t cardINTREG = 0;
2352 uint8_t cardINTBLOCK = 0;
9ca155ba
M
2353 struct Crypto1State mpcs = {0, 0};
2354 struct Crypto1State *pcs;
2355 pcs = &mpcs;
d2f487af 2356 uint32_t numReads = 0;//Counts numer of times reader read a block
f71f4deb 2357 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2358 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE];
2359 uint8_t response[MAX_MIFARE_FRAME_SIZE];
2360 uint8_t response_par[MAX_MIFARE_PARITY_SIZE];
9ca155ba 2361
76ef5273 2362 uint8_t rATQA[] = {0x04, 0x00}; // Mifare classic 1k 4BUID
d2f487af 2363 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2364 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62}; // !!!
c872d8c1 2365 uint8_t rUIDBCC3[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2366
76ef5273 2367 uint8_t rSAKfinal[]= {0x08, 0xb6, 0xdd}; // mifare 1k indicated
2368 uint8_t rSAK1[] = {0x04, 0xda, 0x17}; // indicate UID not finished
9ca155ba 2369
d2f487af 2370 uint8_t rAUTH_NT[] = {0x01, 0x02, 0x03, 0x04};
2371 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
7bc95e2e 2372
79dcb9e0 2373 //Here, we collect UID,sector,keytype,NT,AR,NR,NT2,AR2,NR2
c872d8c1 2374 // This will be used in the reader-only attack.
2375
76ef5273 2376 //allow collecting up to 8 sets of nonces to allow recovery of up to 8 keys
2377 #define ATTACK_KEY_COUNT 8 // keep same as define in cmdhfmf.c -> readerAttack()
91f4d531 2378 nonces_t ar_nr_resp[ATTACK_KEY_COUNT*2]; //*2 for 2 separate attack types (nml, moebius)
79dcb9e0 2379 memset(ar_nr_resp, 0x00, sizeof(ar_nr_resp));
2380
91f4d531 2381 uint8_t ar_nr_collected[ATTACK_KEY_COUNT*2]; //*2 for 2nd attack type (moebius)
79dcb9e0 2382 memset(ar_nr_collected, 0x00, sizeof(ar_nr_collected));
c872d8c1 2383 uint8_t nonce1_count = 0;
2384 uint8_t nonce2_count = 0;
2385 uint8_t moebius_n_count = 0;
91f4d531 2386 bool gettingMoebius = false;
c872d8c1 2387 uint8_t mM = 0; //moebius_modifier for collection storage
2388
7bc95e2e 2389 // Authenticate response - nonce
51969283 2390 uint32_t nonce = bytes_to_num(rAUTH_NT, 4);
7bc95e2e 2391
d2f487af 2392 //-- Determine the UID
2393 // Can be set from emulator memory, incoming data
2394 // and can be 7 or 4 bytes long
7bc95e2e 2395 if (flags & FLAG_4B_UID_IN_DATA)
d2f487af 2396 {
2397 // 4B uid comes from data-portion of packet
2398 memcpy(rUIDBCC1,datain,4);
8556b852 2399 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
c872d8c1 2400 _UID_LEN = 4;
7bc95e2e 2401 } else if (flags & FLAG_7B_UID_IN_DATA) {
d2f487af 2402 // 7B uid comes from data-portion of packet
2403 memcpy(&rUIDBCC1[1],datain,3);
2404 memcpy(rUIDBCC2, datain+3, 4);
c872d8c1 2405 _UID_LEN = 7;
2406 } else if (flags & FLAG_10B_UID_IN_DATA) {
2407 memcpy(&rUIDBCC1[1], datain, 3);
2408 memcpy(&rUIDBCC2[1], datain+3, 3);
2409 memcpy( rUIDBCC3, datain+6, 4);
2410 _UID_LEN = 10;
7bc95e2e 2411 } else {
c872d8c1 2412 // get UID from emul memory - guess at length
d2f487af 2413 emlGetMemBt(receivedCmd, 7, 1);
76ef5273 2414 if (receivedCmd[0] == 0x00) { // ---------- 4BUID
d2f487af 2415 emlGetMemBt(rUIDBCC1, 0, 4);
c872d8c1 2416 _UID_LEN = 4;
d2f487af 2417 } else { // ---------- 7BUID
2418 emlGetMemBt(&rUIDBCC1[1], 0, 3);
2419 emlGetMemBt(rUIDBCC2, 3, 4);
c872d8c1 2420 _UID_LEN = 7;
d2f487af 2421 }
2422 }
7bc95e2e 2423
c872d8c1 2424 switch (_UID_LEN) {
2425 case 4:
2426 // save CUID
2427 cuid = bytes_to_num(rUIDBCC1, 4);
2428 // BCC
2429 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2430 if (MF_DBGLEVEL >= 2) {
2431 Dbprintf("4B UID: %02x%02x%02x%02x",
2432 rUIDBCC1[0],
2433 rUIDBCC1[1],
2434 rUIDBCC1[2],
2435 rUIDBCC1[3]
2436 );
2437 }
2438 break;
2439 case 7:
2440 rATQA[0] |= 0x40;
2441 // save CUID
2442 cuid = bytes_to_num(rUIDBCC2, 4);
2443 // CascadeTag, CT
2444 rUIDBCC1[0] = 0x88;
2445 // BCC
2446 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2447 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2448 if (MF_DBGLEVEL >= 2) {
2449 Dbprintf("7B UID: %02x %02x %02x %02x %02x %02x %02x",
2450 rUIDBCC1[1],
2451 rUIDBCC1[2],
2452 rUIDBCC1[3],
2453 rUIDBCC2[0],
2454 rUIDBCC2[1],
2455 rUIDBCC2[2],
2456 rUIDBCC2[3]
2457 );
2458 }
2459 break;
2460 case 10:
2461 rATQA[0] |= 0x80;
2462 //sak_10[0] &= 0xFB;
2463 // save CUID
2464 cuid = bytes_to_num(rUIDBCC3, 4);
2465 // CascadeTag, CT
2466 rUIDBCC1[0] = 0x88;
2467 rUIDBCC2[0] = 0x88;
2468 // BCC
2469 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2470 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2471 rUIDBCC3[4] = rUIDBCC3[0] ^ rUIDBCC3[1] ^ rUIDBCC3[2] ^ rUIDBCC3[3];
2472
2473 if (MF_DBGLEVEL >= 2) {
2474 Dbprintf("10B UID: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
2475 rUIDBCC1[1],
2476 rUIDBCC1[2],
2477 rUIDBCC1[3],
2478 rUIDBCC2[1],
2479 rUIDBCC2[2],
2480 rUIDBCC2[3],
2481 rUIDBCC3[0],
2482 rUIDBCC3[1],
2483 rUIDBCC3[2],
2484 rUIDBCC3[3]
2485 );
2486 }
2487 break;
2488 default:
2489 break;
d2f487af 2490 }
7bc95e2e 2491
09ffd16e 2492 // We need to listen to the high-frequency, peak-detected path.
2493 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2494
2495 // free eventually allocated BigBuf memory but keep Emulator Memory
2496 BigBuf_free_keep_EM();
2497
2498 // clear trace
2499 clear_trace();
2500 set_tracing(TRUE);
2501
7bc95e2e 2502 bool finished = FALSE;
73ab92d1 2503 bool button_pushed = BUTTON_PRESS();
2504 while (!button_pushed && !finished && !usb_poll_validate_length()) {
9ca155ba 2505 WDT_HIT();
9ca155ba
M
2506
2507 // find reader field
9ca155ba 2508 if (cardSTATE == MFEMUL_NOFIELD) {
0c8d25eb 2509 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
9ca155ba 2510 if (vHf > MF_MINFIELDV) {
0014cb46 2511 cardSTATE_TO_IDLE();
9ca155ba
M
2512 LED_A_ON();
2513 }
91f4d531 2514 }
c872d8c1 2515 if (cardSTATE == MFEMUL_NOFIELD) continue;
9ca155ba 2516
d2f487af 2517 //Now, get data
6a1f2d82 2518 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
d2f487af 2519 if (res == 2) { //Field is off!
2520 cardSTATE = MFEMUL_NOFIELD;
2521 LEDsoff();
2522 continue;
7bc95e2e 2523 } else if (res == 1) {
2524 break; //return value 1 means button press
2525 }
91f4d531 2526
d2f487af 2527 // REQ or WUP request in ANY state and WUP in HALTED state
c872d8c1 2528 if (len == 1 && ((receivedCmd[0] == ISO14443A_CMD_REQA && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == ISO14443A_CMD_WUPA)) {
d2f487af 2529 selTimer = GetTickCount();
c872d8c1 2530 EmSendCmdEx(rATQA, sizeof(rATQA), (receivedCmd[0] == ISO14443A_CMD_WUPA));
d2f487af 2531 cardSTATE = MFEMUL_SELECT1;
2532
2533 // init crypto block
2534 LED_B_OFF();
2535 LED_C_OFF();
2536 crypto1_destroy(pcs);
2537 cardAUTHKEY = 0xff;
2538 continue;
0a39986e 2539 }
7bc95e2e 2540
50193c1e 2541 switch (cardSTATE) {
d2f487af 2542 case MFEMUL_NOFIELD:
2543 case MFEMUL_HALTED:
50193c1e 2544 case MFEMUL_IDLE:{
6a1f2d82 2545 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
50193c1e
M
2546 break;
2547 }
2548 case MFEMUL_SELECT1:{
76ef5273 2549 // select all - 0x93 0x20
2550 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT && receivedCmd[1] == 0x20)) {
d2f487af 2551 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
9ca155ba 2552 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
0014cb46 2553 break;
9ca155ba
M
2554 }
2555
76ef5273 2556 // select card - 0x93 0x70 ...
2557 if (len == 9 &&
2558 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2559 if (MF_DBGLEVEL >= 4)
2560 Dbprintf("SELECT %02x%02x%02x%02x received",receivedCmd[2],receivedCmd[3],receivedCmd[4],receivedCmd[5]);
2561
c872d8c1 2562 switch(_UID_LEN) {
2563 case 4:
2564 cardSTATE = MFEMUL_WORK;
2565 LED_B_ON();
2566 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
76ef5273 2567 EmSendCmd(rSAKfinal, sizeof(rSAKfinal));
c872d8c1 2568 break;
2569 case 7:
2570 cardSTATE = MFEMUL_SELECT2;
2571 EmSendCmd(rSAK1, sizeof(rSAK1));
2572 break;
2573 case 10:
2574 cardSTATE = MFEMUL_SELECT2;
76ef5273 2575 EmSendCmd(rSAK1, sizeof(rSAK1));
c872d8c1 2576 break;
2577 default:break;
8556b852 2578 }
c872d8c1 2579 } else {
2580 cardSTATE_TO_IDLE();
9ca155ba 2581 }
50193c1e
M
2582 break;
2583 }
c872d8c1 2584 case MFEMUL_SELECT3:{
2585 if (!len) {
2586 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2587 break;
2588 }
76ef5273 2589 // select all cl3 - 0x97 0x20
c872d8c1 2590 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 && receivedCmd[1] == 0x20)) {
2591 EmSendCmd(rUIDBCC3, sizeof(rUIDBCC3));
2592 break;
2593 }
76ef5273 2594 // select card cl3 - 0x97 0x70
c872d8c1 2595 if (len == 9 &&
2596 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 &&
2597 receivedCmd[1] == 0x70 &&
2598 memcmp(&receivedCmd[2], rUIDBCC3, 4) == 0) ) {
2599
76ef5273 2600 EmSendCmd(rSAKfinal, sizeof(rSAKfinal));
c872d8c1 2601 cardSTATE = MFEMUL_WORK;
2602 LED_B_ON();
2603 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol3 time: %d", GetTickCount() - selTimer);
2604 break;
2605 }
2606 cardSTATE_TO_IDLE();
2607 break;
2608 }
d2f487af 2609 case MFEMUL_AUTH1:{
76ef5273 2610 if( len != 8) {
d2f487af 2611 cardSTATE_TO_IDLE();
6a1f2d82 2612 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2613 break;
2614 }
0c8d25eb 2615
c872d8c1 2616 uint32_t nr = bytes_to_num(receivedCmd, 4);
2617 uint32_t ar = bytes_to_num(&receivedCmd[4], 4);
79dcb9e0 2618
76ef5273 2619 // Collect AR/NR per keytype & sector
79dcb9e0 2620 if(flags & FLAG_NR_AR_ATTACK) {
2621 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
6eae192c 2622 if ( ar_nr_collected[i+mM]==0 || ((cardAUTHSC == ar_nr_resp[i+mM].sector) && (cardAUTHKEY == ar_nr_resp[i+mM].keytype) && (ar_nr_collected[i+mM] > 0)) ) {
c872d8c1 2623 // if first auth for sector, or matches sector and keytype of previous auth
2624 if (ar_nr_collected[i+mM] < 2) {
2625 // if we haven't already collected 2 nonces for this sector
2626 if (ar_nr_resp[ar_nr_collected[i+mM]].ar != ar) {
2627 // Avoid duplicates... probably not necessary, ar should vary.
2628 if (ar_nr_collected[i+mM]==0) {
2629 // first nonce collect
2630 ar_nr_resp[i+mM].cuid = cuid;
2631 ar_nr_resp[i+mM].sector = cardAUTHSC;
2632 ar_nr_resp[i+mM].keytype = cardAUTHKEY;
2633 ar_nr_resp[i+mM].nonce = nonce;
2634 ar_nr_resp[i+mM].nr = nr;
2635 ar_nr_resp[i+mM].ar = ar;
2636 nonce1_count++;
76ef5273 2637 // add this nonce to first moebius nonce
c872d8c1 2638 ar_nr_resp[i+ATTACK_KEY_COUNT].cuid = cuid;
2639 ar_nr_resp[i+ATTACK_KEY_COUNT].sector = cardAUTHSC;
2640 ar_nr_resp[i+ATTACK_KEY_COUNT].keytype = cardAUTHKEY;
2641 ar_nr_resp[i+ATTACK_KEY_COUNT].nonce = nonce;
2642 ar_nr_resp[i+ATTACK_KEY_COUNT].nr = nr;
2643 ar_nr_resp[i+ATTACK_KEY_COUNT].ar = ar;
2644 ar_nr_collected[i+ATTACK_KEY_COUNT]++;
76ef5273 2645 } else { // second nonce collect (std and moebius)
c872d8c1 2646 ar_nr_resp[i+mM].nonce2 = nonce;
2647 ar_nr_resp[i+mM].nr2 = nr;
2648 ar_nr_resp[i+mM].ar2 = ar;
6eae192c 2649 if (!gettingMoebius) {
c872d8c1 2650 nonce2_count++;
76ef5273 2651 // check if this was the last second nonce we need for std attack
c872d8c1 2652 if ( nonce2_count == nonce1_count ) {
76ef5273 2653 // done collecting std test switch to moebius
2654 // first finish incrementing last sample
6eae192c 2655 ar_nr_collected[i+mM]++;
76ef5273 2656 // switch to moebius collection
6eae192c 2657 gettingMoebius = true;
c872d8c1 2658 mM = ATTACK_KEY_COUNT;
2659 nonce = nonce*7;
6eae192c 2660 break;
c872d8c1 2661 }
2662 } else {
2663 moebius_n_count++;
76ef5273 2664 // if we've collected all the nonces we need - finish.
c872d8c1 2665 if (nonce1_count == moebius_n_count) finished = true;
2666 }
79dcb9e0 2667 }
c872d8c1 2668 ar_nr_collected[i+mM]++;
79dcb9e0 2669 }
2670 }
6eae192c 2671 // we found right spot for this nonce stop looking
2672 break;
79dcb9e0 2673 }
d2f487af 2674 }
2675 }
6eae192c 2676
d2f487af 2677 // --- crypto
c872d8c1 2678 crypto1_word(pcs, nr , 1);
2679 cardRr = ar ^ crypto1_word(pcs, 0, 0);
d2f487af 2680
2681 // test if auth OK
2682 if (cardRr != prng_successor(nonce, 64)){
b03c0f2d 2683 if (MF_DBGLEVEL >= 2) Dbprintf("AUTH FAILED for sector %d with key %c. cardRr=%08x, succ=%08x",
2684 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2685 cardRr, prng_successor(nonce, 64));
7bc95e2e 2686 // Shouldn't we respond anything here?
d2f487af 2687 // Right now, we don't nack or anything, which causes the
2688 // reader to do a WUPA after a while. /Martin
b03c0f2d 2689 // -- which is the correct response. /piwi
d2f487af 2690 cardSTATE_TO_IDLE();
6a1f2d82 2691 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
d2f487af 2692 break;
2693 }
2694
79dcb9e0 2695 //auth successful
d2f487af 2696 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2697
2698 num_to_bytes(ans, 4, rAUTH_AT);
2699 // --- crypto
2700 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2701 LED_C_ON();
2702 cardSTATE = MFEMUL_WORK;
b03c0f2d 2703 if (MF_DBGLEVEL >= 4) Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2704 cardAUTHSC, cardAUTHKEY == 0 ? 'A' : 'B',
2705 GetTickCount() - authTimer);
d2f487af 2706 break;
2707 }
50193c1e 2708 case MFEMUL_SELECT2:{
7bc95e2e 2709 if (!len) {
6a1f2d82 2710 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2711 break;
76ef5273 2712 }
2713 // select all cl2 - 0x95 0x20
2714 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 && receivedCmd[1] == 0x20)) {
9ca155ba 2715 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
8556b852
M
2716 break;
2717 }
9ca155ba 2718
76ef5273 2719 // select cl2 card - 0x95 0x70 xxxxxxxxxxxx
8556b852 2720 if (len == 9 &&
76ef5273 2721 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 && receivedCmd[1] == 0x70 && memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0)) {
c872d8c1 2722 switch(_UID_LEN) {
2723 case 7:
76ef5273 2724 EmSendCmd(rSAKfinal, sizeof(rSAKfinal));
c872d8c1 2725 cardSTATE = MFEMUL_WORK;
2726 LED_B_ON();
2727 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2728 break;
2729 case 10:
76ef5273 2730 EmSendCmd(rSAK1, sizeof(rSAK1));
c872d8c1 2731 cardSTATE = MFEMUL_SELECT3;
2732 break;
2733 default:break;
2734 }
8556b852
M
2735 break;
2736 }
0014cb46
M
2737
2738 // i guess there is a command). go into the work state.
7bc95e2e 2739 if (len != 4) {
6a1f2d82 2740 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2741 break;
2742 }
0014cb46 2743 cardSTATE = MFEMUL_WORK;
d2f487af 2744 //goto lbWORK;
2745 //intentional fall-through to the next case-stmt
50193c1e 2746 }
51969283 2747
7bc95e2e 2748 case MFEMUL_WORK:{
2749 if (len == 0) {
6a1f2d82 2750 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2751 break;
2752 }
2753
d2f487af 2754 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2755
7bc95e2e 2756 if(encrypted_data) {
51969283
M
2757 // decrypt seqence
2758 mf_crypto1_decrypt(pcs, receivedCmd, len);
d2f487af 2759 }
7bc95e2e 2760
d2f487af 2761 if (len == 4 && (receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61)) {
6eae192c 2762
2763 // if authenticating to a block that shouldn't exist - as long as we are not doing the reader attack
2764 if (receivedCmd[1] >= 16 * 4 && !(flags & FLAG_NR_AR_ATTACK)) {
c872d8c1 2765 //is this the correct response to an auth on a out of range block? marshmellow
2766 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2767 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2768 break;
2769 }
2770
d2f487af 2771 authTimer = GetTickCount();
2772 cardAUTHSC = receivedCmd[1] / 4; // received block num
2773 cardAUTHKEY = receivedCmd[0] - 0x60;
2774 crypto1_destroy(pcs);//Added by martin
2775 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
c872d8c1 2776 //uint64_t key=emlGetKey(cardAUTHSC, cardAUTHKEY);
2777 //Dbprintf("key: %04x%08x",(uint32_t)(key>>32)&0xFFFF,(uint32_t)(key&0xFFFFFFFF));
51969283 2778
d2f487af 2779 if (!encrypted_data) { // first authentication
b03c0f2d 2780 if (MF_DBGLEVEL >= 4) Dbprintf("Reader authenticating for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
51969283 2781
d2f487af 2782 crypto1_word(pcs, cuid ^ nonce, 0);//Update crypto state
2783 num_to_bytes(nonce, 4, rAUTH_AT); // Send nonce
7bc95e2e 2784 } else { // nested authentication
b03c0f2d 2785 if (MF_DBGLEVEL >= 4) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %d",receivedCmd[1] ,receivedCmd[1],cardAUTHKEY );
7bc95e2e 2786 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
d2f487af 2787 num_to_bytes(ans, 4, rAUTH_AT);
2788 }
0c8d25eb 2789
d2f487af 2790 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2791 //Dbprintf("Sending rAUTH %02x%02x%02x%02x", rAUTH_AT[0],rAUTH_AT[1],rAUTH_AT[2],rAUTH_AT[3]);
2792 cardSTATE = MFEMUL_AUTH1;
2793 break;
51969283 2794 }
7bc95e2e 2795
8f51ddb0
M
2796 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2797 // BUT... ACK --> NACK
2798 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2799 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2800 break;
2801 }
2802
2803 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2804 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2805 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2806 break;
0a39986e
M
2807 }
2808
7bc95e2e 2809 if(len != 4) {
6a1f2d82 2810 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
7bc95e2e 2811 break;
2812 }
d2f487af 2813
2814 if(receivedCmd[0] == 0x30 // read block
2815 || receivedCmd[0] == 0xA0 // write block
b03c0f2d 2816 || receivedCmd[0] == 0xC0 // inc
2817 || receivedCmd[0] == 0xC1 // dec
2818 || receivedCmd[0] == 0xC2 // restore
7bc95e2e 2819 || receivedCmd[0] == 0xB0) { // transfer
2820 if (receivedCmd[1] >= 16 * 4) {
d2f487af 2821 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
e35031d2 2822 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2823 break;
2824 }
2825
7bc95e2e 2826 if (receivedCmd[1] / 4 != cardAUTHSC) {
8f51ddb0 2827 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
e35031d2 2828 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate (0x%02x) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
8f51ddb0
M
2829 break;
2830 }
d2f487af 2831 }
2832 // read block
2833 if (receivedCmd[0] == 0x30) {
b03c0f2d 2834 if (MF_DBGLEVEL >= 4) {
d2f487af 2835 Dbprintf("Reader reading block %d (0x%02x)",receivedCmd[1],receivedCmd[1]);
2836 }
8f51ddb0
M
2837 emlGetMem(response, receivedCmd[1], 1);
2838 AppendCrc14443a(response, 16);
6a1f2d82 2839 mf_crypto1_encrypt(pcs, response, 18, response_par);
2840 EmSendCmdPar(response, 18, response_par);
d2f487af 2841 numReads++;
7bc95e2e 2842 if(exitAfterNReads > 0 && numReads == exitAfterNReads) {
d2f487af 2843 Dbprintf("%d reads done, exiting", numReads);
2844 finished = true;
2845 }
0a39986e
M
2846 break;
2847 }
0a39986e 2848 // write block
d2f487af 2849 if (receivedCmd[0] == 0xA0) {
b03c0f2d 2850 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)",receivedCmd[1],receivedCmd[1]);
8f51ddb0 2851 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
8f51ddb0
M
2852 cardSTATE = MFEMUL_WRITEBL2;
2853 cardWRBL = receivedCmd[1];
0a39986e 2854 break;
7bc95e2e 2855 }
0014cb46 2856 // increment, decrement, restore
d2f487af 2857 if (receivedCmd[0] == 0xC0 || receivedCmd[0] == 0xC1 || receivedCmd[0] == 0xC2) {
b03c0f2d 2858 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
d2f487af 2859 if (emlCheckValBl(receivedCmd[1])) {
2860 if (MF_DBGLEVEL >= 2) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
0014cb46
M
2861 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2862 break;
2863 }
2864 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2865 if (receivedCmd[0] == 0xC1)
2866 cardSTATE = MFEMUL_INTREG_INC;
2867 if (receivedCmd[0] == 0xC0)
2868 cardSTATE = MFEMUL_INTREG_DEC;
2869 if (receivedCmd[0] == 0xC2)
2870 cardSTATE = MFEMUL_INTREG_REST;
2871 cardWRBL = receivedCmd[1];
0014cb46
M
2872 break;
2873 }
0014cb46 2874 // transfer
d2f487af 2875 if (receivedCmd[0] == 0xB0) {
b03c0f2d 2876 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
0014cb46
M
2877 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2878 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2879 else
2880 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
0014cb46
M
2881 break;
2882 }
9ca155ba 2883 // halt
d2f487af 2884 if (receivedCmd[0] == 0x50 && receivedCmd[1] == 0x00) {
9ca155ba 2885 LED_B_OFF();
0a39986e 2886 LED_C_OFF();
0014cb46
M
2887 cardSTATE = MFEMUL_HALTED;
2888 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
6a1f2d82 2889 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0a39986e 2890 break;
9ca155ba 2891 }
d2f487af 2892 // RATS
2893 if (receivedCmd[0] == 0xe0) {//RATS
8f51ddb0
M
2894 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2895 break;
2896 }
d2f487af 2897 // command not allowed
2898 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2899 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
51969283 2900 break;
8f51ddb0
M
2901 }
2902 case MFEMUL_WRITEBL2:{
2903 if (len == 18){
2904 mf_crypto1_decrypt(pcs, receivedCmd, len);
2905 emlSetMem(receivedCmd, cardWRBL, 1);
2906 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2907 cardSTATE = MFEMUL_WORK;
51969283 2908 } else {
0014cb46 2909 cardSTATE_TO_IDLE();
6a1f2d82 2910 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
8f51ddb0 2911 }
8f51ddb0 2912 break;
50193c1e 2913 }
0014cb46
M
2914
2915 case MFEMUL_INTREG_INC:{
2916 mf_crypto1_decrypt(pcs, receivedCmd, len);
2917 memcpy(&ans, receivedCmd, 4);
2918 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2919 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2920 cardSTATE_TO_IDLE();
2921 break;
7bc95e2e 2922 }
6a1f2d82 2923 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2924 cardINTREG = cardINTREG + ans;
2925 cardSTATE = MFEMUL_WORK;
2926 break;
2927 }
2928 case MFEMUL_INTREG_DEC:{
2929 mf_crypto1_decrypt(pcs, receivedCmd, len);
2930 memcpy(&ans, receivedCmd, 4);
2931 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2932 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2933 cardSTATE_TO_IDLE();
2934 break;
2935 }
6a1f2d82 2936 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2937 cardINTREG = cardINTREG - ans;
2938 cardSTATE = MFEMUL_WORK;
2939 break;
2940 }
2941 case MFEMUL_INTREG_REST:{
2942 mf_crypto1_decrypt(pcs, receivedCmd, len);
2943 memcpy(&ans, receivedCmd, 4);
2944 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2945 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2946 cardSTATE_TO_IDLE();
2947 break;
2948 }
6a1f2d82 2949 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
0014cb46
M
2950 cardSTATE = MFEMUL_WORK;
2951 break;
2952 }
50193c1e 2953 }
73ab92d1 2954 button_pushed = BUTTON_PRESS();
50193c1e
M
2955 }
2956
9ca155ba
M
2957 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2958 LEDsoff();
2959
76ef5273 2960 if(flags & FLAG_NR_AR_ATTACK && MF_DBGLEVEL >= 1) {
79dcb9e0 2961 for ( uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
2962 if (ar_nr_collected[i] == 2) {
2963 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
2964 Dbprintf("../tools/mfkey/mfkey32 %08x %08x %08x %08x %08x %08x",
2965 ar_nr_resp[i].cuid, //UID
2966 ar_nr_resp[i].nonce, //NT
79dcb9e0 2967 ar_nr_resp[i].nr, //NR1
c872d8c1 2968 ar_nr_resp[i].ar, //AR1
2969 ar_nr_resp[i].nr2, //NR2
2970 ar_nr_resp[i].ar2 //AR2
d2f487af 2971 );
2972 }
79dcb9e0 2973 }
c872d8c1 2974 for ( uint8_t i = ATTACK_KEY_COUNT; i < ATTACK_KEY_COUNT*2; i++) {
2975 if (ar_nr_collected[i] == 2) {
2976 Dbprintf("Collected two pairs of AR/NR which can be used to extract %s from reader for sector %d:", (i<ATTACK_KEY_COUNT/2) ? "keyA" : "keyB", ar_nr_resp[i].sector);
2977 Dbprintf("../tools/mfkey/mfkey32v2 %08x %08x %08x %08x %08x %08x %08x",
2978 ar_nr_resp[i].cuid, //UID
2979 ar_nr_resp[i].nonce, //NT
2980 ar_nr_resp[i].nr, //NR1
2981 ar_nr_resp[i].ar, //AR1
2982 ar_nr_resp[i].nonce2,//NT2
2983 ar_nr_resp[i].nr2, //NR2
2984 ar_nr_resp[i].ar2 //AR2
2985 );
2986 }
2987 }
d2f487af 2988 }
3000dc4e 2989 if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
79dcb9e0 2990
76ef5273 2991 if(flags & FLAG_INTERACTIVE) { // Interactive mode flag, means we need to send ACK
c872d8c1 2992 //Send the collected ar_nr in the response
73ab92d1 2993 cmd_send(CMD_ACK,CMD_SIMULATE_MIFARE_CARD,button_pushed,0,&ar_nr_resp,sizeof(ar_nr_resp));
79dcb9e0 2994 }
15c4dc5a 2995}
b62a5a84 2996
d2f487af 2997
b62a5a84
M
2998//-----------------------------------------------------------------------------
2999// MIFARE sniffer.
3000//
3001//-----------------------------------------------------------------------------
5cd9ec01
M
3002void RAMFUNC SniffMifare(uint8_t param) {
3003 // param:
3004 // bit 0 - trigger from first card answer
3005 // bit 1 - trigger from first reader 7-bit request
39864b0b
M
3006
3007 // C(red) A(yellow) B(green)
b62a5a84
M
3008 LEDsoff();
3009 // init trace buffer
3000dc4e
MHS
3010 clear_trace();
3011 set_tracing(TRUE);
b62a5a84 3012
b62a5a84
M
3013 // The command (reader -> tag) that we're receiving.
3014 // The length of a received command will in most cases be no more than 18 bytes.
3015 // So 32 should be enough!
f71f4deb 3016 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
3017 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
b62a5a84 3018 // The response (tag -> reader) that we're receiving.
f71f4deb 3019 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
3020 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
b62a5a84 3021
09ffd16e 3022 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
3023
f71f4deb 3024 // free eventually allocated BigBuf memory
3025 BigBuf_free();
3026 // allocate the DMA buffer, used to stream samples from the FPGA
3027 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 3028 uint8_t *data = dmaBuf;
3029 uint8_t previous_data = 0;
5cd9ec01
M
3030 int maxDataLen = 0;
3031 int dataLen = 0;
7bc95e2e 3032 bool ReaderIsActive = FALSE;
3033 bool TagIsActive = FALSE;
3034
b62a5a84 3035 // Set up the demodulator for tag -> reader responses.
6a1f2d82 3036 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
3037
3038 // Set up the demodulator for the reader -> tag commands
6a1f2d82 3039 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
3040
3041 // Setup for the DMA.
7bc95e2e 3042 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 3043
b62a5a84 3044 LED_D_OFF();
39864b0b
M
3045
3046 // init sniffer
3047 MfSniffInit();
b62a5a84 3048
b62a5a84 3049 // And now we loop, receiving samples.
7bc95e2e 3050 for(uint32_t sniffCounter = 0; TRUE; ) {
3051
5cd9ec01
M
3052 if(BUTTON_PRESS()) {
3053 DbpString("cancelled by button");
7bc95e2e 3054 break;
5cd9ec01
M
3055 }
3056
b62a5a84
M
3057 LED_A_ON();
3058 WDT_HIT();
39864b0b 3059
7bc95e2e 3060 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3061 // check if a transaction is completed (timeout after 2000ms).
3062 // if yes, stop the DMA transfer and send what we have so far to the client
3063 if (MfSniffSend(2000)) {
3064 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3065 sniffCounter = 0;
3066 data = dmaBuf;
3067 maxDataLen = 0;
3068 ReaderIsActive = FALSE;
3069 TagIsActive = FALSE;
3070 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 3071 }
39864b0b 3072 }
7bc95e2e 3073
3074 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3075 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
3076 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
3077 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
3078 } else {
3079 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
5cd9ec01
M
3080 }
3081 // test for length of buffer
7bc95e2e 3082 if(dataLen > maxDataLen) { // we are more behind than ever...
3083 maxDataLen = dataLen;
f71f4deb 3084 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 3085 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 3086 break;
b62a5a84
M
3087 }
3088 }
5cd9ec01 3089 if(dataLen < 1) continue;
b62a5a84 3090
7bc95e2e 3091 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
3092 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3093 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3094 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
55acbb2a 3095 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
3096 }
3097 // secondary buffer sets as primary, secondary buffer was stopped
3098 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3099 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
3100 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3101 }
5cd9ec01
M
3102
3103 LED_A_OFF();
b62a5a84 3104
7bc95e2e 3105 if (sniffCounter & 0x01) {
b62a5a84 3106
7bc95e2e 3107 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
3108 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3109 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3110 LED_C_INV();
6a1f2d82 3111 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
b62a5a84 3112
7bc95e2e 3113 /* And ready to receive another command. */
05ddb52c 3114 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3115
3116 /* And also reset the demod code */
3117 DemodReset();
3118 }
3119 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3120 }
3121
3122 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
3123 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3124 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3125 LED_C_INV();
b62a5a84 3126
6a1f2d82 3127 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
39864b0b 3128
7bc95e2e 3129 // And ready to receive another response.
3130 DemodReset();
48ece4a7 3131 // And reset the Miller decoder including its (now outdated) input buffer
3132 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 3133 }
3134 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3135 }
b62a5a84
M
3136 }
3137
7bc95e2e 3138 previous_data = *data;
3139 sniffCounter++;
5cd9ec01 3140 data++;
d714d3ef 3141 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01 3142 data = dmaBuf;
b62a5a84 3143 }
7bc95e2e 3144
b62a5a84
M
3145 } // main cycle
3146
3147 DbpString("COMMAND FINISHED");
3148
55acbb2a 3149 FpgaDisableSscDma();
39864b0b
M
3150 MfSniffEnd();
3151
7bc95e2e 3152 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
b62a5a84 3153 LEDsoff();
3803d529 3154}
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