cleanup clocks

diff --git a/galaxian/src/dcm.v b/galaxian/src/dcm.v
index 64541bcaca24aa1c5a006d4b1e19d73c037af158..9f51aedf41caad9bcf0ce8f6f54da05c2bb403a5 100644 (file)
--- a/galaxian/src/dcm.v
+++ b/galaxian/src/dcm.v
@@ -55,7 +55,7 @@ module mc_dcm(CLKIN_IN,
                        .STATUS());
    defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
    defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
                        .STATUS());
    defparam DCM_SP_INST.CLK_FEEDBACK = "1X";
    defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;

-   defparam DCM_SP_INST.CLKFX_DIVIDE = 27;
+   defparam DCM_SP_INST.CLKFX_DIVIDE = 13;

    defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
    defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
    defparam DCM_SP_INST.CLKIN_PERIOD = 8.000;
    defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
    defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
    defparam DCM_SP_INST.CLKIN_PERIOD = 8.000;

diff --git a/galaxian/src/mc_adec.v b/galaxian/src/mc_adec.v
index 65525ba1e207f48c7b5a5da12be72cf7715446d1..2fa91fd8b8d2a1e800083d22b33ac05e92f30b62 100644 (file)
--- a/galaxian/src/mc_adec.v
+++ b/galaxian/src/mc_adec.v
@@ -137,8 +137,8 @@ wire   W_NMI_ONn = W_9N_Q[1]; //  galaxian
 reg    W_6S1_Q,W_6S1_Qn;\r
 reg    W_6S2_Qn;\r
 \r
 reg    W_6S1_Q,W_6S1_Qn;\r
 reg    W_6S2_Qn;\r
 \r

-//assign O_WAITn = W_6S1_Qn;\r
-assign O_WAITn = 1'b1 ; // No Wait\r
+assign O_WAITn = W_6S1_Qn;\r
+//assign O_WAITn = 1'b1 ; // No Wait\r

 \r
 always@(posedge I_CPU_CLK or negedge I_V_BLn)\r
 begin\r
 \r
 always@(posedge I_CPU_CLK or negedge I_V_BLn)\r
 begin\r

diff --git a/galaxian/src/mc_bram_if.v b/galaxian/src/mc_bram_if.v
index 8476f25cd30574977e6f625aed2cd617aff2a06f..1374c92c18571dbfc640547478f4838dee7b05cd 100644 (file)
--- a/galaxian/src/mc_bram_if.v
+++ b/galaxian/src/mc_bram_if.v
@@ -266,7 +266,7 @@ alt_ram_256_5 LRAM(
 .outclock(~I_CLK),\r
 .address(I_ADDR),\r
 .data(I_D),\r
 .outclock(~I_CLK),\r
 .address(I_ADDR),\r
 .data(I_D),\r

-.wren(I_WE),\r
+.wren(~I_WE),\r

 .q(W_D)\r
 \r
 );\r
 .q(W_D)\r
 \r
 );\r


@@ -282,7 +282,7 @@ RAMB4_S8 LRAM(
 .DI({3'b000,I_D}),\r
 .DO(W_D),\r
 .EN(1'b1),\r
 .DI({3'b000,I_D}),\r
 .DO(W_D),\r
 .EN(1'b1),\r

-.WE(I_WE),\r
+.WE(~I_WE),\r

 .RST(1'b0)\r
 \r
 );\r
 .RST(1'b0)\r
 \r
 );\r

diff --git a/galaxian/src/mc_clock.v b/galaxian/src/mc_clock.v
index 43cadb42e86b73f13c84ee474619f0163bfd20f5..a88d95c0ebe39e892df205613d666f958cd4c835 100644 (file)
--- a/galaxian/src/mc_clock.v
+++ b/galaxian/src/mc_clock.v
@@ -17,47 +17,61 @@
 \r
 module mc_clock(\r
 \r
 \r
 module mc_clock(\r
 \r

-I_CLK_18M,\r
+I_CLK_36M,\r
+O_CLK_18M,\r

 O_CLK_12M,\r
 O_CLK_12M,\r

-O_CLK_06M,\r
-O_CLK_06Mn\r
+O_CLK_06M\r

 \r
 );\r
 \r
 \r
 );\r
 \r

-input  I_CLK_18M;\r
+input I_CLK_36M;\r
+output O_CLK_18M;\r

 output O_CLK_12M;\r
 output O_CLK_06M;\r
 output O_CLK_12M;\r
 output O_CLK_06M;\r

-output O_CLK_06Mn;\r

 \r
 // 2/3 clock divider(duty 33%)\r
 \r
 // 2/3 clock divider(duty 33%)\r

-reg [1:0] clk_ff1,clk_ff2;\r

 //I_CLK   1010101010101010101\r
 //c_ff10  0011110011110011110\r
 //c_ff11  0011000011000011000\r
 //c_ff20  0000110000110000110\r
 //c_ff21  0110000110000110000\r
 //O_12M   0000110110110110110\r
 //I_CLK   1010101010101010101\r
 //c_ff10  0011110011110011110\r
 //c_ff11  0011000011000011000\r
 //c_ff20  0000110000110000110\r
 //c_ff21  0110000110000110000\r
 //O_12M   0000110110110110110\r

-always @(posedge I_CLK_18M)\r
+reg [1:0] state;\r
+reg clk_12m;\r
+initial state = 0;\r
+initial clk_12m = 0;\r
+\r
+// 2/3 clock         (duty 66%)\r
+always @(negedge I_CLK_36M)\r

 begin\r
 begin\r

-   clk_ff1[0] <= ~clk_ff1[0] | clk_ff1[1];\r
-   clk_ff1[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r
-   clk_ff2[0] <= clk_ff1[0] & clk_ff1[1];\r
+   case (state)\r
+      2'd0: state <= 2'd1;\r
+      2'd1: state <= 2'd2;\r
+      2'd2: state <= 2'd0;\r
+      2'd3: state <= 2'd0;\r
+   endcase\r
+\r
+   if (state == 2'd2)\r
+      clk_12m = 1;\r
+   else\r
+      clk_12m = 0;\r

 end\r
 end\r

-always @(negedge I_CLK_18M)\r
-   clk_ff2[1] <= ~clk_ff1[0] & ~clk_ff1[1];\r

 \r
 \r

-// 2/3 clock         (duty 66%)\r
-assign O_CLK_12M = clk_ff2[0]| clk_ff2[1];\r
- \r
+assign O_CLK_12M = clk_12m;\r
+\r
+reg CLK_18M;\r
+always @(posedge I_CLK_36M)\r
+begin\r
+   CLK_18M <= ~ CLK_18M;\r
+end\r
+assign O_CLK_18M = CLK_18M;\r
+\r

 // 1/3 clock divider (duty 50%)\r
 // 1/3 clock divider (duty 50%)\r

-reg CLK_6M , CLK_6Mn;\r
+reg CLK_6M;\r

 always @(posedge O_CLK_12M)\r
 begin\r
 always @(posedge O_CLK_12M)\r
 begin\r

-   CLK_6Mn <=  CLK_6M;\r

    CLK_6M  <= ~CLK_6M;\r
 end\r
 assign O_CLK_06M = CLK_6M;\r
    CLK_6M  <= ~CLK_6M;\r
 end\r
 assign O_CLK_06M = CLK_6M;\r

-assign O_CLK_06Mn = CLK_6Mn;\r
-\r

 \r
 \r

-endmodule
\ No newline at end of file
+endmodule\r

diff --git a/galaxian/src/mc_hv_count.v b/galaxian/src/mc_hv_count.v
index aa34b406b3fadcb565f3b181b6137d9f3cdf1da3..06f30233e85d671c5ce90eba4e0f838e62096d48 100644 (file)
--- a/galaxian/src/mc_hv_count.v
+++ b/galaxian/src/mc_hv_count.v
@@ -61,12 +61,11 @@ assign O_H_CNT  = H_CNT[8:0];
 \r
 //-------   H_SYNC     ----------------------------------------\r
 \r
 \r
 //-------   H_SYNC     ----------------------------------------\r
 \r

-reg    H_SYNCn;\r
-wire   H_SYNC = ~H_SYNCn;\r
+reg    H_SYNC;\r

 always@(posedge H_CNT[4] or negedge H_CNT[8]) \r
 begin\r
 always@(posedge H_CNT[4] or negedge H_CNT[8]) \r
 begin\r

-   if(H_CNT[8]==1'b0) H_SYNCn <= 1'b1;\r
-   else   H_SYNCn <= ~(~H_CNT[6]& H_CNT[5]);\r
+   if(H_CNT[8]==1'b0) H_SYNC <= 1'b0;\r
+   else   H_SYNC <= (~H_CNT[6]& H_CNT[5]);\r

 end\r
 \r
 assign O_H_SYNC = H_SYNC;\r
 end\r
 \r
 assign O_H_SYNC = H_SYNC;\r


@@ -124,4 +123,4 @@ assign O_V_BL2n = V_BL2n;
 \r
 assign O_C_BLn = ~(~V_BLn | H_CNT[8]);\r
 \r
 \r
 assign O_C_BLn = ~(~V_BLn | H_CNT[8]);\r
 \r

-endmodule
\ No newline at end of file
+endmodule\r

diff --git a/galaxian/src/mc_ld_pls.v b/galaxian/src/mc_ld_pls.v
index 51a2934e438d7ce3ddef63b703822e54ac99ea96..01fc558006e7436ba4c469ed9b8f56db96ecda3c 100644 (file)
--- a/galaxian/src/mc_ld_pls.v
+++ b/galaxian/src/mc_ld_pls.v
@@ -46,7 +46,7 @@ output O_MLDn;
 output O_SLDn;\r
 \r
 reg    W_5C_Q;\r
 output O_SLDn;\r
 \r
 reg    W_5C_Q;\r

-always@(posedge I_CLK_6M)\r
+always@(negedge I_CLK_6M)\r

    W_5C_Q <= I_H_CNT[0];\r
 \r
 //    Parts 4D\r
    W_5C_Q <= I_H_CNT[0];\r
 \r
 //    Parts 4D\r


@@ -83,7 +83,7 @@ logic_74xx139 U_4C1(
 );\r
 \r
 reg    W_4C1_Q3;\r
 );\r
 \r
 reg    W_4C1_Q3;\r

-always@(negedge I_CLK_6M)    // 2004-9-22 added\r
+always@(posedge  I_CLK_6M)    // 2004-9-22 added\r

    W_4C1_Q3 <= W_4C1_Q[3];\r
 \r
 reg    W_4C2_B;\r
    W_4C1_Q3 <= W_4C1_Q[3];\r
 \r
 reg    W_4C2_B;\r

diff --git a/galaxian/src/mc_top.v b/galaxian/src/mc_top.v
index 99a4a6aa911479a125de90de30e64aa00dccc672..4cabd744bd9af09ff10b09f4be993047ba89da7c 100644 (file)
--- a/galaxian/src/mc_top.v
+++ b/galaxian/src/mc_top.v
@@ -89,7 +89,8 @@ output O_VGA_V_SYNCn;
 \r
 wire   W_RESETn = |(~I_PSW[8:5]);\r
 //------ CLOCK GEN ---------------------------\r
 \r
 wire   W_RESETn = |(~I_PSW[8:5]);\r
 //------ CLOCK GEN ---------------------------\r

-wire   I_CLK_18432M;\r
+wire   W_CLK_18M;\r
+wire   W_CLK_36M;\r

 wire   W_CLK_12M,WB_CLK_12M;\r
 wire   W_CLK_6M,WB_CLK_6M;\r
 wire   W_STARS_CLK;\r
 wire   W_CLK_12M,WB_CLK_12M;\r
 wire   W_CLK_6M,WB_CLK_6M;\r
 wire   W_STARS_CLK;\r


@@ -97,7 +98,7 @@ wire   W_STARS_CLK;
 mc_dcm clockgen(\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r
 mc_dcm clockgen(\r
 .CLKIN_IN(I_CLK_125M),\r
 .RST_IN(! W_RESETn),\r

-.CLKFX_OUT(I_CLK_18432M)\r
+.CLKFX_OUT(W_CLK_36M)\r

 );\r
 \r
 //------ H&V COUNTER -------------------------\r
 );\r
 \r
 //------ H&V COUNTER -------------------------\r


@@ -144,7 +145,8 @@ wire   [7:0]W_VID_DO;
 \r
 mc_clock MC_CLK(\r
 \r
 \r
 mc_clock MC_CLK(\r
 \r

-.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_36M(W_CLK_36M),\r
+.O_CLK_18M(W_CLK_18M),\r

 .O_CLK_12M(WB_CLK_12M),\r
 .O_CLK_06M(WB_CLK_6M)\r
 \r
 .O_CLK_12M(WB_CLK_12M),\r
 .O_CLK_06M(WB_CLK_6M)\r
 \r


@@ -329,7 +331,7 @@ wire        VIB_SW = died & (&on_game[1:0]);
 \r
 fpga_arcade_if pspad(\r
 \r
 \r
 fpga_arcade_if pspad(\r
 \r

-.CLK_18M432(I_CLK_18432M),\r
+.CLK_18M432(W_CLK_18M),\r

 .I_RSTn(W_RESETn),\r
 .psCLK(psCLK),\r
 .psSEL(psSEL),\r
 .I_RSTn(W_RESETn),\r
 .psCLK(psCLK),\r
 .psSEL(psSEL),\r


@@ -444,7 +446,7 @@ wire   [1:0]W_VID;
 wire   [2:0]W_COL;\r
 \r
 mc_video MC_VID(\r
 wire   [2:0]W_COL;\r
 \r
 mc_video MC_VID(\r

-.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_18M(W_CLK_18M),\r

 .I_CLK_12M(W_CLK_12M),\r
 .I_CLK_6M(W_CLK_6M),\r
 .I_H_CNT(W_H_CNT),\r
 .I_CLK_12M(W_CLK_12M),\r
 .I_CLK_6M(W_CLK_6M),\r
 .I_H_CNT(W_H_CNT),\r


@@ -503,7 +505,7 @@ wire   [1:0]W_STARS_B;
 \r
 mc_stars MC_STARS( \r
 \r
 \r
 mc_stars MC_STARS( \r
 \r

-.I_CLK_18M(I_CLK_18432M),\r
+.I_CLK_18M(W_CLK_18M),\r

 `ifdef DEVICE_CYCLONE\r
 .I_CLK_6M(~WB_CLK_6M),\r
 `endif\r
 `ifdef DEVICE_CYCLONE\r
 .I_CLK_6M(~WB_CLK_6M),\r
 `endif\r


@@ -615,7 +617,7 @@ wire   [7:0]W_SDAT_B;
 \r
 mc_sound_b MC_SOUND_B(\r
 \r
 \r
 mc_sound_b MC_SOUND_B(\r
 \r

-.I_CLK1(I_CLK_18432M),\r
+.I_CLK1(W_CLK_18M),\r

 .I_CLK2(W_CLK_6M),\r
 .I_RSTn(rst_count[3]),\r
 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r
 .I_CLK2(W_CLK_6M),\r
 .I_RSTn(rst_count[3]),\r
 .I_SW({&on_game[1:0],W_HIT,W_FIRE}),\r


@@ -639,7 +641,7 @@ assign  O_SOUND_OUT_R = W_DAC_B;
 \r
 dac wav_dac_a(\r
 \r
 \r
 dac wav_dac_a(\r
 \r

-.Clk(I_CLK_18432M), \r
+.Clk(W_CLK_18M), \r

 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_A),\r
 .DACout(W_DAC_A)\r
 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_A),\r
 .DACout(W_DAC_A)\r


@@ -648,7 +650,7 @@ dac wav_dac_a(
 \r
 dac wav_dac_b(\r
 \r
 \r
 dac wav_dac_b(\r
 \r

-.Clk(I_CLK_18432M), \r
+.Clk(W_CLK_18M), \r

 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_B),\r
 .DACout(W_DAC_B)\r
 .Reset(~W_RESETn),\r
 .DACin(W_SDAT_B),\r
 .DACout(W_DAC_B)\r

diff --git a/galaxian/src/mc_video.v b/galaxian/src/mc_video.v
index c184923475107e739e9da4a4ad66d58fcc862f0a..a12155d55546a01330c8762c0ad6acc3d7f68898 100644 (file)
--- a/galaxian/src/mc_video.v
+++ b/galaxian/src/mc_video.v
@@ -119,7 +119,7 @@ end
 \r
 mc_ld_pls LD_PLS(\r
 \r
 \r
 mc_ld_pls LD_PLS(\r
 \r

-.I_CLK_6M(~I_CLK_6M),\r
+.I_CLK_6M(I_CLK_6M),\r

 .I_H_CNT(I_H_CNT),\r
 .I_3D_DI(W_3D),\r
 \r
 .I_H_CNT(I_H_CNT),\r
 .I_3D_DI(W_3D),\r
 \r


@@ -339,16 +339,14 @@ begin
 end\r
 \r
 wire   [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r
 end\r
 \r
 wire   [7:0]W_LRAM_A = W_45T_Q^{8{W_H_FLIP1X}};\r

-wire   W_LRAM_WE = ~I_CLK_6M;\r

 \r
 wire   [4:0]W_LRAM_DI;\r
 wire   [4:0]W_LRAM_DO;\r
 \r
 reg    [1:0]W_RV;\r
 reg    [2:0]W_RC;\r
 \r
 wire   [4:0]W_LRAM_DI;\r
 wire   [4:0]W_LRAM_DO;\r
 \r
 reg    [1:0]W_RV;\r
 reg    [2:0]W_RC;\r

-wire   W_1U_CLK = ~I_CLK_6M;\r

 \r
 \r

-always@(posedge W_1U_CLK)\r
+always@(negedge I_CLK_6M)\r

 begin\r
       W_RV <= W_LRAM_DO[1:0];    \r
       W_RC <= W_LRAM_DO[4:2];\r
 begin\r
       W_RV <= W_LRAM_DO[1:0];    \r
       W_RC <= W_LRAM_DO[4:2];\r


@@ -379,7 +377,7 @@ mc_lram LRAM(
 \r
 .I_CLK(I_CLK_18M),\r
 .I_ADDR(W_LRAM_A),\r
 \r
 .I_CLK(I_CLK_18M),\r
 .I_ADDR(W_LRAM_A),\r

-.I_WE(W_LRAM_WE),\r
+.I_WE(I_CLK_6M),\r

 .I_D(W_LRAM_DI),\r
 .O_Dn(W_LRAM_DO)\r
 \r
 .I_D(W_LRAM_DI),\r
 .O_Dn(W_LRAM_DO)\r
 \r