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15c4dc5a 1//-----------------------------------------------------------------------------
b62a5a84 2// Merlok - June 2011, 2012
15c4dc5a 3// Gerhard de Koning Gans - May 2008
534983d7 4// Hagen Fritsch - June 2010
bd20f8f4 5//
6// This code is licensed to you under the terms of the GNU GPL, version 2 or,
7// at your option, any later version. See the LICENSE.txt file for the text of
8// the license.
15c4dc5a 9//-----------------------------------------------------------------------------
bd20f8f4 10// Routines to support ISO 14443 type A.
11//-----------------------------------------------------------------------------
12
de77d4ac 13#include "iso14443a.h"
14
b7d3e899 15#include <stdio.h>
16#include <string.h>
e30c654b 17#include "proxmark3.h"
15c4dc5a 18#include "apps.h"
f7e3ed82 19#include "util.h"
902cb3c0 20#include "cmd.h"
15c4dc5a 21#include "iso14443crc.h"
33443e7c 22#include "crapto1/crapto1.h"
20f9a2a1 23#include "mifareutil.h"
de77d4ac 24#include "mifaresniff.h"
3000dc4e 25#include "BigBuf.h"
c872d8c1 26#include "protocols.h"
1f065e1d 27#include "parity.h"
fc52fbd4 28#include "fpgaloader.h"
1f065e1d 29
de77d4ac 30typedef struct {
31 enum {
32 DEMOD_UNSYNCD,
33 // DEMOD_HALF_SYNCD,
34 // DEMOD_MOD_FIRST_HALF,
35 // DEMOD_NOMOD_FIRST_HALF,
36 DEMOD_MANCHESTER_DATA
37 } state;
38 uint16_t twoBits;
39 uint16_t highCnt;
40 uint16_t bitCount;
41 uint16_t collisionPos;
42 uint16_t syncBit;
43 uint8_t parityBits;
44 uint8_t parityLen;
45 uint16_t shiftReg;
46 uint16_t samples;
47 uint16_t len;
48 uint32_t startTime, endTime;
49 uint8_t *output;
50 uint8_t *parity;
51} tDemod;
52
53typedef enum {
54 MOD_NOMOD = 0,
55 MOD_SECOND_HALF,
56 MOD_FIRST_HALF,
57 MOD_BOTH_HALVES
58 } Modulation_t;
59
60typedef struct {
61 enum {
62 STATE_UNSYNCD,
63 STATE_START_OF_COMMUNICATION,
64 STATE_MILLER_X,
65 STATE_MILLER_Y,
66 STATE_MILLER_Z,
67 // DROP_NONE,
68 // DROP_FIRST_HALF,
69 } state;
70 uint16_t shiftReg;
a8561e35 71 int16_t bitCount;
de77d4ac 72 uint16_t len;
73 uint16_t byteCntMax;
74 uint16_t posCnt;
75 uint16_t syncBit;
76 uint8_t parityBits;
77 uint8_t parityLen;
78 uint32_t fourBits;
79 uint32_t startTime, endTime;
a8561e35 80 uint8_t *output;
de77d4ac 81 uint8_t *parity;
82} tUart;
c872d8c1 83
534983d7 84static uint32_t iso14a_timeout;
db68bcdb 85#define MAX_ISO14A_TIMEOUT 524288
86
1e262141 87int rsamples = 0;
1e262141 88uint8_t trigger = 0;
b0127e65 89// the block number for the ISO14443-4 PCB
90static uint8_t iso14_pcb_blocknum = 0;
15c4dc5a 91
7bc95e2e 92//
93// ISO14443 timing:
94//
95// minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
96#define REQUEST_GUARD_TIME (7000/16 + 1)
a8561e35 97// minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
98#define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
de77d4ac 99// bool LastCommandWasRequest = false;
7bc95e2e 100
101//
102// Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
103//
d714d3ef 104// When the PM acts as reader and is receiving tag data, it takes
105// 3 ticks delay in the AD converter
106// 16 ticks until the modulation detector completes and sets curbit
107// 8 ticks until bit_to_arm is assigned from curbit
108// 8*16 ticks for the transfer from FPGA to ARM
7bc95e2e 109// 4*16 ticks until we measure the time
a8561e35 110// - 8*16 ticks because we measure the time of the previous transfer
111#define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
7bc95e2e 112
113// When the PM acts as a reader and is sending, it takes
114// 4*16 ticks until we can write data to the sending hold register
115// 8*16 ticks until the SHR is transferred to the Sending Shift Register
116// 8 ticks until the first transfer starts
117// 8 ticks later the FPGA samples the data
118// 1 tick to assign mod_sig_coil
119#define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
120
121// When the PM acts as tag and is receiving it takes
d714d3ef 122// 2 ticks delay in the RF part (for the first falling edge),
7bc95e2e 123// 3 ticks for the A/D conversion,
124// 8 ticks on average until the start of the SSC transfer,
125// 8 ticks until the SSC samples the first data
126// 7*16 ticks to complete the transfer from FPGA to ARM
127// 8 ticks until the next ssp_clk rising edge
a8561e35 128// 4*16 ticks until we measure the time
129// - 8*16 ticks because we measure the time of the previous transfer
d714d3ef 130#define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
a8561e35 131
7bc95e2e 132// The FPGA will report its internal sending delay in
133uint16_t FpgaSendQueueDelay;
134// the 5 first bits are the number of bits buffered in mod_sig_buf
135// the last three bits are the remaining ticks/2 after the mod_sig_buf shift
136#define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
137
138// When the PM acts as tag and is sending, it takes
6e49717b 139// 4*16 + 8 ticks until we can write data to the sending hold register
7bc95e2e 140// 8*16 ticks until the SHR is transferred to the Sending Shift Register
6e49717b 141// 8 ticks later the FPGA samples the first data
142// + 16 ticks until assigned to mod_sig
7bc95e2e 143// + 1 tick to assign mod_sig_coil
6e49717b 144// + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
145#define DELAY_ARM2AIR_AS_TAG (4*16 + 8 + 8*16 + 8 + 16 + 1 + DELAY_FPGA_QUEUE)
7bc95e2e 146
147// When the PM acts as sniffer and is receiving tag data, it takes
148// 3 ticks A/D conversion
d714d3ef 149// 14 ticks to complete the modulation detection
150// 8 ticks (on average) until the result is stored in to_arm
7bc95e2e 151// + the delays in transferring data - which is the same for
152// sniffing reader and tag data and therefore not relevant
a8561e35 153#define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
154
d714d3ef 155// When the PM acts as sniffer and is receiving reader data, it takes
a8561e35 156// 2 ticks delay in analogue RF receiver (for the falling edge of the
d714d3ef 157// start bit, which marks the start of the communication)
7bc95e2e 158// 3 ticks A/D conversion
d714d3ef 159// 8 ticks on average until the data is stored in to_arm.
7bc95e2e 160// + the delays in transferring data - which is the same for
161// sniffing reader and tag data and therefore not relevant
a8561e35 162#define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
7bc95e2e 163
164//variables used for timing purposes:
165//these are in ssp_clk cycles:
6a1f2d82 166static uint32_t NextTransferTime;
167static uint32_t LastTimeProxToAirStart;
168static uint32_t LastProxToAirDuration;
7bc95e2e 169
170
171
8f51ddb0 172// CARD TO READER - manchester
72934aa3 173// Sequence D: 11110000 modulation with subcarrier during first half
174// Sequence E: 00001111 modulation with subcarrier during second half
175// Sequence F: 00000000 no modulation with subcarrier
8f51ddb0 176// READER TO CARD - miller
72934aa3 177// Sequence X: 00001100 drop after half a period
178// Sequence Y: 00000000 no drop
179// Sequence Z: 11000000 drop at start
a8561e35 180#define SEC_D 0xf0
181#define SEC_E 0x0f
182#define SEC_F 0x00
183#define SEC_X 0x0c
184#define SEC_Y 0x00
185#define SEC_Z 0xc0
15c4dc5a 186
902cb3c0 187void iso14a_set_trigger(bool enable) {
534983d7 188 trigger = enable;
189}
190
d19929cb 191
bb04ef21 192void iso14a_set_timeout(uint32_t timeout) {
fa85b085 193 // adjust timeout by FPGA delays and 2 additional ssp_frames to detect SOF
194 iso14a_timeout = timeout + (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/(16*8) + 2;
47b78133 195 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", timeout, timeout / 106);
b0127e65 196}
8556b852 197
19a700a8 198
47b78133 199uint32_t iso14a_get_timeout(void) {
fa85b085 200 return iso14a_timeout - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/(16*8) - 2;
19a700a8 201}
202
15c4dc5a 203//-----------------------------------------------------------------------------
204// Generate the parity value for a byte sequence
e30c654b 205//
15c4dc5a 206//-----------------------------------------------------------------------------
6a1f2d82 207void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par)
15c4dc5a 208{
6a1f2d82 209 uint16_t paritybit_cnt = 0;
210 uint16_t paritybyte_cnt = 0;
211 uint8_t parityBits = 0;
212
213 for (uint16_t i = 0; i < iLen; i++) {
214 // Generate the parity bits
1f065e1d 215 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
6a1f2d82 216 if (paritybit_cnt == 7) {
a8561e35 217 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
218 parityBits = 0; // and advance to next Parity Byte
6a1f2d82 219 paritybyte_cnt++;
220 paritybit_cnt = 0;
221 } else {
222 paritybit_cnt++;
223 }
5f6d6c90 224 }
6a1f2d82 225
226 // save remaining parity bits
227 par[paritybyte_cnt] = parityBits;
a8561e35 228
15c4dc5a 229}
230
534983d7 231void AppendCrc14443a(uint8_t* data, int len)
15c4dc5a 232{
5f6d6c90 233 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
15c4dc5a 234}
235
6e49717b 236static void AppendCrc14443b(uint8_t* data, int len)
48ece4a7 237{
238 ComputeCrc14443(CRC_14443_B,data,len,data+len,data+len+1);
239}
240
241
7bc95e2e 242//=============================================================================
243// ISO 14443 Type A - Miller decoder
244//=============================================================================
245// Basics:
246// This decoder is used when the PM3 acts as a tag.
a8561e35 247// The reader will generate "pauses" by temporarily switching of the field.
248// At the PM3 antenna we will therefore measure a modulated antenna voltage.
7bc95e2e 249// The FPGA does a comparison with a threshold and would deliver e.g.:
250// ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
251// The Miller decoder needs to identify the following sequences:
a8561e35 252// 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
253// 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
254// 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
7bc95e2e 255// Note 1: the bitstream may start at any time. We therefore need to sync.
256// Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
15c4dc5a 257//-----------------------------------------------------------------------------
b62a5a84 258static tUart Uart;
15c4dc5a 259
d7aa3739 260// Lookup-Table to decide if 4 raw bits are a modulation.
05ddb52c 261// We accept the following:
262// 0001 - a 3 tick wide pause
263// 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
264// 0111 - a 2 tick wide pause shifted left
265// 1001 - a 2 tick wide pause shifted right
d7aa3739 266const bool Mod_Miller_LUT[] = {
de77d4ac 267 false, true, false, true, false, false, false, true,
268 false, true, false, false, false, false, false, false
d7aa3739 269};
05ddb52c 270#define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
271#define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
d7aa3739 272
6e49717b 273static void UartReset()
15c4dc5a 274{
7bc95e2e 275 Uart.state = STATE_UNSYNCD;
276 Uart.bitCount = 0;
a8561e35 277 Uart.len = 0; // number of decoded data bytes
278 Uart.parityLen = 0; // number of decoded parity bytes
279 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
280 Uart.parityBits = 0; // holds 8 parity bits
7bc95e2e 281}
15c4dc5a 282
6e49717b 283static void UartInit(uint8_t *data, uint8_t *parity)
6a1f2d82 284{
285 Uart.output = data;
286 Uart.parity = parity;
a8561e35 287 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
288 Uart.startTime = 0;
289 Uart.endTime = 0;
6a1f2d82 290 UartReset();
291}
d714d3ef 292
7bc95e2e 293// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
294static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time)
295{
15c4dc5a 296
ef00343c 297 Uart.fourBits = (Uart.fourBits << 8) | bit;
a8561e35 298
299 if (Uart.state == STATE_UNSYNCD) { // not yet synced
300
301 Uart.syncBit = 9999; // not set
05ddb52c 302 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
303 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
a8561e35 304 // we therefore look for a ...xx11111111111100x11111xxxxxx... pattern
05ddb52c 305 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
a8561e35 306 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00000111 11111111 11101111 10000000
307 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00000111 11111111 10001111 10000000
308 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
05ddb52c 309 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
310 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
311 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
312 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
313 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
314 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
315 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
316
a8561e35 317 if (Uart.syncBit != 9999) { // found a sync bit
ef00343c 318 Uart.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
319 Uart.startTime -= Uart.syncBit;
320 Uart.endTime = Uart.startTime;
321 Uart.state = STATE_START_OF_COMMUNICATION;
1523527f 322 LED_B_ON();
7bc95e2e 323 }
15c4dc5a 324
7bc95e2e 325 } else {
15c4dc5a 326
a8561e35 327 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
328 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
1523527f 329 LED_B_OFF();
d7aa3739 330 UartReset();
a8561e35 331 } else { // Modulation in first half = Sequence Z = logic "0"
332 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
1523527f 333 LED_B_OFF();
7bc95e2e 334 UartReset();
7bc95e2e 335 } else {
336 Uart.bitCount++;
a8561e35 337 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
7bc95e2e 338 Uart.state = STATE_MILLER_Z;
339 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
a8561e35 340 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
7bc95e2e 341 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
a8561e35 342 Uart.parityBits <<= 1; // make room for the parity bit
343 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
7bc95e2e 344 Uart.bitCount = 0;
345 Uart.shiftReg = 0;
a8561e35 346 if((Uart.len&0x0007) == 0) { // every 8 data bytes
347 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
6a1f2d82 348 Uart.parityBits = 0;
349 }
15c4dc5a 350 }
7bc95e2e 351 }
d7aa3739 352 }
353 } else {
a8561e35 354 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
7bc95e2e 355 Uart.bitCount++;
a8561e35 356 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
7bc95e2e 357 Uart.state = STATE_MILLER_X;
358 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
a8561e35 359 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
7bc95e2e 360 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
a8561e35 361 Uart.parityBits <<= 1; // make room for the new parity bit
362 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
7bc95e2e 363 Uart.bitCount = 0;
364 Uart.shiftReg = 0;
a8561e35 365 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
366 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
6a1f2d82 367 Uart.parityBits = 0;
368 }
7bc95e2e 369 }
a8561e35 370 } else { // no modulation in both halves - Sequence Y
371 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
1523527f 372 LED_B_OFF();
15c4dc5a 373 Uart.state = STATE_UNSYNCD;
a8561e35 374 Uart.bitCount--; // last "0" was part of EOC sequence
375 Uart.shiftReg <<= 1; // drop it
376 if(Uart.bitCount > 0) { // if we decoded some bits
377 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
378 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
379 Uart.parityBits <<= 1; // add a (void) parity bit
380 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
381 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
de77d4ac 382 return true;
a8561e35 383 } else if (Uart.len & 0x0007) { // there are some parity bits to store
384 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
385 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
52bfb955 386 }
387 if (Uart.len) {
a8561e35 388 return true; // we are finished with decoding the raw data sequence
52bfb955 389 } else {
a8561e35 390 UartReset(); // Nothing received - start over
7bc95e2e 391 }
15c4dc5a 392 }
a8561e35 393 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
1523527f 394 LED_B_OFF();
7bc95e2e 395 UartReset();
a8561e35 396 } else { // a logic "0"
7bc95e2e 397 Uart.bitCount++;
a8561e35 398 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
7bc95e2e 399 Uart.state = STATE_MILLER_Y;
a8561e35 400 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
7bc95e2e 401 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
a8561e35 402 Uart.parityBits <<= 1; // make room for the parity bit
403 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
7bc95e2e 404 Uart.bitCount = 0;
405 Uart.shiftReg = 0;
a8561e35 406 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
407 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
6a1f2d82 408 Uart.parityBits = 0;
409 }
15c4dc5a 410 }
411 }
d7aa3739 412 }
15c4dc5a 413 }
15c4dc5a 414
a8561e35 415 }
416
417 return false; // not finished yet, need more data
15c4dc5a 418}
419
7bc95e2e 420
421
15c4dc5a 422//=============================================================================
e691fc45 423// ISO 14443 Type A - Manchester decoder
15c4dc5a 424//=============================================================================
e691fc45 425// Basics:
7bc95e2e 426// This decoder is used when the PM3 acts as a reader.
e691fc45 427// The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
428// at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
429// ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
430// The Manchester decoder needs to identify the following sequences:
a8561e35 431// 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
432// 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
433// 8 ticks unmodulated: Sequence F = end of communication
434// 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
7bc95e2e 435// Note 1: the bitstream may start at any time. We therefore need to sync.
e691fc45 436// Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
b62a5a84 437static tDemod Demod;
15c4dc5a 438
d7aa3739 439// Lookup-Table to decide if 4 raw bits are a modulation.
d714d3ef 440// We accept three or four "1" in any position
7bc95e2e 441const bool Mod_Manchester_LUT[] = {
de77d4ac 442 false, false, false, false, false, false, false, true,
443 false, false, false, true, false, true, true, true
7bc95e2e 444};
445
446#define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
447#define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
15c4dc5a 448
2f2d9fc5 449
6e49717b 450static void DemodReset()
e691fc45 451{
7bc95e2e 452 Demod.state = DEMOD_UNSYNCD;
a8561e35 453 Demod.len = 0; // number of decoded data bytes
6a1f2d82 454 Demod.parityLen = 0;
a8561e35 455 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
456 Demod.parityBits = 0; //
457 Demod.collisionPos = 0; // Position of collision bit
458 Demod.twoBits = 0xffff; // buffer for 2 Bits
7bc95e2e 459 Demod.highCnt = 0;
460 Demod.startTime = 0;
461 Demod.endTime = 0;
e691fc45 462}
15c4dc5a 463
6e49717b 464static void DemodInit(uint8_t *data, uint8_t *parity)
6a1f2d82 465{
466 Demod.output = data;
467 Demod.parity = parity;
468 DemodReset();
469}
470
7bc95e2e 471// use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
472static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time)
e691fc45 473{
7bc95e2e 474
475 Demod.twoBits = (Demod.twoBits << 8) | bit;
a8561e35 476
7bc95e2e 477 if (Demod.state == DEMOD_UNSYNCD) {
478
a8561e35 479 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
7bc95e2e 480 if (Demod.twoBits == 0x0000) {
481 Demod.highCnt++;
482 } else {
483 Demod.highCnt = 0;
484 }
485 } else {
a8561e35 486 Demod.syncBit = 0xFFFF; // not set
487 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
7bc95e2e 488 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
489 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
490 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
491 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
492 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
493 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
494 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
d7aa3739 495 if (Demod.syncBit != 0xFFFF) {
7bc95e2e 496 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
497 Demod.startTime -= Demod.syncBit;
a8561e35 498 Demod.bitCount = offset; // number of decoded data bits
e691fc45 499 Demod.state = DEMOD_MANCHESTER_DATA;
1523527f 500 LED_C_ON();
2f2d9fc5 501 }
7bc95e2e 502 }
15c4dc5a 503
7bc95e2e 504 } else {
15c4dc5a 505
a8561e35 506 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
507 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
e691fc45 508 if (!Demod.collisionPos) {
509 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
510 }
a8561e35 511 } // modulation in first half only - Sequence D = 1
7bc95e2e 512 Demod.bitCount++;
a8561e35 513 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
514 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
e691fc45 515 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
a8561e35 516 Demod.parityBits <<= 1; // make room for the parity bit
517 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
e691fc45 518 Demod.bitCount = 0;
519 Demod.shiftReg = 0;
a8561e35 520 if((Demod.len&0x0007) == 0) { // every 8 data bytes
521 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
6a1f2d82 522 Demod.parityBits = 0;
523 }
15c4dc5a 524 }
7bc95e2e 525 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
a8561e35 526 } else { // no modulation in first half
527 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
e691fc45 528 Demod.bitCount++;
a8561e35 529 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
530 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
e691fc45 531 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
a8561e35 532 Demod.parityBits <<= 1; // make room for the new parity bit
e691fc45 533 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
534 Demod.bitCount = 0;
535 Demod.shiftReg = 0;
a8561e35 536 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
537 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
6a1f2d82 538 Demod.parityBits = 0;
539 }
15c4dc5a 540 }
7bc95e2e 541 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
a8561e35 542 } else { // no modulation in both halves - End of communication
1523527f 543 LED_C_OFF();
a8561e35 544 if(Demod.bitCount > 0) { // there are some remaining data bits
545 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
546 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
547 Demod.parityBits <<= 1; // add a (void) parity bit
548 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
549 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
de77d4ac 550 return true;
a8561e35 551 } else if (Demod.len & 0x0007) { // there are some parity bits to store
552 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
553 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
52bfb955 554 }
555 if (Demod.len) {
a8561e35 556 return true; // we are finished with decoding the raw data sequence
557 } else { // nothing received. Start over
d7aa3739 558 DemodReset();
e691fc45 559 }
15c4dc5a 560 }
7bc95e2e 561 }
15c4dc5a 562
a8561e35 563 }
564
565 return false; // not finished yet, need more data
15c4dc5a 566}
567
568//=============================================================================
569// Finally, a `sniffer' for ISO 14443 Type A
570// Both sides of communication!
571//=============================================================================
572
573//-----------------------------------------------------------------------------
574// Record the sequence of commands sent by the reader to the tag, with
575// triggering so that we start recording at the point that the tag is moved
576// near the reader.
577//-----------------------------------------------------------------------------
5cd9ec01
M
578void RAMFUNC SnoopIso14443a(uint8_t param) {
579 // param:
580 // bit 0 - trigger from first card answer
581 // bit 1 - trigger from first reader 7-bit request
a8561e35 582
5cd9ec01 583 LEDsoff();
1523527f 584 LED_A_ON();
5cd9ec01 585
09ffd16e 586 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
587
f71f4deb 588 // Allocate memory from BigBuf for some buffers
589 // free all previous allocations first
590 BigBuf_free();
591
5cd9ec01 592 // The command (reader -> tag) that we're receiving.
f71f4deb 593 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
594 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
a8561e35 595
5cd9ec01 596 // The response (tag -> reader) that we're receiving.
f71f4deb 597 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
598 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
a8561e35 599
5cd9ec01 600 // The DMA buffer, used to stream samples from the FPGA
f71f4deb 601 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
602
603 // init trace buffer
3000dc4e 604 clear_trace();
de77d4ac 605 set_tracing(true);
f71f4deb 606
7bc95e2e 607 uint8_t *data = dmaBuf;
608 uint8_t previous_data = 0;
5cd9ec01
M
609 int maxDataLen = 0;
610 int dataLen = 0;
de77d4ac 611 bool TagIsActive = false;
612 bool ReaderIsActive = false;
a8561e35 613
5cd9ec01 614 // Set up the demodulator for tag -> reader responses.
6a1f2d82 615 DemodInit(receivedResponse, receivedResponsePar);
a8561e35 616
5cd9ec01 617 // Set up the demodulator for the reader -> tag commands
6a1f2d82 618 UartInit(receivedCmd, receivedCmdPar);
a8561e35 619
7bc95e2e 620 // Setup and start DMA.
5cd9ec01 621 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
a8561e35 622
09ffd16e 623 // We won't start recording the frames that we acquire until we trigger;
624 // a good trigger condition to get started is probably when we see a
625 // response from the tag.
de77d4ac 626 // triggered == false -- to wait first for card
a8561e35 627 bool triggered = !(param & 0x03);
628
5cd9ec01 629 // And now we loop, receiving samples.
a8561e35 630 for (uint32_t rsamples = 0; true; ) {
7bc95e2e 631
a8561e35 632 if (BUTTON_PRESS()) {
5cd9ec01 633 DbpString("cancelled by button");
7bc95e2e 634 break;
5cd9ec01 635 }
15c4dc5a 636
5cd9ec01 637 WDT_HIT();
15c4dc5a 638
5cd9ec01
M
639 int register readBufDataP = data - dmaBuf;
640 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
641 if (readBufDataP <= dmaBufDataP){
642 dataLen = dmaBufDataP - readBufDataP;
643 } else {
7bc95e2e 644 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
5cd9ec01
M
645 }
646 // test for length of buffer
647 if(dataLen > maxDataLen) {
648 maxDataLen = dataLen;
f71f4deb 649 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
7bc95e2e 650 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
651 break;
5cd9ec01
M
652 }
653 }
654 if(dataLen < 1) continue;
655
656 // primary buffer was stopped( <-- we lost data!
657 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
658 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
659 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
7bc95e2e 660 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
661 }
662 // secondary buffer sets as primary, secondary buffer was stopped
663 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
664 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
665 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
666 }
667
a8561e35 668 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
3be2a5ae 669
a8561e35 670 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
7bc95e2e 671 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
672 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
7bc95e2e 673 // check - if there is a short 7bit request from reader
1523527f 674 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) {
675 triggered = true;
676 }
7bc95e2e 677 if(triggered) {
a8561e35 678 if (!LogTrace(receivedCmd,
679 Uart.len,
6a1f2d82 680 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
681 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
a8561e35 682 Uart.parity,
de77d4ac 683 true)) break;
7bc95e2e 684 }
685 /* And ready to receive another command. */
48ece4a7 686 UartReset();
7bc95e2e 687 /* And also reset the demod code, which might have been */
688 /* false-triggered by the commands from the reader. */
689 DemodReset();
7bc95e2e 690 }
691 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
5cd9ec01 692 }
3be2a5ae 693
a8561e35 694 if (!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
7bc95e2e 695 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
1523527f 696 if (ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
a8561e35 697 if (!LogTrace(receivedResponse,
698 Demod.len,
699 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
6a1f2d82 700 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
701 Demod.parity,
de77d4ac 702 false)) break;
de77d4ac 703 if ((!triggered) && (param & 0x01)) triggered = true;
7bc95e2e 704 // And ready to receive another response.
705 DemodReset();
48ece4a7 706 // And reset the Miller decoder including itS (now outdated) input buffer
707 UartInit(receivedCmd, receivedCmdPar);
a8561e35 708 }
7bc95e2e 709 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
710 }
5cd9ec01
M
711 }
712
7bc95e2e 713 previous_data = *data;
714 rsamples++;
5cd9ec01 715 data++;
d714d3ef 716 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01
M
717 data = dmaBuf;
718 }
719 } // main cycle
720
7bc95e2e 721 FpgaDisableSscDma();
1523527f 722 LEDsoff();
723
724 DbpString("COMMAND FINISHED");
7bc95e2e 725 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
3000dc4e 726 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
15c4dc5a 727}
728
15c4dc5a 729//-----------------------------------------------------------------------------
730// Prepare tag messages
731//-----------------------------------------------------------------------------
6a1f2d82 732static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity)
15c4dc5a 733{
8f51ddb0 734 ToSendReset();
15c4dc5a 735
736 // Correction bit, might be removed when not needed
737 ToSendStuffBit(0);
738 ToSendStuffBit(0);
739 ToSendStuffBit(0);
740 ToSendStuffBit(0);
741 ToSendStuffBit(1); // 1
742 ToSendStuffBit(0);
743 ToSendStuffBit(0);
744 ToSendStuffBit(0);
a8561e35 745
15c4dc5a 746 // Send startbit
72934aa3 747 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 748 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 749
a8561e35 750 for (uint16_t i = 0; i < len; i++) {
8f51ddb0 751 uint8_t b = cmd[i];
15c4dc5a 752
753 // Data bits
a8561e35 754 for (uint16_t j = 0; j < 8; j++) {
15c4dc5a 755 if(b & 1) {
72934aa3 756 ToSend[++ToSendMax] = SEC_D;
15c4dc5a 757 } else {
72934aa3 758 ToSend[++ToSendMax] = SEC_E;
8f51ddb0
M
759 }
760 b >>= 1;
761 }
15c4dc5a 762
0014cb46 763 // Get the parity bit
6a1f2d82 764 if (parity[i>>3] & (0x80>>(i&0x0007))) {
8f51ddb0 765 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 766 LastProxToAirDuration = 8 * ToSendMax - 4;
15c4dc5a 767 } else {
72934aa3 768 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 769 LastProxToAirDuration = 8 * ToSendMax;
15c4dc5a 770 }
8f51ddb0 771 }
15c4dc5a 772
8f51ddb0
M
773 // Send stopbit
774 ToSend[++ToSendMax] = SEC_F;
15c4dc5a 775
8f51ddb0
M
776 // Convert from last byte pos to length
777 ToSendMax++;
8f51ddb0
M
778}
779
15c4dc5a 780
8f51ddb0
M
781static void Code4bitAnswerAsTag(uint8_t cmd)
782{
783 int i;
784
5f6d6c90 785 ToSendReset();
8f51ddb0
M
786
787 // Correction bit, might be removed when not needed
788 ToSendStuffBit(0);
789 ToSendStuffBit(0);
790 ToSendStuffBit(0);
791 ToSendStuffBit(0);
792 ToSendStuffBit(1); // 1
793 ToSendStuffBit(0);
794 ToSendStuffBit(0);
795 ToSendStuffBit(0);
796
797 // Send startbit
798 ToSend[++ToSendMax] = SEC_D;
799
800 uint8_t b = cmd;
a8561e35 801 for (i = 0; i < 4; i++) {
8f51ddb0
M
802 if(b & 1) {
803 ToSend[++ToSendMax] = SEC_D;
7bc95e2e 804 LastProxToAirDuration = 8 * ToSendMax - 4;
8f51ddb0
M
805 } else {
806 ToSend[++ToSendMax] = SEC_E;
7bc95e2e 807 LastProxToAirDuration = 8 * ToSendMax;
8f51ddb0
M
808 }
809 b >>= 1;
810 }
811
812 // Send stopbit
813 ToSend[++ToSendMax] = SEC_F;
814
5f6d6c90 815 // Convert from last byte pos to length
816 ToSendMax++;
15c4dc5a 817}
818
6e49717b 819
820static uint8_t *LastReaderTraceTime = NULL;
821
822static void EmLogTraceReader(void) {
823 // remember last reader trace start to fix timing info later
824 LastReaderTraceTime = BigBuf_get_addr() + BigBuf_get_traceLen();
825 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, true);
826}
827
828
829static void FixLastReaderTraceTime(uint32_t tag_StartTime) {
830 uint32_t reader_EndTime = Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG;
831 uint32_t reader_StartTime = Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG;
832 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
833 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
834 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
835 reader_StartTime = tag_StartTime - exact_fdt - reader_modlen;
836 LastReaderTraceTime[0] = (reader_StartTime >> 0) & 0xff;
837 LastReaderTraceTime[1] = (reader_StartTime >> 8) & 0xff;
838 LastReaderTraceTime[2] = (reader_StartTime >> 16) & 0xff;
839 LastReaderTraceTime[3] = (reader_StartTime >> 24) & 0xff;
840}
841
a8561e35 842
6e49717b 843static void EmLogTraceTag(uint8_t *tag_data, uint16_t tag_len, uint8_t *tag_Parity, uint32_t ProxToAirDuration) {
844 uint32_t tag_StartTime = LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG;
845 uint32_t tag_EndTime = (LastTimeProxToAirStart + ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG;
846 LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, false);
847 FixLastReaderTraceTime(tag_StartTime);
848}
849
850
15c4dc5a 851//-----------------------------------------------------------------------------
852// Wait for commands from reader
853// Stop when button is pressed
de77d4ac 854// Or return true when command is captured
15c4dc5a 855//-----------------------------------------------------------------------------
6a1f2d82 856static int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len)
15c4dc5a 857{
a8561e35 858 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
859 // only, since we are receiving, not transmitting).
860 // Signal field is off with the appropriate LED
861 LED_D_OFF();
862 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
15c4dc5a 863
a8561e35 864 // Now run a `software UART' on the stream of incoming samples.
6a1f2d82 865 UartInit(received, parity);
7bc95e2e 866
867 // clear RXRDY:
a8561e35 868 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
869
870 for (;;) {
871 WDT_HIT();
15c4dc5a 872
a8561e35 873 if(BUTTON_PRESS()) return false;
15c4dc5a 874
a8561e35 875 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
876 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 877 if(MillerDecoding(b, 0)) {
878 *len = Uart.len;
6e49717b 879 EmLogTraceReader();
de77d4ac 880 return true;
15c4dc5a 881 }
a8561e35 882 }
883 }
15c4dc5a 884}
28afbd2b 885
6e49717b 886
28afbd2b 887int EmSend4bit(uint8_t resp);
b35e04a7 888static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, uint8_t *par);
a8561e35 889int EmSendCmd(uint8_t *resp, uint16_t respLen);
b35e04a7 890int EmSendPrecompiledCmd(tag_response_info_t *response_info);
15c4dc5a 891
ce02f6f9 892
6e49717b 893static bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
7bc95e2e 894 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
ce02f6f9 895 // This will need the following byte array for a modulation sequence
896 // 144 data bits (18 * 8)
897 // 18 parity bits
898 // 2 Start and stop
899 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
900 // 1 just for the case
901 // ----------- +
902 // 166 bytes, since every bit that needs to be send costs us a byte
903 //
a8561e35 904
905
ce02f6f9 906 // Prepare the tag modulation bits from the message
6e49717b 907 GetParity(response_info->response, response_info->response_n, &(response_info->par));
908 CodeIso14443aAsTagPar(response_info->response,response_info->response_n, &(response_info->par));
a8561e35 909
ce02f6f9 910 // Make sure we do not exceed the free buffer space
911 if (ToSendMax > max_buffer_size) {
a8561e35 912 Dbprintf("Out of memory, when modulating bits for tag answer:");
913 Dbhexdump(response_info->response_n, response_info->response, false);
914 return false;
ce02f6f9 915 }
a8561e35 916
ce02f6f9 917 // Copy the byte array, used for this modulation to the buffer position
6e49717b 918 memcpy(response_info->modulation, ToSend, ToSendMax);
a8561e35 919
7bc95e2e 920 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
ce02f6f9 921 response_info->modulation_n = ToSendMax;
7bc95e2e 922 response_info->ProxToAirDuration = LastProxToAirDuration;
a8561e35 923
ce02f6f9 924 return true;
925}
926
f71f4deb 927
928// "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
a8561e35 929// Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
6e49717b 930// 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits for the modulation
f71f4deb 931// -> need 273 bytes buffer
932#define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 273
933
6e49717b 934bool prepare_allocated_tag_modulation(tag_response_info_t* response_info, uint8_t **buffer, size_t *max_buffer_size) {
935
ce02f6f9 936 // Retrieve and store the current buffer index
6e49717b 937 response_info->modulation = *buffer;
a8561e35 938
ce02f6f9 939 // Forward the prepare tag modulation function to the inner function
6e49717b 940 if (prepare_tag_modulation(response_info, *max_buffer_size)) {
a8561e35 941 // Update the free buffer offset and the remaining buffer size
942 *buffer += ToSendMax;
6e49717b 943 *max_buffer_size -= ToSendMax;
a8561e35 944 return true;
ce02f6f9 945 } else {
a8561e35 946 return false;
ce02f6f9 947 }
948}
949
15c4dc5a 950//-----------------------------------------------------------------------------
951// Main loop of simulated tag: receive commands from reader, decide what
952// response to send, and send it.
953//-----------------------------------------------------------------------------
28afbd2b 954void SimulateIso14443aTag(int tagType, int uid_1st, int uid_2nd, byte_t* data)
15c4dc5a 955{
81cd0474 956 uint8_t sak;
957
958 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
959 uint8_t response1[2];
a8561e35 960
81cd0474 961 switch (tagType) {
962 case 1: { // MIFARE Classic
963 // Says: I am Mifare 1k - original line
964 response1[0] = 0x04;
965 response1[1] = 0x00;
966 sak = 0x08;
967 } break;
968 case 2: { // MIFARE Ultralight
969 // Says: I am a stupid memory tag, no crypto
970 response1[0] = 0x04;
971 response1[1] = 0x00;
972 sak = 0x00;
973 } break;
974 case 3: { // MIFARE DESFire
975 // Says: I am a DESFire tag, ph33r me
976 response1[0] = 0x04;
977 response1[1] = 0x03;
978 sak = 0x20;
979 } break;
980 case 4: { // ISO/IEC 14443-4
981 // Says: I am a javacard (JCOP)
982 response1[0] = 0x04;
983 response1[1] = 0x00;
984 sak = 0x28;
985 } break;
3fe4ff4f 986 case 5: { // MIFARE TNP3XXX
987 // Says: I am a toy
988 response1[0] = 0x01;
989 response1[1] = 0x0f;
990 sak = 0x01;
a8561e35 991 } break;
81cd0474 992 default: {
993 Dbprintf("Error: unkown tagtype (%d)",tagType);
994 return;
995 } break;
996 }
a8561e35 997
81cd0474 998 // The second response contains the (mandatory) first 24 bits of the UID
c8b6da22 999 uint8_t response2[5] = {0x00};
81cd0474 1000
1001 // Check if the uid uses the (optional) part
c8b6da22 1002 uint8_t response2a[5] = {0x00};
a8561e35 1003
81cd0474 1004 if (uid_2nd) {
1005 response2[0] = 0x88;
1006 num_to_bytes(uid_1st,3,response2+1);
1007 num_to_bytes(uid_2nd,4,response2a);
1008 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
1009
1010 // Configure the ATQA and SAK accordingly
1011 response1[0] |= 0x40;
1012 sak |= 0x04;
1013 } else {
1014 num_to_bytes(uid_1st,4,response2);
1015 // Configure the ATQA and SAK accordingly
1016 response1[0] &= 0xBF;
1017 sak &= 0xFB;
1018 }
1019
1020 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
1021 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
1022
1023 // Prepare the mandatory SAK (for 4 and 7 byte UID)
c8b6da22 1024 uint8_t response3[3] = {0x00};
81cd0474 1025 response3[0] = sak;
1026 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
1027
1028 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
c8b6da22 1029 uint8_t response3a[3] = {0x00};
81cd0474 1030 response3a[0] = sak & 0xFB;
1031 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
1032
254b70a4 1033 uint8_t response5[] = { 0x00, 0x00, 0x00, 0x00 }; // Very random tag nonce
a8561e35 1034 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
1035 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
6a1f2d82 1036 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
1037 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
1038 // TC(1) = 0x02: CID supported, NAD not supported
ce02f6f9 1039 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
1040
7bc95e2e 1041 #define TAG_RESPONSE_COUNT 7
1042 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
1043 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
1044 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
1045 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
1046 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
1047 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
1048 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
1049 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1050 };
1051
1052 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1053 // Such a response is less time critical, so we can prepare them on the fly
1054 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1055 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1056 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1057 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1058 tag_response_info_t dynamic_response_info = {
1059 .response = dynamic_response_buffer,
1060 .response_n = 0,
1061 .modulation = dynamic_modulation_buffer,
1062 .modulation_n = 0
1063 };
a8561e35 1064
09ffd16e 1065 // We need to listen to the high-frequency, peak-detected path.
1066 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1067
f71f4deb 1068 BigBuf_free_keep_EM();
1069
1070 // allocate buffers:
1071 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1072 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
6e49717b 1073 uint8_t *free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1074 size_t free_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
f71f4deb 1075 // clear trace
3000dc4e 1076 clear_trace();
de77d4ac 1077 set_tracing(true);
f71f4deb 1078
7bc95e2e 1079 // Prepare the responses of the anticollision phase
ce02f6f9 1080 // there will be not enough time to do this at the moment the reader sends it REQA
7bc95e2e 1081 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++) {
6e49717b 1082 prepare_allocated_tag_modulation(&responses[i], &free_buffer_pointer, &free_buffer_size);
7bc95e2e 1083 }
15c4dc5a 1084
7bc95e2e 1085 int len = 0;
15c4dc5a 1086
1087 // To control where we are in the protocol
1088 int order = 0;
1089 int lastorder;
1090
1091 // Just to allow some checks
1092 int happened = 0;
1093 int happened2 = 0;
81cd0474 1094 int cmdsRecvd = 0;
15c4dc5a 1095
254b70a4 1096 cmdsRecvd = 0;
7bc95e2e 1097 tag_response_info_t* p_response;
15c4dc5a 1098
254b70a4 1099 LED_A_ON();
a8561e35 1100 for (;;) {
7bc95e2e 1101 // Clean receive command buffer
6a1f2d82 1102 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
ce02f6f9 1103 DbpString("Button press");
254b70a4 1104 break;
1105 }
7bc95e2e 1106
1107 p_response = NULL;
a8561e35 1108
254b70a4 1109 // Okay, look at the command now.
1110 lastorder = order;
1111 if(receivedCmd[0] == 0x26) { // Received a REQUEST
ce02f6f9 1112 p_response = &responses[0]; order = 1;
254b70a4 1113 } else if(receivedCmd[0] == 0x52) { // Received a WAKEUP
ce02f6f9 1114 p_response = &responses[0]; order = 6;
a8561e35 1115 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x93) { // Received request for UID (cascade 1)
ce02f6f9 1116 p_response = &responses[1]; order = 2;
a8561e35 1117 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == 0x95) { // Received request for UID (cascade 2)
ce02f6f9 1118 p_response = &responses[2]; order = 20;
a8561e35 1119 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x93) { // Received a SELECT (cascade 1)
ce02f6f9 1120 p_response = &responses[3]; order = 3;
a8561e35 1121 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == 0x95) { // Received a SELECT (cascade 2)
ce02f6f9 1122 p_response = &responses[4]; order = 30;
a8561e35 1123 } else if(receivedCmd[0] == 0x30) { // Received a (plain) READ
1124 EmSendCmd(data+(4*receivedCmd[1]),16);
7bc95e2e 1125 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
5f6d6c90 1126 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
7bc95e2e 1127 p_response = NULL;
a8561e35 1128 } else if(receivedCmd[0] == 0x50) { // Received a HALT
7bc95e2e 1129 p_response = NULL;
a8561e35 1130 } else if(receivedCmd[0] == 0x60 || receivedCmd[0] == 0x61) { // Received an authentication request
ce02f6f9 1131 p_response = &responses[5]; order = 7;
a8561e35 1132 } else if(receivedCmd[0] == 0xE0) { // Received a RATS request
1133 if (tagType == 1 || tagType == 2) { // RATS not supported
7bc95e2e 1134 EmSend4bit(CARD_NACK_NA);
1135 p_response = NULL;
1136 } else {
1137 p_response = &responses[6]; order = 70;
1138 }
6a1f2d82 1139 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
7bc95e2e 1140 uint32_t nr = bytes_to_num(receivedCmd,4);
1141 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1142 Dbprintf("Auth attempt {nr}{ar}: %08x %08x",nr,ar);
1143 } else {
1144 // Check for ISO 14443A-4 compliant commands, look at left nibble
1145 switch (receivedCmd[0]) {
1146
1147 case 0x0B:
1148 case 0x0A: { // IBlock (command)
1149 dynamic_response_info.response[0] = receivedCmd[0];
1150 dynamic_response_info.response[1] = 0x00;
1151 dynamic_response_info.response[2] = 0x90;
1152 dynamic_response_info.response[3] = 0x00;
1153 dynamic_response_info.response_n = 4;
1154 } break;
1155
1156 case 0x1A:
1157 case 0x1B: { // Chaining command
1158 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1159 dynamic_response_info.response_n = 2;
1160 } break;
1161
1162 case 0xaa:
1163 case 0xbb: {
1164 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1165 dynamic_response_info.response_n = 2;
1166 } break;
a8561e35 1167
7bc95e2e 1168 case 0xBA: { //
1169 memcpy(dynamic_response_info.response,"\xAB\x00",2);
1170 dynamic_response_info.response_n = 2;
1171 } break;
1172
1173 case 0xCA:
1174 case 0xC2: { // Readers sends deselect command
1175 memcpy(dynamic_response_info.response,"\xCA\x00",2);
1176 dynamic_response_info.response_n = 2;
1177 } break;
1178
1179 default: {
1180 // Never seen this command before
7bc95e2e 1181 Dbprintf("Received unknown command (len=%d):",len);
1182 Dbhexdump(len,receivedCmd,false);
1183 // Do not respond
1184 dynamic_response_info.response_n = 0;
1185 } break;
1186 }
a8561e35 1187
7bc95e2e 1188 if (dynamic_response_info.response_n > 0) {
1189 // Copy the CID from the reader query
1190 dynamic_response_info.response[1] = receivedCmd[1];
ce02f6f9 1191
7bc95e2e 1192 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1193 AppendCrc14443a(dynamic_response_info.response,dynamic_response_info.response_n);
1194 dynamic_response_info.response_n += 2;
a8561e35 1195
7bc95e2e 1196 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1197 Dbprintf("Error preparing tag response");
7bc95e2e 1198 break;
1199 }
1200 p_response = &dynamic_response_info;
1201 }
81cd0474 1202 }
15c4dc5a 1203
1204 // Count number of wakeups received after a halt
1205 if(order == 6 && lastorder == 5) { happened++; }
1206
1207 // Count number of other messages after a halt
1208 if(order != 6 && lastorder == 5) { happened2++; }
1209
15c4dc5a 1210 if(cmdsRecvd > 999) {
1211 DbpString("1000 commands later...");
254b70a4 1212 break;
15c4dc5a 1213 }
ce02f6f9 1214 cmdsRecvd++;
1215
1216 if (p_response != NULL) {
b35e04a7 1217 EmSendPrecompiledCmd(p_response);
7bc95e2e 1218 }
a8561e35 1219
d9de20fa 1220 if (!get_tracing()) {
7bc95e2e 1221 Dbprintf("Trace Full. Simulation stopped.");
1222 break;
1223 }
1224 }
15c4dc5a 1225
1226 Dbprintf("%x %x %x", happened, happened2, cmdsRecvd);
1227 LED_A_OFF();
f71f4deb 1228 BigBuf_free_keep_EM();
15c4dc5a 1229}
1230
9492e0b0 1231
1232// prepare a delayed transfer. This simply shifts ToSend[] by a number
1233// of bits specified in the delay parameter.
6e49717b 1234static void PrepareDelayedTransfer(uint16_t delay)
9492e0b0 1235{
1236 uint8_t bitmask = 0;
1237 uint8_t bits_to_shift = 0;
1238 uint8_t bits_shifted = 0;
a8561e35 1239
9492e0b0 1240 delay &= 0x07;
1241 if (delay) {
1242 for (uint16_t i = 0; i < delay; i++) {
1243 bitmask |= (0x01 << i);
1244 }
7bc95e2e 1245 ToSend[ToSendMax++] = 0x00;
9492e0b0 1246 for (uint16_t i = 0; i < ToSendMax; i++) {
1247 bits_to_shift = ToSend[i] & bitmask;
1248 ToSend[i] = ToSend[i] >> delay;
1249 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1250 bits_shifted = bits_to_shift;
1251 }
1252 }
1253}
1254
7bc95e2e 1255
1256//-------------------------------------------------------------------------------------
15c4dc5a 1257// Transmit the command (to the tag) that was placed in ToSend[].
9492e0b0 1258// Parameter timing:
7bc95e2e 1259// if NULL: transfer at next possible time, taking into account
a8561e35 1260// request guard time, startup frame guard time and frame delay time
1261// if == 0: transfer immediately and return time of transfer
9492e0b0 1262// if != 0: delay transfer until time specified
7bc95e2e 1263//-------------------------------------------------------------------------------------
6a1f2d82 1264static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing)
15c4dc5a 1265{
a8561e35 1266 LED_B_ON();
1523527f 1267 LED_D_ON();
9492e0b0 1268 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
e30c654b 1269
7bc95e2e 1270 uint32_t ThisTransferTime = 0;
e30c654b 1271
9492e0b0 1272 if (timing) {
a8561e35 1273 if(*timing == 0) { // Measure time
7bc95e2e 1274 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
9492e0b0 1275 } else {
a8561e35 1276 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
9492e0b0 1277 }
7bc95e2e 1278 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
a8561e35 1279 while (GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
7bc95e2e 1280 LastTimeProxToAirStart = *timing;
1281 } else {
1282 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
a8561e35 1283 while (GetCountSspClk() < ThisTransferTime);
7bc95e2e 1284 LastTimeProxToAirStart = ThisTransferTime;
9492e0b0 1285 }
a8561e35 1286
7bc95e2e 1287 // clear TXRDY
1288 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1289
7bc95e2e 1290 uint16_t c = 0;
a8561e35 1291 for (;;) {
9492e0b0 1292 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1293 AT91C_BASE_SSC->SSC_THR = cmd[c];
1294 c++;
1295 if(c >= len) {
1296 break;
1297 }
1298 }
1299 }
a8561e35 1300
7bc95e2e 1301 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
a8561e35 1302 LED_B_OFF();
15c4dc5a 1303}
1304
7bc95e2e 1305
15c4dc5a 1306//-----------------------------------------------------------------------------
195af472 1307// Prepare reader command (in bits, support short frames) to send to FPGA
15c4dc5a 1308//-----------------------------------------------------------------------------
6e49717b 1309static void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity)
15c4dc5a 1310{
7bc95e2e 1311 int i, j;
1312 int last;
1313 uint8_t b;
e30c654b 1314
7bc95e2e 1315 ToSendReset();
e30c654b 1316
7bc95e2e 1317 // Start of Communication (Seq. Z)
1318 ToSend[++ToSendMax] = SEC_Z;
1319 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1320 last = 0;
1321
1322 size_t bytecount = nbytes(bits);
1323 // Generate send structure for the data bits
1324 for (i = 0; i < bytecount; i++) {
1325 // Get the current byte to send
1326 b = cmd[i];
1327 size_t bitsleft = MIN((bits-(i*8)),8);
1328
1329 for (j = 0; j < bitsleft; j++) {
1330 if (b & 1) {
1331 // Sequence X
1332 ToSend[++ToSendMax] = SEC_X;
1333 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1334 last = 1;
1335 } else {
1336 if (last == 0) {
1337 // Sequence Z
1338 ToSend[++ToSendMax] = SEC_Z;
1339 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1340 } else {
1341 // Sequence Y
1342 ToSend[++ToSendMax] = SEC_Y;
1343 last = 0;
1344 }
1345 }
1346 b >>= 1;
1347 }
1348
6a1f2d82 1349 // Only transmit parity bit if we transmitted a complete byte
48ece4a7 1350 if (j == 8 && parity != NULL) {
7bc95e2e 1351 // Get the parity bit
6a1f2d82 1352 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
7bc95e2e 1353 // Sequence X
1354 ToSend[++ToSendMax] = SEC_X;
1355 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1356 last = 1;
1357 } else {
1358 if (last == 0) {
1359 // Sequence Z
1360 ToSend[++ToSendMax] = SEC_Z;
1361 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1362 } else {
1363 // Sequence Y
1364 ToSend[++ToSendMax] = SEC_Y;
1365 last = 0;
1366 }
1367 }
1368 }
1369 }
e30c654b 1370
7bc95e2e 1371 // End of Communication: Logic 0 followed by Sequence Y
1372 if (last == 0) {
1373 // Sequence Z
1374 ToSend[++ToSendMax] = SEC_Z;
1375 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1376 } else {
1377 // Sequence Y
1378 ToSend[++ToSendMax] = SEC_Y;
1379 last = 0;
1380 }
1381 ToSend[++ToSendMax] = SEC_Y;
e30c654b 1382
7bc95e2e 1383 // Convert to length of command:
1384 ToSendMax++;
15c4dc5a 1385}
1386
0c8d25eb 1387
9ca155ba
M
1388//-----------------------------------------------------------------------------
1389// Wait for commands from reader
1390// Stop when button is pressed (return 1) or field was gone (return 2)
1391// Or return 0 when command is captured
1392//-----------------------------------------------------------------------------
6e49717b 1393int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity)
9ca155ba 1394{
a8561e35 1395 uint32_t field_off_time = -1;
1396 uint32_t samples = 0;
1397 int ret = 0;
1398 uint8_t b = 0;;
1399 uint8_t dmaBuf[DMA_BUFFER_SIZE];
1400 uint8_t *upTo = dmaBuf;
1401
9ca155ba
M
1402 *len = 0;
1403
a8561e35 1404 // Run a 'software UART' on the stream of incoming samples.
1405 UartInit(received, parity);
9ca155ba 1406
9ca155ba
M
1407 // start ADC
1408 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
7bc95e2e 1409
b35e04a7 1410 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN
a8561e35 1411 while (GetCountSspClk() < LastTimeProxToAirStart + LastProxToAirDuration + (FpgaSendQueueDelay>>3) - 8 - 3) /* wait */ ;
b35e04a7 1412
1413 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1414 // only, since we are receiving, not transmitting).
b35e04a7 1415 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1416
a8561e35 1417 // clear receive register, measure time of next transfer
1418 uint32_t temp = AT91C_BASE_SSC->SSC_RHR; (void) temp;
1419 while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)) ;
1420 uint32_t start_time = GetCountSspClk() & 0xfffffff8;
1421
1422 // Setup and start DMA.
1423 FpgaSetupSscDma(dmaBuf, DMA_BUFFER_SIZE);
1424
9ca155ba 1425 for(;;) {
a8561e35 1426 uint16_t behindBy = ((uint8_t*)AT91C_BASE_PDC_SSC->PDC_RPR - upTo) & (DMA_BUFFER_SIZE-1);
9ca155ba 1427
a8561e35 1428 if (behindBy == 0) continue;
9ca155ba 1429
a8561e35 1430 b = *upTo++;
1431
1432 if(upTo >= dmaBuf + DMA_BUFFER_SIZE) { // we have read all of the DMA buffer content.
1433 upTo = dmaBuf; // start reading the circular buffer from the beginning
1434 if(behindBy > (9*DMA_BUFFER_SIZE/10)) {
1435 Dbprintf("About to blow circular buffer - aborted! behindBy=%d", behindBy);
1436 ret = 1;
1437 break;
9ca155ba
M
1438 }
1439 }
a8561e35 1440 if (AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_ENDRX)) { // DMA Counter Register had reached 0, already rotated.
1441 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf; // refresh the DMA Next Buffer and
1442 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE; // DMA Next Counter registers
1443 }
7bc95e2e 1444
a8561e35 1445 if (BUTTON_PRESS()) {
1446 ret = 1;
1447 break;
1448 }
1449
1450 // check reader's HF field
1451 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF_LOW)) {
1452 if ((MAX_ADC_HF_VOLTAGE_LOW * AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF_LOW]) >> 10 < MF_MINFIELDV) {
1453 if (GetTickCount() - field_off_time > 50) {
1454 ret = 2; // reader has switched off HF field for more than 50ms. Timeout
1455 break;
1456 }
1457 } else {
1458 field_off_time = GetTickCount(); // HF field is still there. Reset timer
9ca155ba 1459 }
a8561e35 1460 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START; // restart ADC
1461 }
1462
1463 if (MillerDecoding(b, start_time + samples*8)) {
1464 *len = Uart.len;
1465 EmLogTraceReader();
1466 ret = 0;
1467 break;
1468 }
7bc95e2e 1469
a8561e35 1470 samples++;
9ca155ba 1471 }
a8561e35 1472
1473 FpgaDisableSscDma();
1474 return ret;
9ca155ba
M
1475}
1476
9ca155ba 1477
b35e04a7 1478static int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen)
7bc95e2e 1479{
a8561e35 1480 LED_C_ON();
1481
7bc95e2e 1482 uint8_t b;
1483 uint16_t i = 0;
b35e04a7 1484 bool correctionNeeded;
1485
9ca155ba
M
1486 // Modulate Manchester
1487 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
7bc95e2e 1488
1489 // include correction bit if necessary
b35e04a7 1490 if (Uart.bitCount == 7)
1491 {
1492 // Short tags (7 bits) don't have parity, determine the correct value from MSB
1493 correctionNeeded = Uart.output[0] & 0x40;
1494 }
1495 else
1496 {
1497 // Look at the last parity bit
1498 correctionNeeded = Uart.parity[(Uart.len-1)/8] & (0x80 >> ((Uart.len-1) & 7));
7bc95e2e 1499 }
b35e04a7 1500
a8561e35 1501 if (correctionNeeded) {
9ca155ba
M
1502 // 1236, so correction bit needed
1503 i = 0;
7bc95e2e 1504 } else {
1505 i = 1;
9ca155ba 1506 }
7bc95e2e 1507
a8561e35 1508 // clear receiving shift register and holding register
7bc95e2e 1509 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
a8561e35 1510 while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
7bc95e2e 1511 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
a8561e35 1512
7bc95e2e 1513 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
a8561e35 1514 for (uint16_t j = 0; j < 5; j++) { // allow timeout - better late than never
1515 while (!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
7bc95e2e 1516 if (AT91C_BASE_SSC->SSC_RHR) break;
1517 }
1518
6e49717b 1519 LastTimeProxToAirStart = (GetCountSspClk() & 0xfffffff8) + (correctionNeeded?8:0);
7bc95e2e 1520
9ca155ba 1521 // send cycle
a8561e35 1522 for (; i < respLen; ) {
9ca155ba 1523 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
7bc95e2e 1524 AT91C_BASE_SSC->SSC_THR = resp[i++];
1525 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
9ca155ba 1526 }
a8561e35 1527
9ca155ba
M
1528 if(BUTTON_PRESS()) {
1529 break;
1530 }
1531 }
1532
a8561e35 1533 LED_C_OFF();
9ca155ba
M
1534 return 0;
1535}
1536
6e49717b 1537
a8561e35 1538int EmSend4bit(uint8_t resp){
7bc95e2e 1539 Code4bitAnswerAsTag(resp);
b35e04a7 1540 int res = EmSendCmd14443aRaw(ToSend, ToSendMax);
a8561e35 1541 // Log this tag answer and fix timing of previous reader command:
6e49717b 1542 EmLogTraceTag(&resp, 1, NULL, LastProxToAirDuration);
0a39986e 1543 return res;
9ca155ba
M
1544}
1545
6e49717b 1546
b35e04a7 1547static int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
7bc95e2e 1548 CodeIso14443aAsTagPar(resp, respLen, par);
b35e04a7 1549 int res = EmSendCmd14443aRaw(ToSend, ToSendMax);
a8561e35 1550 // Log this tag answer and fix timing of previous reader command:
6e49717b 1551 EmLogTraceTag(resp, respLen, par, LastProxToAirDuration);
8f51ddb0
M
1552 return res;
1553}
1554
6e49717b 1555
6a1f2d82 1556int EmSendCmd(uint8_t *resp, uint16_t respLen){
1557 uint8_t par[MAX_PARITY_SIZE];
1558 GetParity(resp, respLen, par);
b35e04a7 1559 return EmSendCmdExPar(resp, respLen, par);
8f51ddb0
M
1560}
1561
6e49717b 1562
6a1f2d82 1563int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
b35e04a7 1564 return EmSendCmdExPar(resp, respLen, par);
7bc95e2e 1565}
1566
6e49717b 1567
b35e04a7 1568int EmSendPrecompiledCmd(tag_response_info_t *response_info) {
1569 int ret = EmSendCmd14443aRaw(response_info->modulation, response_info->modulation_n);
a8561e35 1570 // Log this tag answer and fix timing of previous reader command:
6e49717b 1571 EmLogTraceTag(response_info->response, response_info->response_n, &(response_info->par), response_info->ProxToAirDuration);
1572 return ret;
9ca155ba
M
1573}
1574
6e49717b 1575
15c4dc5a 1576//-----------------------------------------------------------------------------
1577// Wait a certain time for tag response
de77d4ac 1578// If a response is captured return true
1579// If it takes too long return false
15c4dc5a 1580//-----------------------------------------------------------------------------
6a1f2d82 1581static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset)
15c4dc5a 1582{
52bfb955 1583 uint32_t c;
a8561e35 1584
15c4dc5a 1585 // Set FPGA mode to "reader listen mode", no modulation (listen
534983d7 1586 // only, since we are receiving, not transmitting).
1587 // Signal field is on with the appropriate LED
1588 LED_D_ON();
1589 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
a8561e35 1590
534983d7 1591 // Now get the answer from the card
6a1f2d82 1592 DemodInit(receivedResponse, receivedResponsePar);
15c4dc5a 1593
7bc95e2e 1594 // clear RXRDY:
a8561e35 1595 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
0c8d25eb 1596
15c4dc5a 1597 c = 0;
a8561e35 1598 for (;;) {
534983d7 1599 WDT_HIT();
15c4dc5a 1600
534983d7 1601 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
534983d7 1602 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
7bc95e2e 1603 if(ManchesterDecoding(b, offset, 0)) {
1604 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
de77d4ac 1605 return true;
19a700a8 1606 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
a8561e35 1607 return false;
15c4dc5a 1608 }
534983d7 1609 }
1610 }
15c4dc5a 1611}
1612
48ece4a7 1613
6a1f2d82 1614void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing)
15c4dc5a 1615{
6a1f2d82 1616 CodeIso14443aBitsAsReaderPar(frame, bits, par);
a8561e35 1617
7bc95e2e 1618 // Send command to tag
1619 TransmitFor14443a(ToSend, ToSendMax, timing);
1620 if(trigger)
1621 LED_A_ON();
a8561e35 1622
7bc95e2e 1623 // Log reader command in trace buffer
d9de20fa 1624 LogTrace(frame, nbytes(bits), LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_READER, (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_READER, par, true);
15c4dc5a 1625}
1626
48ece4a7 1627
6a1f2d82 1628void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing)
dfc3c505 1629{
6a1f2d82 1630 ReaderTransmitBitsPar(frame, len*8, par, timing);
dfc3c505 1631}
15c4dc5a 1632
48ece4a7 1633
6e49717b 1634static void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing)
e691fc45 1635{
1636 // Generate parity and redirect
6a1f2d82 1637 uint8_t par[MAX_PARITY_SIZE];
1638 GetParity(frame, len/8, par);
1639 ReaderTransmitBitsPar(frame, len, par, timing);
e691fc45 1640}
1641
48ece4a7 1642
6a1f2d82 1643void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing)
15c4dc5a 1644{
1645 // Generate parity and redirect
6a1f2d82 1646 uint8_t par[MAX_PARITY_SIZE];
1647 GetParity(frame, len, par);
1648 ReaderTransmitBitsPar(frame, len*8, par, timing);
15c4dc5a 1649}
1650
6e49717b 1651
1652static int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity)
e691fc45 1653{
de77d4ac 1654 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset)) return false;
d9de20fa 1655 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false);
e691fc45 1656 return Demod.len;
1657}
1658
6e49717b 1659
6a1f2d82 1660int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity)
15c4dc5a 1661{
de77d4ac 1662 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0)) return false;
d9de20fa 1663 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, false);
e691fc45 1664 return Demod.len;
f89c7050
M
1665}
1666
47b78133 1667
1668static void iso14a_set_ATS_times(uint8_t *ats) {
1669
1670 uint8_t tb1;
a8561e35 1671 uint8_t fwi, sfgi;
47b78133 1672 uint32_t fwt, sfgt;
a8561e35 1673
1674 if (ats[0] > 1) { // there is a format byte T0
1675 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
1676 if ((ats[1] & 0x10) == 0x10) { // there is an interface byte TA(1) preceding TB(1)
47b78133 1677 tb1 = ats[3];
1678 } else {
1679 tb1 = ats[2];
1680 }
a8561e35 1681 fwi = (tb1 & 0xf0) >> 4; // frame waiting time integer (FWI)
47b78133 1682 if (fwi != 15) {
a8561e35 1683 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
47b78133 1684 iso14a_set_timeout(fwt/(8*16));
1685 }
a8561e35 1686 sfgi = tb1 & 0x0f; // startup frame guard time integer (SFGI)
47b78133 1687 if (sfgi != 0 && sfgi != 15) {
a8561e35 1688 sfgt = 256 * 16 * (1 << sfgi); // startup frame guard time (SFGT) in 1/fc
47b78133 1689 NextTransferTime = MAX(NextTransferTime, Demod.endTime + (sfgt - DELAY_AIR2ARM_AS_READER - DELAY_ARM2AIR_AS_READER)/16);
1690 }
1691 }
1692 }
1693}
1694
1695
1696static int GetATQA(uint8_t *resp, uint8_t *resp_par) {
1697
a8561e35 1698#define WUPA_RETRY_TIMEOUT 10 // 10ms
47b78133 1699 uint8_t wupa[] = { 0x52 }; // 0x26 - REQA 0x52 - WAKE-UP
1700
1701 uint32_t save_iso14a_timeout = iso14a_get_timeout();
a8561e35 1702 iso14a_set_timeout(1236/(16*8)+1); // response to WUPA is expected at exactly 1236/fc. No need to wait longer.
1703
47b78133 1704 uint32_t start_time = GetTickCount();
1705 int len;
a8561e35 1706
47b78133 1707 // we may need several tries if we did send an unknown command or a wrong authentication before...
1708 do {
1709 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1710 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
1711 // Receive the ATQA
1712 len = ReaderReceive(resp, resp_par);
1713 } while (len == 0 && GetTickCount() <= start_time + WUPA_RETRY_TIMEOUT);
a8561e35 1714
47b78133 1715 iso14a_set_timeout(save_iso14a_timeout);
1716 return len;
1717}
1718
1719
de77d4ac 1720// performs iso14443a anticollision (optional) and card select procedure
1721// fills the uid and cuid pointer unless NULL
1722// fills the card info record unless NULL
a8561e35 1723// if anticollision is false, then the UID must be provided in uid_ptr[]
de77d4ac 1724// and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
c04a4b60 1725// requests ATS unless no_rats is true
1726int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades, bool no_rats) {
6a1f2d82 1727 uint8_t sel_all[] = { 0x93,0x20 };
1728 uint8_t sel_uid[] = { 0x93,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1729 uint8_t rats[] = { 0xE0,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
f71f4deb 1730 uint8_t resp[MAX_FRAME_SIZE]; // theoretically. A usual RATS will be much smaller
1731 uint8_t resp_par[MAX_PARITY_SIZE];
6a1f2d82 1732 byte_t uid_resp[4];
1733 size_t uid_resp_len;
1734
1735 uint8_t sak = 0x04; // cascade uid
1736 int cascade_level = 0;
1737 int len;
1738
618c220c
OM
1739 // init card struct
1740 if(p_hi14a_card) {
1741 p_hi14a_card->uidlen = 0;
1742 memset(p_hi14a_card->uid, 0, 10);
1743 p_hi14a_card->ats_len = 0;
1744 }
1745
47b78133 1746 if (!GetATQA(resp, resp_par)) {
1747 return 0;
1748 }
6a1f2d82 1749
1750 if(p_hi14a_card) {
1751 memcpy(p_hi14a_card->atqa, resp, 2);
6a1f2d82 1752 }
5f6d6c90 1753
de77d4ac 1754 if (anticollision) {
1755 // clear uid
1756 if (uid_ptr) {
1757 memset(uid_ptr,0,10);
1758 }
6a1f2d82 1759 }
79a73ab2 1760
ee1eadee 1761 // check for proprietary anticollision:
1762 if ((resp[0] & 0x1F) == 0) {
1763 return 3;
1764 }
a8561e35 1765
6a1f2d82 1766 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1767 // which case we need to make a cascade 2 request and select - this is a long UID
a8561e35 1768 // While the UID is not complete, the 3rd bit (from the right) is set in the SAK.
1769 for (; sak & 0x04; cascade_level++) {
6a1f2d82 1770 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1771 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1772
de77d4ac 1773 if (anticollision) {
1774 // SELECT_ALL
1775 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
fc52fbd4 1776 if (!ReaderReceive(resp, resp_par)) {
1777 return 0;
1778 }
de77d4ac 1779
a8561e35 1780 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
de77d4ac 1781 memset(uid_resp, 0, 4);
1782 uint16_t uid_resp_bits = 0;
1783 uint16_t collision_answer_offset = 0;
1784 // anti-collision-loop:
1785 while (Demod.collisionPos) {
1786 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
a8561e35 1787 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
de77d4ac 1788 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1789 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1790 }
a8561e35 1791 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
de77d4ac 1792 uid_resp_bits++;
1793 // construct anticollosion command:
a8561e35 1794 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
de77d4ac 1795 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1796 sel_uid[2+i] = uid_resp[i];
1797 }
1798 collision_answer_offset = uid_resp_bits%8;
1799 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
fc52fbd4 1800 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) {
1801 return 0;
1802 }
6a1f2d82 1803 }
de77d4ac 1804 // finally, add the last bits and BCC of the UID
1805 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1806 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1807 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
6a1f2d82 1808 }
de77d4ac 1809
a8561e35 1810 } else { // no collision, use the response to SELECT_ALL as current uid
de77d4ac 1811 memcpy(uid_resp, resp, 4);
e691fc45 1812 }
de77d4ac 1813 } else {
1814 if (cascade_level < num_cascades - 1) {
1815 uid_resp[0] = 0x88;
1816 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1817 } else {
1818 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
e691fc45 1819 }
6a1f2d82 1820 }
1821 uid_resp_len = 4;
5f6d6c90 1822
6a1f2d82 1823 // calculate crypto UID. Always use last 4 Bytes.
1824 if(cuid_ptr) {
1825 *cuid_ptr = bytes_to_num(uid_resp, 4);
1826 }
e30c654b 1827
6a1f2d82 1828 // Construct SELECT UID command
a8561e35 1829 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1830 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
1831 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1832 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
6a1f2d82 1833 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1834
1835 // Receive the SAK
fc52fbd4 1836 if (!ReaderReceive(resp, resp_par)) {
1837 return 0;
1838 }
6a1f2d82 1839 sak = resp[0];
a8561e35 1840
de77d4ac 1841 // Test if more parts of the uid are coming
6a1f2d82 1842 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1843 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1844 // http://www.nxp.com/documents/application_note/AN10927.pdf
6a1f2d82 1845 uid_resp[0] = uid_resp[1];
1846 uid_resp[1] = uid_resp[2];
a8561e35 1847 uid_resp[2] = uid_resp[3];
6a1f2d82 1848 uid_resp_len = 3;
1849 }
5f6d6c90 1850
de77d4ac 1851 if(uid_ptr && anticollision) {
6a1f2d82 1852 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1853 }
5f6d6c90 1854
6a1f2d82 1855 if(p_hi14a_card) {
1856 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1857 p_hi14a_card->uidlen += uid_resp_len;
1858 }
1859 }
79a73ab2 1860
6a1f2d82 1861 if(p_hi14a_card) {
1862 p_hi14a_card->sak = sak;
6a1f2d82 1863 }
534983d7 1864
7376da5c 1865 // PICC compilant with iso14443a-4 ---> (SAK & 0x20 != 0)
a8561e35 1866 if( (sak & 0x20) == 0) return 2;
534983d7 1867
c04a4b60 1868 if (!no_rats) {
1869 // Request for answer to select
1870 AppendCrc14443a(rats, 2);
1871 ReaderTransmit(rats, sizeof(rats), NULL);
1c611bbd 1872
fc52fbd4 1873 if (!(len = ReaderReceive(resp, resp_par))) {
1874 return 0;
1875 }
5191b3d1 1876
c04a4b60 1877 if(p_hi14a_card) {
1878 memcpy(p_hi14a_card->ats, resp, len);
1879 p_hi14a_card->ats_len = len;
1880 }
19a700a8 1881
c04a4b60 1882 // reset the PCB block number
1883 iso14_pcb_blocknum = 0;
19a700a8 1884
47b78133 1885 // set default timeout and delay next transfer based on ATS
1886 iso14a_set_ATS_times(resp);
a8561e35 1887
c04a4b60 1888 }
a8561e35 1889 return 1;
7e758047 1890}
15c4dc5a 1891
6e49717b 1892
7bc95e2e 1893void iso14443a_setup(uint8_t fpga_minor_mode) {
7cc204bf 1894 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
9492e0b0 1895 // Set up the synchronous serial port
6a5d4e17 1896 FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
7bc95e2e 1897 // connect Demodulated Signal to ADC:
7e758047 1898 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
e30c654b 1899
7e758047 1900 // Signal field is on with the appropriate LED
7bc95e2e 1901 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD
1902 || fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN) {
1903 LED_D_ON();
1904 } else {
1905 LED_D_OFF();
1906 }
1907 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
534983d7 1908
a8561e35 1909 // Set ADC to read field strength
1910 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1911 AT91C_BASE_ADC->ADC_MR =
1912 ADC_MODE_PRESCALE(63) |
1913 ADC_MODE_STARTUP_TIME(1) |
1914 ADC_MODE_SAMPLE_HOLD_TIME(15);
1915 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF_LOW);
1916
7bc95e2e 1917 // Start the timer
1918 StartCountSspClk();
a8561e35 1919
7bc95e2e 1920 DemodReset();
1921 UartReset();
a8561e35 1922 LastTimeProxToAirStart = 0;
1923 FpgaSendQueueDelay = 0;
1924 LastProxToAirDuration = 20; // arbitrary small value. Avoid lock in EmGetCmd()
7bc95e2e 1925 NextTransferTime = 2*DELAY_ARM2AIR_AS_READER;
6e49717b 1926 iso14a_set_timeout(1060); // 10ms default
7e758047 1927}
15c4dc5a 1928
ba4f95b4 1929/* Peter Fillmore 2015
1930Added card id field to the function
1931 info from ISO14443A standard
1932b1 = Block Number
1933b2 = RFU (always 1)
1934b3 = depends on block
1935b4 = Card ID following if set to 1
1936b5 = depends on block type
1937b6 = depends on block type
1938b7,b8 = block type.
1939Coding of I-BLOCK:
1940b8 b7 b6 b5 b4 b3 b2 b1
19410 0 0 x x x 1 x
1942b5 = chaining bit
1943Coding of R-block:
1944b8 b7 b6 b5 b4 b3 b2 b1
19451 0 1 x x 0 1 x
1946b5 = ACK/NACK
1947Coding of S-block:
1948b8 b7 b6 b5 b4 b3 b2 b1
a8561e35 19491 1 x x x 0 1 0
ba4f95b4 1950b5,b6 = 00 - DESELECT
a8561e35 1951 11 - WTX
1952*/
189b8177 1953int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, bool send_chaining, void *data, uint8_t *res) {
6a1f2d82 1954 uint8_t parity[MAX_PARITY_SIZE];
b7d3e899 1955 uint8_t real_cmd[cmd_len + 4];
a8561e35 1956
39cc1c87
OM
1957 if (cmd_len) {
1958 // ISO 14443 APDU frame: PCB [CID] [NAD] APDU CRC PCB=0x02
a8561e35 1959 real_cmd[0] = 0x02; // bnr,nad,cid,chn=0; i-block(0x00)
189b8177 1960 if (send_chaining) {
1961 real_cmd[0] |= 0x10;
1962 }
39cc1c87
OM
1963 // put block number into the PCB
1964 real_cmd[0] |= iso14_pcb_blocknum;
1965 memcpy(real_cmd + 1, cmd, cmd_len);
1966 } else {
1967 // R-block. ACK
a8561e35 1968 real_cmd[0] = 0xA2; // r-block + ACK
39cc1c87
OM
1969 real_cmd[0] |= iso14_pcb_blocknum;
1970 }
b7d3e899 1971 AppendCrc14443a(real_cmd, cmd_len + 1);
a8561e35 1972
b7d3e899 1973 ReaderTransmit(real_cmd, cmd_len + 3, NULL);
1974
6a1f2d82 1975 size_t len = ReaderReceive(data, parity);
1976 uint8_t *data_bytes = (uint8_t *) data;
b7d3e899 1977
1978 if (!len) {
b0127e65 1979 return 0; //DATA LINK ERROR
a8561e35 1980 } else {
1981 // S-Block WTX
1982 while (len && ((data_bytes[0] & 0xF2) == 0xF2)) {
7c7327e7 1983 uint32_t save_iso14a_timeout = iso14a_get_timeout();
db68bcdb 1984 // temporarily increase timeout
7c7327e7 1985 iso14a_set_timeout(MAX((data_bytes[1] & 0x3f) * save_iso14a_timeout, MAX_ISO14A_TIMEOUT));
a8561e35 1986 // Transmit WTX back
a63505c9 1987 // byte1 - WTXM [1..59]. command FWT=FWT*WTXM
1988 data_bytes[1] = data_bytes[1] & 0x3f; // 2 high bits mandatory set to 0b
1989 // now need to fix CRC.
1990 AppendCrc14443a(data_bytes, len - 2);
1991 // transmit S-Block
1992 ReaderTransmit(data_bytes, len, NULL);
a8561e35 1993 // retrieve the result again (with increased timeout)
a63505c9 1994 len = ReaderReceive(data, parity);
1995 data_bytes = data;
db68bcdb 1996 // restore timeout
7c7327e7 1997 iso14a_set_timeout(save_iso14a_timeout);
a63505c9 1998 }
1999
2000 // if we received an I- or R(ACK)-Block with a block number equal to the
2001 // current block number, toggle the current block number
b7d3e899 2002 if (len >= 3 // PCB+CRC = 3 bytes
a8561e35 2003 && ((data_bytes[0] & 0xC0) == 0 // I-Block
2004 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2005 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
b7d3e899 2006 {
2007 iso14_pcb_blocknum ^= 1;
2008 }
a8561e35 2009
39cc1c87
OM
2010 // if we received I-block with chaining we need to send ACK and receive another block of data
2011 if (res)
2012 *res = data_bytes[0];
b0127e65 2013
b7d3e899 2014 // crc check
39cc1c87 2015 if (len >= 3 && !CheckCrc14443(CRC_14443_A, data_bytes, len)) {
b7d3e899 2016 return -1;
2017 }
a8561e35 2018
b7d3e899 2019 }
a8561e35 2020
c719d385
OM
2021 if (len) {
2022 // cut frame byte
2023 len -= 1;
2024 // memmove(data_bytes, data_bytes + 1, len);
2025 for (int i = 0; i < len; i++)
2026 data_bytes[i] = data_bytes[i + 1];
2027 }
a8561e35 2028
534983d7 2029 return len;
2030}
2031
6e49717b 2032
7e758047 2033//-----------------------------------------------------------------------------
2034// Read an ISO 14443a tag. Send out commands and store answers.
2035//
2036//-----------------------------------------------------------------------------
7bc95e2e 2037void ReaderIso14443a(UsbCommand *c)
7e758047 2038{
534983d7 2039 iso14a_command_t param = c->arg[0];
7bc95e2e 2040 uint8_t *cmd = c->d.asBytes;
04bc1c66 2041 size_t len = c->arg[1] & 0xffff;
2042 size_t lenbits = c->arg[1] >> 16;
2043 uint32_t timeout = c->arg[2];
9492e0b0 2044 uint32_t arg0 = 0;
618c220c 2045 byte_t buf[USB_CMD_DATA_SIZE] = {0};
6a1f2d82 2046 uint8_t par[MAX_PARITY_SIZE];
f1a983a3 2047 bool cantSELECT = false;
a8561e35 2048
eb6e8de4 2049 set_tracing(true);
a8561e35 2050
eb6e8de4 2051 if(param & ISO14A_CLEAR_TRACE) {
3000dc4e 2052 clear_trace();
5f6d6c90 2053 }
e691fc45 2054
79a73ab2 2055 if(param & ISO14A_REQUEST_TRIGGER) {
de77d4ac 2056 iso14a_set_trigger(true);
9492e0b0 2057 }
15c4dc5a 2058
534983d7 2059 if(param & ISO14A_CONNECT) {
f1a983a3 2060 LED_A_ON();
7bc95e2e 2061 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
5f6d6c90 2062 if(!(param & ISO14A_NO_SELECT)) {
2063 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
c04a4b60 2064 arg0 = iso14443a_select_card(NULL, card, NULL, true, 0, param & ISO14A_NO_RATS);
f1a983a3 2065
2066 // if we cant select then we cant send data
499df908 2067 if (arg0 != 1 && arg0 != 2) {
2068 // 1 - all is OK with ATS, 2 - without ATS
2069 cantSELECT = true;
2070 }
fc52fbd4 2071 FpgaDisableTracing();
f1a983a3 2072 LED_B_ON();
5f6d6c90 2073 cmd_send(CMD_ACK,arg0,card->uidlen,0,buf,sizeof(iso14a_card_select_t));
f1a983a3 2074 LED_B_OFF();
5f6d6c90 2075 }
534983d7 2076 }
e30c654b 2077
534983d7 2078 if(param & ISO14A_SET_TIMEOUT) {
04bc1c66 2079 iso14a_set_timeout(timeout);
534983d7 2080 }
e30c654b 2081
f1a983a3 2082 if(param & ISO14A_APDU && !cantSELECT) {
39cc1c87 2083 uint8_t res;
189b8177 2084 arg0 = iso14_apdu(cmd, len, (param & ISO14A_SEND_CHAINING), buf, &res);
fc52fbd4 2085 FpgaDisableTracing();
f1a983a3 2086 LED_B_ON();
39cc1c87 2087 cmd_send(CMD_ACK, arg0, res, 0, buf, sizeof(buf));
f1a983a3 2088 LED_B_OFF();
534983d7 2089 }
e30c654b 2090
f1a983a3 2091 if(param & ISO14A_RAW && !cantSELECT) {
534983d7 2092 if(param & ISO14A_APPEND_CRC) {
48ece4a7 2093 if(param & ISO14A_TOPAZMODE) {
2094 AppendCrc14443b(cmd,len);
2095 } else {
2096 AppendCrc14443a(cmd,len);
2097 }
534983d7 2098 len += 2;
c7324bef 2099 if (lenbits) lenbits += 16;
15c4dc5a 2100 }
a8561e35 2101 if(lenbits>0) { // want to send a specific number of bits (e.g. short commands)
48ece4a7 2102 if(param & ISO14A_TOPAZMODE) {
2103 int bits_to_send = lenbits;
2104 uint16_t i = 0;
a8561e35 2105 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
48ece4a7 2106 bits_to_send -= 7;
2107 while (bits_to_send > 0) {
a8561e35 2108 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
48ece4a7 2109 bits_to_send -= 8;
2110 }
2111 } else {
2112 GetParity(cmd, lenbits/8, par);
a8561e35 2113 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
48ece4a7 2114 }
a8561e35 2115 } else { // want to send complete bytes only
48ece4a7 2116 if(param & ISO14A_TOPAZMODE) {
2117 uint16_t i = 0;
a8561e35 2118 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
48ece4a7 2119 while (i < len) {
a8561e35 2120 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
48ece4a7 2121 }
2122 } else {
a8561e35 2123 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
48ece4a7 2124 }
5f6d6c90 2125 }
6a1f2d82 2126 arg0 = ReaderReceive(buf, par);
fc52fbd4 2127 FpgaDisableTracing();
f1a983a3 2128
2129 LED_B_ON();
9492e0b0 2130 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
f1a983a3 2131 LED_B_OFF();
534983d7 2132 }
15c4dc5a 2133
79a73ab2 2134 if(param & ISO14A_REQUEST_TRIGGER) {
de77d4ac 2135 iso14a_set_trigger(false);
9492e0b0 2136 }
15c4dc5a 2137
79a73ab2 2138 if(param & ISO14A_NO_DISCONNECT) {
534983d7 2139 return;
9492e0b0 2140 }
15c4dc5a 2141
15c4dc5a 2142 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2143 LEDsoff();
15c4dc5a 2144}
b0127e65 2145
1c611bbd 2146
1c611bbd 2147// Determine the distance between two nonces.
2148// Assume that the difference is small, but we don't know which is first.
2149// Therefore try in alternating directions.
6e49717b 2150static int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
1c611bbd 2151
2152 uint16_t i;
2153 uint32_t nttmp1, nttmp2;
e772353f 2154
1c611bbd 2155 if (nt1 == nt2) return 0;
2156
2157 nttmp1 = nt1;
2158 nttmp2 = nt2;
a8561e35 2159
1c611bbd 2160 for (i = 1; i < 32768; i++) {
2161 nttmp1 = prng_successor(nttmp1, 1);
2162 if (nttmp1 == nt2) return i;
2163 nttmp2 = prng_successor(nttmp2, 1);
dc8ba239 2164 if (nttmp2 == nt1) return -i;
1c611bbd 2165 }
a8561e35 2166
1c611bbd 2167 return(-99999); // either nt1 or nt2 are invalid nonces
e772353f 2168}
2169
e772353f 2170
1c611bbd 2171//-----------------------------------------------------------------------------
2172// Recover several bits of the cypher stream. This implements (first stages of)
2173// the algorithm described in "The Dark Side of Security by Obscurity and
2174// Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2175// (article by Nicolas T. Courtois, 2009)
2176//-----------------------------------------------------------------------------
2177void ReaderMifare(bool first_try)
2178{
2179 // Mifare AUTH
2180 uint8_t mf_auth[] = { 0x60,0x00,0xf5,0x7b };
2181 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2182 static uint8_t mf_nr_ar3;
e772353f 2183
f71f4deb 2184 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE];
2185 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE];
7bc95e2e 2186
664e132f 2187 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
a8561e35 2188
f71f4deb 2189 // free eventually allocated BigBuf memory. We want all for tracing.
2190 BigBuf_free();
a8561e35 2191
3000dc4e 2192 clear_trace();
de77d4ac 2193 set_tracing(true);
e772353f 2194
664e132f 2195 uint8_t nt_diff = 0;
a8561e35 2196 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
664e132f 2197 static uint8_t par_low = 0;
de77d4ac 2198 bool led_on = true;
ca4714cd 2199 uint8_t uid[10] ={0};
1c611bbd 2200 uint32_t cuid;
e772353f 2201
6a1f2d82 2202 uint32_t nt = 0;
2ed270a8 2203 uint32_t previous_nt = 0;
1c611bbd 2204 static uint32_t nt_attacked = 0;
664e132f 2205 uint8_t par_list[8] = {0x00};
2206 uint8_t ks_list[8] = {0x00};
e772353f 2207
dfb387bf 2208 #define PRNG_SEQUENCE_LENGTH (1 << 16);
664e132f 2209 uint32_t sync_time = GetCountSspClk() & 0xfffffff8;
8c6b2298 2210 static int32_t sync_cycles;
1c611bbd 2211 int catch_up_cycles = 0;
2212 int last_catch_up = 0;
8c6b2298 2213 uint16_t elapsed_prng_sequences;
1c611bbd 2214 uint16_t consecutive_resyncs = 0;
2215 int isOK = 0;
e772353f 2216
a8561e35 2217 if (first_try) {
1c611bbd 2218 mf_nr_ar3 = 0;
664e132f 2219 par[0] = par_low = 0;
a8561e35 2220 sync_cycles = PRNG_SEQUENCE_LENGTH; // theory: Mifare Classic's random generator repeats every 2^16 cycles (and so do the tag nonces).
1c611bbd 2221 nt_attacked = 0;
1c611bbd 2222 }
2223 else {
2224 // we were unsuccessful on a previous call. Try another READER nonce (first 3 parity bits remain the same)
1c611bbd 2225 mf_nr_ar3++;
2226 mf_nr_ar[3] = mf_nr_ar3;
6a1f2d82 2227 par[0] = par_low;
1c611bbd 2228 }
e30c654b 2229
15c4dc5a 2230 LED_A_ON();
2231 LED_B_OFF();
2232 LED_C_OFF();
dc8ba239 2233
a8561e35 2234
2235 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2236 #define MAX_SYNC_TRIES 32
2237 #define SYNC_TIME_BUFFER 16 // if there is only SYNC_TIME_BUFFER left before next planned sync, wait for next PRNG cycle
2238 #define NUM_DEBUG_INFOS 8 // per strategy
2239 #define MAX_STRATEGY 3
dfb387bf 2240 uint16_t unexpected_random = 0;
2241 uint16_t sync_tries = 0;
2242 int16_t debug_info_nr = -1;
8c6b2298 2243 uint16_t strategy = 0;
2244 int32_t debug_info[MAX_STRATEGY][NUM_DEBUG_INFOS];
2245 uint32_t select_time;
2246 uint32_t halt_time;
a8561e35 2247
2248 for (uint16_t i = 0; true; i++) {
2249
dc8ba239 2250 LED_C_ON();
1c611bbd 2251 WDT_HIT();
e30c654b 2252
1c611bbd 2253 // Test if the action was cancelled
2254 if(BUTTON_PRESS()) {
dc8ba239 2255 isOK = -1;
1c611bbd 2256 break;
2257 }
a8561e35 2258
8c6b2298 2259 if (strategy == 2) {
2260 // test with additional hlt command
2261 halt_time = 0;
2262 int len = mifare_sendcmd_short(NULL, false, 0x50, 0x00, receivedAnswer, receivedAnswerPar, &halt_time);
2263 if (len && MF_DBGLEVEL >= 3) {
2264 Dbprintf("Unexpected response of %d bytes to hlt command (additional debugging).", len);
2265 }
2266 }
2267
2268 if (strategy == 3) {
2269 // test with FPGA power off/on
2270 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2271 SpinDelay(200);
2272 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2273 SpinDelay(100);
2274 }
a8561e35 2275
c04a4b60 2276 if(!iso14443a_select_card(uid, NULL, &cuid, true, 0, true)) {
a8561e35 2277 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Can't select card");
1c611bbd 2278 continue;
2279 }
8c6b2298 2280 select_time = GetCountSspClk();
1c611bbd 2281
8c6b2298 2282 elapsed_prng_sequences = 1;
dfb387bf 2283 if (debug_info_nr == -1) {
2284 sync_time = (sync_time & 0xfffffff8) + sync_cycles + catch_up_cycles;
2285 catch_up_cycles = 0;
1c611bbd 2286
664e132f 2287 // if we missed the sync time already or are about to miss it, advance to the next nonce repeat
2288 while(sync_time < GetCountSspClk() + SYNC_TIME_BUFFER) {
8c6b2298 2289 elapsed_prng_sequences++;
dfb387bf 2290 sync_time = (sync_time & 0xfffffff8) + sync_cycles;
2291 }
e30c654b 2292
a8561e35 2293 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
dfb387bf 2294 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2295 } else {
8c6b2298 2296 // collect some information on tag nonces for debugging:
a8561e35 2297 #define DEBUG_FIXED_SYNC_CYCLES PRNG_SEQUENCE_LENGTH
8c6b2298 2298 if (strategy == 0) {
2299 // nonce distances at fixed time after card select:
2300 sync_time = select_time + DEBUG_FIXED_SYNC_CYCLES;
2301 } else if (strategy == 1) {
2302 // nonce distances at fixed time between authentications:
2303 sync_time = sync_time + DEBUG_FIXED_SYNC_CYCLES;
2304 } else if (strategy == 2) {
2305 // nonce distances at fixed time after halt:
2306 sync_time = halt_time + DEBUG_FIXED_SYNC_CYCLES;
2307 } else {
2308 // nonce_distances at fixed time after power on
2309 sync_time = DEBUG_FIXED_SYNC_CYCLES;
2310 }
2311 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
a8561e35 2312 }
f89c7050 2313
1c611bbd 2314 // Receive the (4 Byte) "random" nonce
6a1f2d82 2315 if (!ReaderReceive(receivedAnswer, receivedAnswerPar)) {
a8561e35 2316 if (MF_DBGLEVEL >= 1) Dbprintf("Mifare: Couldn't receive tag nonce");
1c611bbd 2317 continue;
2318 }
2319
1c611bbd 2320 previous_nt = nt;
2321 nt = bytes_to_num(receivedAnswer, 4);
2322
2323 // Transmit reader nonce with fake par
9492e0b0 2324 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
1c611bbd 2325
2326 if (first_try && previous_nt && !nt_attacked) { // we didn't calibrate our clock yet
2327 int nt_distance = dist_nt(previous_nt, nt);
2328 if (nt_distance == 0) {
2329 nt_attacked = nt;
dfb387bf 2330 } else {
dc8ba239 2331 if (nt_distance == -99999) { // invalid nonce received
dfb387bf 2332 unexpected_random++;
8c6b2298 2333 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
a8561e35 2334 isOK = -3; // Card has an unpredictable PRNG. Give up
dc8ba239 2335 break;
2336 } else {
a8561e35 2337 continue; // continue trying...
dc8ba239 2338 }
1c611bbd 2339 }
dfb387bf 2340 if (++sync_tries > MAX_SYNC_TRIES) {
8c6b2298 2341 if (strategy > MAX_STRATEGY || MF_DBGLEVEL < 3) {
a8561e35 2342 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
dfb387bf 2343 break;
a8561e35 2344 } else { // continue for a while, just to collect some debug info
8c6b2298 2345 debug_info[strategy][debug_info_nr] = nt_distance;
2346 debug_info_nr++;
2347 if (debug_info_nr == NUM_DEBUG_INFOS) {
2348 strategy++;
2349 debug_info_nr = 0;
2350 }
dfb387bf 2351 continue;
2352 }
2353 }
8c6b2298 2354 sync_cycles = (sync_cycles - nt_distance/elapsed_prng_sequences);
dfb387bf 2355 if (sync_cycles <= 0) {
2356 sync_cycles += PRNG_SEQUENCE_LENGTH;
2357 }
2358 if (MF_DBGLEVEL >= 3) {
8c6b2298 2359 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
dfb387bf 2360 }
1c611bbd 2361 continue;
2362 }
2363 }
2364
a8561e35 2365 if ((nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
1c611bbd 2366 catch_up_cycles = -dist_nt(nt_attacked, nt);
a8561e35 2367 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
1c611bbd 2368 catch_up_cycles = 0;
2369 continue;
2370 }
8c6b2298 2371 catch_up_cycles /= elapsed_prng_sequences;
1c611bbd 2372 if (catch_up_cycles == last_catch_up) {
2373 consecutive_resyncs++;
2374 }
2375 else {
2376 last_catch_up = catch_up_cycles;
a8561e35 2377 consecutive_resyncs = 0;
1c611bbd 2378 }
2379 if (consecutive_resyncs < 3) {
9492e0b0 2380 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, -catch_up_cycles, consecutive_resyncs);
1c611bbd 2381 }
a8561e35 2382 else {
1c611bbd 2383 sync_cycles = sync_cycles + catch_up_cycles;
9492e0b0 2384 if (MF_DBGLEVEL >= 3) Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, -catch_up_cycles, sync_cycles);
8c6b2298 2385 last_catch_up = 0;
2386 catch_up_cycles = 0;
2387 consecutive_resyncs = 0;
1c611bbd 2388 }
2389 continue;
2390 }
a8561e35 2391
1c611bbd 2392 consecutive_resyncs = 0;
a8561e35 2393
1c611bbd 2394 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
8c6b2298 2395 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
a8561e35 2396 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2397
8c6b2298 2398 if (nt_diff == 0) {
6a1f2d82 2399 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
1c611bbd 2400 }
2401
2402 led_on = !led_on;
2403 if(led_on) LED_B_ON(); else LED_B_OFF();
2404
6a1f2d82 2405 par_list[nt_diff] = SwapBits(par[0], 8);
1c611bbd 2406 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05;
2407
2408 // Test if the information is complete
2409 if (nt_diff == 0x07) {
2410 isOK = 1;
2411 break;
2412 }
2413
2414 nt_diff = (nt_diff + 1) & 0x07;
2415 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
6a1f2d82 2416 par[0] = par_low;
1c611bbd 2417 } else {
2418 if (nt_diff == 0 && first_try)
2419 {
6a1f2d82 2420 par[0]++;
a8561e35 2421 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
dc8ba239 2422 isOK = -2;
2423 break;
2424 }
1c611bbd 2425 } else {
6a1f2d82 2426 par[0] = ((par[0] & 0x1F) + 1) | par_low;
1c611bbd 2427 }
2428 }
2429 }
2430
1c611bbd 2431
2432 mf_nr_ar[3] &= 0x1F;
dfb387bf 2433
2434 if (isOK == -4) {
2435 if (MF_DBGLEVEL >= 3) {
8c6b2298 2436 for (uint16_t i = 0; i <= MAX_STRATEGY; i++) {
a8561e35 2437 for (uint16_t j = 0; j < NUM_DEBUG_INFOS; j++) {
8c6b2298 2438 Dbprintf("collected debug info[%d][%d] = %d", i, j, debug_info[i][j]);
2439 }
dfb387bf 2440 }
2441 }
2442 }
a8561e35 2443
fc52fbd4 2444 FpgaDisableTracing();
2445
664e132f 2446 uint8_t buf[32];
1c611bbd 2447 memcpy(buf + 0, uid, 4);
2448 num_to_bytes(nt, 4, buf + 4);
2449 memcpy(buf + 8, par_list, 8);
2450 memcpy(buf + 16, ks_list, 8);
664e132f 2451 memcpy(buf + 24, mf_nr_ar, 8);
a8561e35 2452
664e132f 2453 cmd_send(CMD_ACK, isOK, 0, 0, buf, 32);
1c611bbd 2454
2455 // Thats it...
2456 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2457 LEDsoff();
7bc95e2e 2458
de77d4ac 2459 set_tracing(false);
20f9a2a1 2460}
1c611bbd 2461
d2f487af 2462
b62a5a84 2463//-----------------------------------------------------------------------------
a8561e35 2464// MIFARE sniffer.
2465//
b62a5a84 2466//-----------------------------------------------------------------------------
5cd9ec01
M
2467void RAMFUNC SniffMifare(uint8_t param) {
2468 // param:
2469 // bit 0 - trigger from first card answer
2470 // bit 1 - trigger from first reader 7-bit request
39864b0b
M
2471
2472 // C(red) A(yellow) B(green)
b62a5a84 2473 LEDsoff();
1523527f 2474 LED_A_ON();
a8561e35 2475
b62a5a84 2476 // init trace buffer
3000dc4e 2477 clear_trace();
de77d4ac 2478 set_tracing(true);
b62a5a84 2479
b62a5a84
M
2480 // The command (reader -> tag) that we're receiving.
2481 // The length of a received command will in most cases be no more than 18 bytes.
2482 // So 32 should be enough!
f71f4deb 2483 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE];
2484 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE];
b62a5a84 2485 // The response (tag -> reader) that we're receiving.
f71f4deb 2486 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE];
2487 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE];
b62a5a84 2488
09ffd16e 2489 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
2490
f71f4deb 2491 // free eventually allocated BigBuf memory
2492 BigBuf_free();
2493 // allocate the DMA buffer, used to stream samples from the FPGA
2494 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
7bc95e2e 2495 uint8_t *data = dmaBuf;
2496 uint8_t previous_data = 0;
5cd9ec01
M
2497 int maxDataLen = 0;
2498 int dataLen = 0;
de77d4ac 2499 bool ReaderIsActive = false;
2500 bool TagIsActive = false;
7bc95e2e 2501
b62a5a84 2502 // Set up the demodulator for tag -> reader responses.
6a1f2d82 2503 DemodInit(receivedResponse, receivedResponsePar);
b62a5a84
M
2504
2505 // Set up the demodulator for the reader -> tag commands
6a1f2d82 2506 UartInit(receivedCmd, receivedCmdPar);
b62a5a84
M
2507
2508 // Setup for the DMA.
7bc95e2e 2509 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
b62a5a84 2510
39864b0b
M
2511 // init sniffer
2512 MfSniffInit();
b62a5a84 2513
b62a5a84 2514 // And now we loop, receiving samples.
a8561e35 2515 for (uint32_t sniffCounter = 0; true; ) {
2516
5cd9ec01 2517 if(BUTTON_PRESS()) {
8ec06f5e 2518 DbpString("Canceled by button.");
7bc95e2e 2519 break;
5cd9ec01
M
2520 }
2521
b62a5a84 2522 WDT_HIT();
a8561e35 2523
2524 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
7bc95e2e 2525 // check if a transaction is completed (timeout after 2000ms).
2526 // if yes, stop the DMA transfer and send what we have so far to the client
a8561e35 2527 if (MfSniffSend(2000)) {
7bc95e2e 2528 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
2529 sniffCounter = 0;
2530 data = dmaBuf;
2531 maxDataLen = 0;
de77d4ac 2532 ReaderIsActive = false;
2533 TagIsActive = false;
7bc95e2e 2534 FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE); // set transfer address and number of bytes. Start transfer.
39864b0b 2535 }
39864b0b 2536 }
a8561e35 2537
2538 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
7bc95e2e 2539 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
a8561e35 2540 if (readBufDataP <= dmaBufDataP){ // we are processing the same block of data which is currently being transferred
2541 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
2542 } else {
7bc95e2e 2543 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
5cd9ec01
M
2544 }
2545 // test for length of buffer
a8561e35 2546 if(dataLen > maxDataLen) { // we are more behind than ever...
2547 maxDataLen = dataLen;
f71f4deb 2548 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
5cd9ec01 2549 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
7bc95e2e 2550 break;
b62a5a84
M
2551 }
2552 }
5cd9ec01 2553 if(dataLen < 1) continue;
b62a5a84 2554
7bc95e2e 2555 // primary buffer was stopped ( <-- we lost data!
5cd9ec01
M
2556 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
2557 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
2558 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
55acbb2a 2559 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
5cd9ec01
M
2560 }
2561 // secondary buffer sets as primary, secondary buffer was stopped
2562 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
2563 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
b62a5a84
M
2564 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
2565 }
5cd9ec01 2566
7bc95e2e 2567 if (sniffCounter & 0x01) {
b62a5a84 2568
a8561e35 2569 if(!TagIsActive) { // no need to try decoding tag data if the reader is sending
7bc95e2e 2570 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
2571 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
feb328c9 2572
de77d4ac 2573 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, true)) break;
b62a5a84 2574
7bc95e2e 2575 /* And ready to receive another command. */
05ddb52c 2576 UartInit(receivedCmd, receivedCmdPar);
a8561e35 2577
7bc95e2e 2578 /* And also reset the demod code */
2579 DemodReset();
2580 }
2581 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
2582 }
a8561e35 2583
2584 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending
7bc95e2e 2585 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
2586 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
b62a5a84 2587
de77d4ac 2588 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, false)) break;
39864b0b 2589
7bc95e2e 2590 // And ready to receive another response.
2591 DemodReset();
48ece4a7 2592 // And reset the Miller decoder including its (now outdated) input buffer
2593 UartInit(receivedCmd, receivedCmdPar);
7bc95e2e 2594 }
2595 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
2596 }
b62a5a84
M
2597 }
2598
7bc95e2e 2599 previous_data = *data;
2600 sniffCounter++;
5cd9ec01 2601 data++;
d714d3ef 2602 if(data == dmaBuf + DMA_BUFFER_SIZE) {
5cd9ec01 2603 data = dmaBuf;
b62a5a84 2604 }
7bc95e2e 2605
b62a5a84
M
2606 } // main cycle
2607
ca8a3478 2608 FpgaDisableTracing();
1523527f 2609 FpgaDisableSscDma();
2610 LEDsoff();
2611
8ec06f5e 2612 DbpString("COMMAND FINISHED.");
b62a5a84 2613
39864b0b 2614 MfSniffEnd();
a8561e35 2615
7bc95e2e 2616 Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3803d529 2617}
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