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raggedstone
2007-03-18
michael
UseHighz for programming the spartan 3, as programming...
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2007-03-14
michael
create device node
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2007-03-11
michael
revert previous Makefile commit, delete *.cdc files...
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2007-03-11
michael
working vio
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2007-03-11
michael
watch vio out on LED
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2007-03-11
michael
add cable help
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2007-03-11
michael
add vio to trigger an interrupt from chipscope (doesn...
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2007-03-11
sithglan
more to ignore
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2007-03-11
sithglan
md5sum
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2007-03-11
michael
rename ports
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2007-03-11
sithglan
load driver automatically if not loaded
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2007-03-11
sithglan
perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1...
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2007-03-11
michael
interrupt
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2007-03-11
michael
PCI_IDSEL as trigger
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2007-03-11
sithglan
test target
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2007-03-11
michael
bugfix
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2007-03-11
michael
IDSEL
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2007-03-11
sithglan
rollback
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2007-03-11
sithglan
get rid of vergleich
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2007-03-11
sithglan
this file is no longer autogenerated
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2007-03-11
sithglan
cleanup config space
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2007-03-11
sithglan
more merging
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2007-03-11
sithglan
gone
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2007-03-11
sithglan
even more consolidation
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2007-03-11
sithglan
consolidate more
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2007-03-11
sithglan
etnerprise level consolidation
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2007-03-11
sithglan
merge config space
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2007-03-11
sithglan
begin to merge confi space
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2007-03-11
sithglan
shut the fuck up
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2007-03-11
michael
really fix deps
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2007-03-11
michael
fix dependencies
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2007-03-11
sithglan
perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1...
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2007-03-11
sithglan
Adding a test bench back that isn't a test bench. ...
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2007-03-11
sithglan
all files to lowercase,
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2007-03-11
sithglan
move config space header into pci core directory
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2007-03-11
sithglan
identing
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2007-03-11
sithglan
coding style
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2007-03-11
sithglan
move, ident
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2007-03-11
sithglan
dos2unix *.vhd
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2007-03-11
sithglan
move address register
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2007-03-11
michael
name ports
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2007-03-11
michael
more LA signals
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2007-03-11
michael
add analyzer target
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2007-03-10
michael
add PCI_nREQ
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2007-03-10
sithglan
+= userland
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2007-03-10
sithglan
+= driver
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2007-03-10
michael
cleaner
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2007-03-10
michael
cleanup after coregen
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2007-03-10
michael
missing renames...
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2007-03-10
michael
rename fifo to dhwk_fifo
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2007-03-10
michael
don't rewrite .xco all the time
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2007-03-10
michael
make clean makes really clean now
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2007-03-10
michael
remove build fifo, ila and icon
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2007-03-10
michael
chipscope
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2007-03-10
michael
trigger
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2007-03-10
sithglan
cleanup
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2007-03-10
sithglan
code cleanup
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2007-03-10
michael
CBEn
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2007-03-10
michael
larger ila
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2007-03-10
michael
level
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2007-03-10
michael
updated chipscope project
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2007-03-10
michael
-fifo_control stuff
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2007-03-10
michael
irgendwie gehts
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2007-03-10
michael
now we only lose half the bytes
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2007-03-10
michael
other watched signals
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2007-03-10
sithglan
interrupt scheisse
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2007-03-10
michael
not not
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2007-03-10
michael
chipscope
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2007-03-10
michael
?
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2007-03-10
michael
invert interrupt
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2007-03-10
michael
loopback
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2007-03-10
michael
fifo
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2007-03-10
michael
add ven_rev_id
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2007-03-10
sithglan
*** empty log message ***
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2007-03-10
michael
ucf
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2007-03-10
michael
it synthesizes
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2007-03-10
sithglan
first import of dhwk.
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2007-03-08
michael
connect LEDs on IDE board to main FPGA and let them...
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2007-03-05
michael
add sources for ide daughterboard cpld
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2007-03-03
michael
use rising_edge(clk_i)
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2007-02-25
michael
make load DRIVER=/home/michael/Raggedstone/usb-driver...
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2007-02-14
sithglan
+= Installationsanweisungen
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2007-02-13
michael
running light ;-)
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2007-02-11
michael
we_o
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2007-02-11
michael
first error fixed
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2007-02-11
michael
verdrahtung
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2007-02-11
sithglan
do something with the fifo stuff
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2007-02-11
sithglan
typos
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2007-02-11
sithglan
fifos
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2007-02-11
sithglan
more fifo work
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2007-02-11
michael
old 7seg thingie
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2007-02-11
michael
-dpram component
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2007-02-11
sithglan
-= comments
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2007-02-11
michael
fix address width
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2007-02-11
sithglan
more infra
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2007-02-11
michael
semicolon
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2007-02-11
michael
component for dram
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2007-02-11
sithglan
define xilinix and fpga
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2007-02-11
sithglan
make it compile
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2007-02-11
sithglan
+= glue code wb fifo
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